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</style></HEAD><BODY align="left" style='background-color: #ffffff;'><DIV align="left"><TABLE width="95%" border=0 cellpadding=2><TR><TD><TABLE cellpadding=2 border=0 ><TR><WIZARD></WIZARD><TD><H1>Generation Report - Reed-Solomon Compiler v18.0</H1></TD></TR></TABLE></TD></TR><TR><TD><TABLE cellpadding=2 border=1 width="60%"><TR><TD><B>Entity Name</B></TD><TD>auk_rs_dec_top_atl</TD></TR><TR><TD><B>Variation Name</B></TD><TD>RS_DE_LANE_QUATUS</TD></TR><TR><TD><B>Variation HDL</B></TD><TD>Verilog HDL</TD></TR><TR><TD><B>Output Directory</B></TD><TD>C:\Users\Administrator\Desktop\vlc_m_8x_syn\7_vlc_m_8x_syn_quatus_e6_tx_rx</TD></TR></TABLE></TD></TR><TR><TD><h2>File Summary</h2>The MegaWizard interface is creating the following files in the output directory:</TD></TR><TR><TD><TABLE cellspacing=2 cellpadding=2 border=1 width="100%"><TR align="left"><TH align="left" align="top" width="25%"><B>File</B></TH><TH align="left"><B>Description</B></TH></TR><TR><TD>RS_DE_LANE_QUATUS_testbench.v</TD><TD>Testbench File.</TD></TR><TR><TD>RS_DE_LANE_QUATUS_vsim_script.tcl</TD><TD>TCL Script.</TD></TR><TR><TD>RS_DE_LANE_QUATUS_nativelink.tcl</TD><TD>TCL Script for nativelink simulation.</TD></TR><TR><TD>RS_DE_LANE_QUATUS_encoded_data.txt</TD><TD>Testbench Simulation Data.</TD></TR><TR><TD>RS_DE_LANE_QUATUS_block_period_stim.txt</TD><TD>Testbench Simulation Data.</TD></TR><TR><TD>RS_DE_LANE_QUATUS.v</TD><TD>A MegaCore<small><sup>®</sup></small> function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus Prime software.</TD></TR><TR><TD>RS_DE_LANE_QUATUS_bb.v</TD><TD>Verilog HDL black-box file for the MegaCore function variation. Use this file when using a third-party EDA tool to synthesize your design.</TD></TR><TR><TD>RS_DE_LANE_QUATUS.bsf</TD><TD>Quartus<small><sup>®</sup></small> II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor.</TD></TR><TR><TD>RS_DE_LANE_QUATUS.vo</TD><TD>Verilog HDL IP functional simulation model</TD></TR><TR><TD>RS_DE_LANE_QUATUS_syn.v</TD><TD>A timing and resource estimation netlist for use in some third-party synthesis tools.</TD></TR><TR><TD>RS_DE_LANE_QUATUS.qip</TD><TD>Contains Quartus Prime project information for your MegaCore function variation.</TD></TR><TR><TD>RS_DE_LANE_QUATUS.html</TD><TD>The MegaCore function report file.</TD></TR></TABLE></TD></TR><TR><TD><h2>MegaCore Function Variation File Ports</h2><TABLE border=1 cellpadding=2 cellspacing=0 width="75%"><TR align="left"><TH align="left"><B>Name</B></TH><TH align="left"><B>Direction</B></TH><TH align="left"><B>Width</B></TH></TR><TR><TD>clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>reset</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>rsin</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>rsout</TD><TD>OUTPUT</TD><TD>8</TD></TR><TR><TD>sink_ena</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>sink_val</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>sink_sop</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>sink_eop</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>source_ena</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>source_val</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>source_sop</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>source_eop</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>decfail</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>bypass</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>num_err_sym</TD><TD>OUTPUT</TD><TD>4</TD></TR><TR><TD>rserr</TD><TD>OUTPUT</TD><TD>8</TD></TR></TABLE></TD></TR></TD></TR></TABLE></DIV></BODY></HTML>