Skip to content
View Ken0123456789's full-sized avatar

Block or report Ken0123456789

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

Small footprint and configurable PCIe core

Python 695 163 Updated May 22, 2026

The RIFFA development repository

Verilog 874 346 Updated Jun 11, 2024

Verilog PCI express components

Verilog 1,602 410 Updated Apr 26, 2024

Must-have verilog systemverilog modules

Verilog 1,962 418 Updated Mar 12, 2026

Verilog AXI components for FPGA implementation

Verilog 2,055 531 Updated Feb 27, 2025

Verilog Ethernet components for FPGA implementation

Verilog 2,964 827 Updated Feb 27, 2025

A DDR3 memory controller in Verilog for various FPGAs

Verilog 595 105 Updated Oct 10, 2021

Contains the code examples from The UVM Primer Book sorted by chapters.

SystemVerilog 625 237 Updated Dec 24, 2021

Community managed domain list

Go 2,630 471 Updated May 23, 2026