External Release v2023.10.11

Updated CPUs and instructions according to ISE (Intel® Architecture
Instruction Set Extensions and Future Features) rev-050, September 2023.

Added:
  - New USER_MSR and FRED instructions
  - New chips: Emerald Rapids, Clearwater Forest and Panther Lake
  - ENC2 updates with support for AMX/EVEX, IMM dest operand and EVEX
    scalable operand size instructions
  - Instructions for contributing to the Intel® XED project (README.md)

Fixed:
  - xed_agen() API: Avoid potential signed integer overflow (closes intelxed#305)
  - AMX: Fixed element types and updated extension definition

Modified:
  - Updated DAZ behavior of several AVX_NE_CONVERT instructions
  - Dropped Grand Ridge (No new ISA over SRF)
  - Updated PBNDKB CPUID name

Co-authored-by: marjevan <marjevan@users.noreply.github.com>

External Release v2023.08.21 with APX and AVX10 support

External Release v2023.07.09

Added new CPUs and instructions according to ISE (Intel Architecture Instruction Set Extensions
and Future Features) rev-049, June 2023.

Added:
  - Added new chips: Arrow-Lake and Lunar-Lake
  - Added new instructions: AVX-VNNI-INT16, SHA512, SM3, SM4 and PBNDKB
  - Updated SRF with UINTR and ENQCMD support

External Release v2023.06.07

General:
  - Updated Python version requirement to 3.7

Fixed:
  - Re-enable XED root directory renaming (fixes intelxed#300)
  - Disassembler: Add CET "notrack" prefix emit (intelxed#278)

Improved:
  - Improve decoder code size
  - XED Examples: Improve Code Quality

External Release v2023.04.16

Updated CPUs and instructions according to ISE (Intel Architecture
Instruction Set Extensions and Future Features) rev-048, March 2023.

General:
  - Updated Python version requirement to 3.6 (closes intelxed#293)

Added:
  - Support new AMX instructions: TCMMIMFP16PS and TCMMRLFP16PS
  - Support Clang15 build
  - Support decode-encode of SAE/ROUNDC ignored ISA
  - Added mandatory 66 prefix API: `xed_operand_values_mandatory_66_prefix()`

Fixed:
  - Fixed XED-ILD standalone library for AVX512 instructions (fixes intelxed#298)
  - Chip-Check: Fixed CLDEMOTE mapping (for TREMONT and ALDER_LAKE)
  - Fixed Operand API: `xed_operand_values_print_short()`
  - Fixed FADD operand visibility
  - Changed NOP-0F1F to match SDM definition
  - Removed BROADCAST definition from VINSERTF128
  - Added missing UNDOCUMENTED attribute to instructions not documented in SDM
  - Fixed memory operand for PREFETCH instructions
  - Fixed SENDUIPI register operand width (fixes intelxed#292)
  - Fixed AMD LWP{INS,VAL} operand width (fixes intelxed#299)
  - Fixed git describe fail message (fixes intelxed#291)
  - Updated xed-doc-top (fixes intelxed#294)
  - Fixed libxed documentation for Windows (fixes intelxed#295)
  - Fixed legal headers

Modified:
  - Renamed XED operand: "REXRR" -> "REXR4"

External Release v2022.10.11

Updated CPUs and instructions according to ISE (Intel Architecture Instruction Set Extensions
and Future Features) rev-046, September 2022.

Added:
  - Added new chips: Granite Rapids, Sierra Forest, Grand Ridge and Lakefield
  - Added new Instructions: AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8, CMPCCXADD,
     ICACHE_PREFETCH, MSRLIST, RAO-INT and WRMSRNS
  - Added getter API for VEX.pp prefix encoding value

Fixed:
  - Fixed instructions-set list for SPR
  - Fixed first operand access definition for SSE compute instructions (intelxed#287)

Modified:
  - Internal core modifications and updates

External Release v2022.08.11

General:
- Drop KNC Support

Added:
- Support Clang14 static build (Resolves intelxed#283)

Modified:
- Examples: Improve encoding for non-vector 64bit GPR instructions
- Examples: Support repeatable "-set" knob for setting multiple operands (xed.c
and xed-ex1.c)

Fixed:
- Fixed decoder length check (ILD) for VEX instructions
- Fixed STACKPUSH, STACKPOP registers definition
- Fixed registers definition for the instructions: SWAPGS FXTRACT, F[,A]PTAN, and FSINCOS.
- Fixed lock documentation (intelxed#280)
- Improve EVEX Ubit handling and error detection

External Release v2022.04.17

Added:
    - Added AMX classifier API: xed_classify_amx()
    - Added CPUID bit definition for [F,]CMOV*, FCOMI* and MMX technology
    - Added AMX tests

Modified:
    - Modified xed versioning to <year>.<month>.<day>
    - Improved re-encoding of vector instructions

Fixed:
    - Fixed [LD,ST]TILECFG memory width definition
    - Fixed MOV[H,L,LH,HL]P[S,D] register's access definition
    - Fixed [,V]MASKMOVDQU register's element type
    - Fixed RING0 attribute for CLAC and STAC
    - Fixed JKZD/JKNZD VEX.L bit (intelxed#282)
    - Fixed KNC build and decoder
    - Fixed Clang13 build error for "-Werror=sign-compare" flag

tag 12.0.1

remove avx512-reg-table-gpr. using EVEXRR_ONE instead

(cherry picked from commit b4f810fa1444c1c4a78e6e8752e7b4573f8dfe5a)