chore(rob): delete fusion commitType and add debug_fusionNum for topdown

Author: lewislzh

src/main/scala/xiangshan/backend/Bundles.scala

@@ -208,6 +208,7 @@ object Bundles {
     val canRobCompress  = Bool()
     val crossFtqCommit  = UInt(2.W) // use to caculate the ftq idx of ftqentry when commit
     val crossFtq        = Bool() // use to caculate the ftq idx of brh instructions when pass to exu
+    val fusionNum       = UInt(2.W)
     val selImm          = SelImm()
     val imm             = UInt(32.W)
     val fpu             = new FPUCtrlSignals

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -593,15 +593,6 @@ class CtrlBlockImp(
 
     // update the first RenameWidth - 1 instructions
     decode.io.fusion(i) := fusionDecoder.io.out(i).valid && rename.io.out(i).fire
-    // TODO: remove this dirty code for ftq update
-    val sameFtqPtr = rename.io.in(i).bits.ftqPtr.value === rename.io.in(i + 1).bits.ftqPtr.value
-    val ftqOffset0 = rename.io.in(i).bits.ftqOffset
-    val ftqOffset1 = rename.io.in(i + 1).bits.ftqOffset
-    val ftqOffsetDiff = ftqOffset1 - ftqOffset0
-    val cond1 = sameFtqPtr && ftqOffsetDiff === 1.U
-    val cond2 = sameFtqPtr && ftqOffsetDiff === 2.U
-    val cond3 = !sameFtqPtr && ftqOffset1 === 0.U
-    val cond4 = !sameFtqPtr && ftqOffset1 === 1.U
     when (fusionDecoder.io.out(i).valid) {
       fusionDecoder.io.out(i).bits.update(rename.io.in(i).bits)
       fusionDecoder.io.out(i).bits.update(dispatch.io.renameIn(i).bits)
@@ -616,7 +607,6 @@ class CtrlBlockImp(
       rename.io.isFusionVec(i) := true.B
       rename.io.fusionCross2FtqVec(i) := cross2Ftq
     }
-    XSError(fusionDecoder.io.out(i).valid && !cond1 && !cond2 && !cond3 && !cond4, p"new condition $sameFtqPtr $ftqOffset0 $ftqOffset1\n")
   }
 
   // memory dependency predict

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -376,6 +376,7 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
 
     uops(i).robIdx := robIdxHead + PopCount(io.in.zip(needRobFlags).zip(io.validVec).take(i).map{ case((in, needRobFlag), valid) => valid && in.bits.lastUop && needRobFlag})
     instrSize(i) := instrSizesVec(i) + io.fusionCross2FtqVec(i)
+    uops(i).fusionNum := PopCount(compressMasksVec(i) & Cat(io.isFusionVec.reverse))
     val hasExceptionExceptFlushPipe = Cat(selectFrontend(uops(i).exceptionVec) :+ uops(i).exceptionVec(illegalInstr) :+ uops(i).exceptionVec(virtualInstr)).orR || TriggerAction.isDmode(uops(i).trigger)
     when(isMove(i) || hasExceptionExceptFlushPipe) {
       uops(i).numUops := 0.U

src/main/scala/xiangshan/backend/rob/Rob.scala

@@ -1257,7 +1257,7 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
   val isCommit = io.commits.isCommit
   val isCommitReg = GatedValidRegNext(io.commits.isCommit)
   val instrCntReg = RegInit(0.U(64.W))
-  val fuseCommitCnt = PopCount(io.commits.commitValid.zip(io.commits.info).map { case (v, i) => RegEnable(v && CommitType.isFused(i.commitType), isCommit) })
+  val fuseCommitCnt = RegEnable(io.commits.commitValid.zip(io.commits.info).map { case (v, i) => Mux(v, i.debug_fusionNum.getOrElse(0.U), 0.U) }.reduce(_ +& _), isCommit)
   val trueCommitCnt = RegEnable(io.commits.commitValid.zip(instrSizeCommit).map { case (v, instrSize) => Mux(v, instrSize, 0.U) }.reduce(_ +& _), isCommit)
   val retireCounter = Mux(isCommitReg, trueCommitCnt, 0.U)
   val instrCnt = instrCntReg + retireCounter

src/main/scala/xiangshan/backend/rob/RobBundles.scala

@@ -83,6 +83,7 @@ object RobBundles extends HasCircularQueuePtrHelper {
     val debug_ldest = OptionWrapper(backendParams.basicDebugEn, UInt(LogicRegsWidth.W))
     val debug_pdest = OptionWrapper(backendParams.basicDebugEn, UInt(PhyRegIdxWidth.W))
     val debug_fuType = OptionWrapper(backendParams.debugEn, FuType())
+    val debug_fusionNum = OptionWrapper(backendParams.debugEn, UInt(2.W))
     // debug_end
 
     def isWritebacked: Bool = !uopNum.orR && stdWritebacked
@@ -121,6 +122,7 @@ object RobBundles extends HasCircularQueuePtrHelper {
     val debug_pdest = OptionWrapper(backendParams.basicDebugEn, UInt(PhyRegIdxWidth.W))
     val debug_otherPdest = OptionWrapper(backendParams.basicDebugEn, Vec(7, UInt(PhyRegIdxWidth.W)))
     val debug_fuType = OptionWrapper(backendParams.debugEn, FuType())
+    val debug_fusionNum = OptionWrapper(backendParams.debugEn, UInt(2.W))
     // debug_end
     val dirtyFs = Bool()
     val dirtyVs = Bool()
@@ -147,6 +149,7 @@ object RobBundles extends HasCircularQueuePtrHelper {
     robEntry.debug_ldest.foreach(_ := robEnq.ldest)
     robEntry.debug_pdest.foreach(_ := robEnq.pdest)
     robEntry.debug_fuType.foreach(_ := robEnq.fuType)
+    robEntry.debug_fusionNum.foreach(_ := robEnq.fusionNum)
   }
 
   def connectCommitEntry(robCommitEntry: RobCommitEntryBundle, robEntry: RobEntryBundle): Unit = {
@@ -179,6 +182,7 @@ object RobBundles extends HasCircularQueuePtrHelper {
     robCommitEntry.debug_ldest.foreach(_ := robEntry.debug_ldest.get)
     robCommitEntry.debug_pdest.foreach(_ := robEntry.debug_pdest.get)
     robCommitEntry.debug_fuType.foreach(_ := robEntry.debug_fuType.get)
+    robCommitEntry.debug_fusionNum.foreach(_ := robEntry.debug_fusionNum.get)
   }
 }
 

src/main/scala/xiangshan/package.scala

@@ -163,17 +163,16 @@ package object xiangshan {
   }
 
   object CommitType {
-    def NORMAL = "b000".U  // int/fp
-    def BRANCH = "b001".U  // branch
-    def LOAD   = "b010".U  // load
-    def STORE  = "b011".U  // store
-
-    def apply() = UInt(3.W)
-    def isFused(commitType: UInt): Bool = commitType(2)
-    def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1)
+    def NORMAL = "b00".U  // int/fp
+    def BRANCH = "b01".U  // branch
+    def LOAD   = "b10".U  // load
+    def STORE  = "b11".U  // store
+
+    def apply() = UInt(2.W)
+    def isLoadStore(commitType: UInt): Bool = commitType(1)
     def lsInstIsStore(commitType: UInt): Bool = commitType(0)
     def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType)
-    def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType)
+    def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1)
   }
 
   object RedirectLevel {