Skip to content

Commit d84d620

Browse files
committed
misc: update backend code-owners
1 parent 8e9a16b commit d84d620

File tree

1 file changed

+17
-0
lines changed

1 file changed

+17
-0
lines changed

.github/CODEOWNERS

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,23 @@ src/main/scala/xiangshan/frontend/icache/ @ngc7331 @Gao-Zeyu
66
src/main/scala/xiangshan/frontend/ifu/ @ngc7331 @my-mayfly @Gao-Zeyu
77
src/main/scala/xiangshan/frontend/instruncache/ @ngc7331 @Gao-Zeyu
88

9+
src/main/scala/xiangshan/backend/ @lewislzh
10+
src/main/scala/xiangshan/backend/Region.scala @xiaofeibao-xjtu @lewislzh
11+
src/main/scala/xiangshan/backend/CtrlBlock.scala @wissygh @lewislzh
12+
src/main/scala/xiangshan/backend/ctrlblock/ @wissygh @lewislzh
13+
src/main/scala/xiangshan/backend/datapath/ @xiaofeibao-xjtu @lewislzh
14+
src/main/scala/xiangshan/backend/decode/ @HeiHuDie @lewislzh
15+
src/main/scala/xiangshan/backend/dispatch/ @xiaofeibao-xjtu @lewislzh
16+
src/main/scala/xiangshan/backend/exu/ @sinceforYy @lewislzh
17+
src/main/scala/xiangshan/backend/fu/ @sinceforYy @lewislzh
18+
src/main/scala/xiangshan/backend/fu/NewCSR/ @huxuan0307 @lewislzh
19+
src/main/scala/xiangshan/backend/issue/ @xiaofeibao-xjtu @lewislzh
20+
src/main/scala/xiangshan/backend/regcache/ @xiaofeibao-xjtu @lewislzh
21+
src/main/scala/xiangshan/backend/regfile/ @xiaofeibao-xjtu @lewislzh
22+
src/main/scala/xiangshan/backend/rename/ @Tang-Haojin @lewislzh
23+
src/main/scala/xiangshan/backend/rob/ @NewPaulWalker @xiaofeibao-xjtu @lewislzh
24+
src/main/scala/xiangshan/backend/trace/ @wissygh @lewislzh
25+
926
src/main/scala/xiangshan/cache/ @linjuanZ
1027
src/main/scala/xiangshan/cache/dcache/ @Maxpicca-Li @linjuanZ
1128
src/main/scala/xiangshan/cache/mmu/ @good-circle @cebarobot @linjuanZ

0 commit comments

Comments
 (0)