diff --git a/src/main/scala/xiangshan/XSCore.scala b/src/main/scala/xiangshan/XSCore.scala
index 0e3bbef924c..abc22b3cf83 100644
--- a/src/main/scala/xiangshan/XSCore.scala
+++ b/src/main/scala/xiangshan/XSCore.scala
@@ -214,8 +214,8 @@ trait HasXSParameter {
   )
 
   val dcacheParameters = DCacheParameters(
-    tagECC = Some("secded"),
-    dataECC = Some("secded"),
+    tagECC = Some("none"),
+    dataECC = Some("none"),
     nMissEntries = 16,
     nProbeEntries = 16,
     nReleaseEntries = 16,
diff --git a/src/main/scala/xiangshan/cache/MissQueue.scala b/src/main/scala/xiangshan/cache/MissQueue.scala
index e191f1e3916..c79e2eeb997 100644
--- a/src/main/scala/xiangshan/cache/MissQueue.scala
+++ b/src/main/scala/xiangshan/cache/MissQueue.scala
@@ -364,7 +364,7 @@ class MissQueue(edge: TLEdgeOut) extends DCacheModule with HasTLDump
   })
 
   val pipe_req_arb = Module(new RRArbiter(new MainPipeReq, cfg.nMissEntries))
-  val refill_arb   = Module(new RRArbiter(new Refill, cfg.nMissEntries))
+  val refill_arb   = Module(new Arbiter(new Refill, cfg.nMissEntries))
 
   // dispatch req to MSHR
   val primary_ready  = Wire(Vec(cfg.nMissEntries, Bool()))