diff --git a/src/main/scala/xiangshan/XSCore.scala b/src/main/scala/xiangshan/XSCore.scala
index 4f3bf25aef5..14215dccad6 100644
--- a/src/main/scala/xiangshan/XSCore.scala
+++ b/src/main/scala/xiangshan/XSCore.scala
@@ -50,7 +50,7 @@ case class XSCoreParameters
   EnableRAS: Boolean = true,
   EnableLB: Boolean = false,
   EnableLoop: Boolean = true,
-  EnableSC: Boolean = false,
+  EnableSC: Boolean = true,
   EnbaleTlbDebug: Boolean = false,
   EnableJal: Boolean = false,
   EnableUBTB: Boolean = true,
diff --git a/src/main/scala/xiangshan/frontend/Bim.scala b/src/main/scala/xiangshan/frontend/Bim.scala
index 73759a1f1c7..3cccb938bf3 100644
--- a/src/main/scala/xiangshan/frontend/Bim.scala
+++ b/src/main/scala/xiangshan/frontend/Bim.scala
@@ -94,13 +94,13 @@ class BIM extends BasePredictor with BimParams {
         when (needToUpdate(b)) {
           wrbypass_ctr_valids(wrbypass_enq_idx)(b) := true.B
           wrbypass_ctrs(wrbypass_enq_idx)(b) := newCtrs(b)
-          wrbypass_rows(wrbypass_enq_idx) := updateRow
         }
       }
     }
   }
   
   when (needToUpdate.reduce(_||_) && !wrbypass_hit) {
+    wrbypass_rows(wrbypass_enq_idx) := updateRow
     wrbypass_enq_idx := (wrbypass_enq_idx + 1.U)(log2Up(bypassEntries)-1,0)
   }
 
diff --git a/src/main/scala/xiangshan/frontend/LoopPredictor.scala b/src/main/scala/xiangshan/frontend/LoopPredictor.scala
index 431a74b9843..8ce7f7e08ab 100644
--- a/src/main/scala/xiangshan/frontend/LoopPredictor.scala
+++ b/src/main/scala/xiangshan/frontend/LoopPredictor.scala
@@ -338,9 +338,8 @@ class LoopPredictor extends BasePredictor with LTBParams {
   val updateValid = io.update.valid
   val update = io.update.bits
 
-  val do_redirect = RegNext(io.redirect)
-  val redirectValid = do_redirect.valid
-  val redirect = do_redirect.bits.cfiUpdate
+  val redirectValid = io.redirect.valid
+  val redirect = io.redirect.bits.cfiUpdate
   val redirectPC = redirect.pc
   val redirectBank = ltbAddr.getBank(redirectPC)
  
@@ -363,7 +362,7 @@ class LoopPredictor extends BasePredictor with LTBParams {
     ltbs(i).io.redirect.bits.specCnt := redirect.specCnt(i)
     ltbs(i).io.redirect.bits.mispred := redirect.isMisPred
     ltbs(i).io.redirect.bits.taken := redirect.taken
-    ltbs(i).io.redirect.bits.isReplay := do_redirect.bits.flushItself
+    ltbs(i).io.redirect.bits.isReplay := io.redirect.bits.flushItself
 
     ltbs(i).io.repair := redirectValid && redirectBank =/= i.U
   }
@@ -394,7 +393,7 @@ class LoopPredictor extends BasePredictor with LTBParams {
     XSDebug("[IF4][req] inMask=%b\n", inMask)
 
     XSDebug("[IF4][req] updatePC=%x, updateValid=%d, isBr=%b\n", update.ftqPC, updateValid, update.br_mask.asUInt)
-    XSDebug("[IF4][req] redirectPC=%x redirectBank=%d, redirectValid=%d, isBr=%d, isReplay=%d\n", redirect.pc, redirectBank, redirectValid, redirect.pd.isBr, do_redirect.bits.flushItself)
+    XSDebug("[IF4][req] redirectPC=%x redirectBank=%d, redirectValid=%d, isBr=%d, isReplay=%d\n", redirect.pc, redirectBank, redirectValid, redirect.pd.isBr, io.redirect.bits.flushItself)
     XSDebug("[IF4][req] isMisPred=%d\n", redirect.isMisPred)
 
     XSDebug(redirectValid, "[redirect SpecCnt] ")
diff --git a/src/main/scala/xiangshan/frontend/SC.scala b/src/main/scala/xiangshan/frontend/SC.scala
index 6bf885c7d19..b157d20a1c0 100644
--- a/src/main/scala/xiangshan/frontend/SC.scala
+++ b/src/main/scala/xiangshan/frontend/SC.scala
@@ -123,13 +123,13 @@ class SCTable(val nRows: Int, val ctrBits: Int, val histLen: Int)
         when (io.update.mask(w)) {
           wrbypass_ctr_valids(wrbypass_enq_idx)(ctrPos) := true.B
           wrbypass_ctrs(wrbypass_enq_idx)(w) := update_wdatas(w)
-          wrbypass_idxs(wrbypass_enq_idx) := update_idx
         }
       }
     }
   }
-
+  
   when (io.update.mask.reduce(_||_) && !wrbypass_hit) {
+    wrbypass_idxs(wrbypass_enq_idx) := update_idx
     wrbypass_enq_idx := (wrbypass_enq_idx + 1.U)(log2Ceil(wrBypassEntries)-1,0)
   }
 
@@ -157,19 +157,20 @@ class SCTable(val nRows: Int, val ctrBits: Int, val histLen: Int)
 
 }
 
-class SCThreshold(val ctrBits: Int = 5) extends SCBundle {
+class SCThreshold(val ctrBits: Int = 6) extends SCBundle {
   val ctr = UInt(ctrBits.W)
   def satPos(ctr: UInt = this.ctr) = ctr === ((1.U << ctrBits) - 1.U)
   def satNeg(ctr: UInt = this.ctr) = ctr === 0.U
   def neutralVal = (1.U << (ctrBits - 1))
-  val thres = UInt(5.W)
-  def minThres = 5.U
-  def maxThres = 31.U
+  val thres = UInt(8.W)
+  def initVal = 60.U
+  def minThres = 6.U
+  def maxThres = 255.U
   def update(cause: Bool): SCThreshold = {
     val res = Wire(new SCThreshold(this.ctrBits))
     val newCtr = satUpdate(this.ctr, this.ctrBits, cause)
-    val newThres = Mux(res.satPos(newCtr), this.thres + 1.U,
-                      Mux(res.satNeg(newCtr), this.thres - 1.U,
+    val newThres = Mux(res.satPos(newCtr) && this.thres <= maxThres, this.thres + 2.U,
+                      Mux(res.satNeg(newCtr) && this.thres >= minThres, this.thres - 2.U,
                       this.thres))
     res.thres := newThres
     res.ctr := Mux(res.satPos(newCtr) || res.satNeg(newCtr), res.neutralVal, newCtr)
@@ -182,7 +183,7 @@ object SCThreshold {
   def apply(bits: Int) = {
     val t = Wire(new SCThreshold(ctrBits=bits))
     t.ctr := t.neutralVal
-    t.thres := t.minThres
+    t.thres := t.initVal
     t
   }
 }
@@ -202,9 +203,9 @@ trait HasSC extends HasSCParameter { this: Tage =>
     }
   }
   
-  val scThreshold = RegInit(SCThreshold(5))
-  val useThreshold = WireInit(scThreshold.thres)
-  val updateThreshold = WireInit((useThreshold << 3) + 21.U)
+  val scThresholds = List.fill(TageBanks)(RegInit(SCThreshold(5)))
+  val useThresholds = VecInit(scThresholds map (_.thres))
+  val updateThresholds = VecInit(useThresholds map (t => (t << 3) + 21.U))
   
   val if3_scResps = VecInit(scTables.map(t => t.io.resp))
 
@@ -240,7 +241,7 @@ trait HasSC extends HasSCParameter { this: Tage =>
     val if3_pvdrCtrCentered = getPvdrCentered(providerCtr)
     val if3_totalSums = VecInit(if3_scTableSums.map(_  + if3_pvdrCtrCentered))
     val if3_sumAbs = VecInit(if3_totalSums.map(_.abs.asUInt))
-    val if3_sumBelowThresholds = VecInit(if3_sumAbs.map(_ < useThreshold))
+    val if3_sumBelowThresholds = VecInit(if3_sumAbs zip useThresholds map {case (s, t) => s < t})
     val if3_scPreds = VecInit(if3_totalSums.map (_ >= 0.S))
 
     val if4_sumBelowThresholds = RegEnable(if3_sumBelowThresholds, s3_fire)
@@ -282,12 +283,11 @@ trait HasSC extends HasSCParameter { this: Tage =>
       scUpdateTakens(w) := taken
       (scUpdateOldCtrs(w) zip scOldCtrs).foreach{case (t, c) => t := c}
 
-      when (scPred =/= tagePred && sumAbs < useThreshold - 2.U) {
-        val newThres = scThreshold.update(scPred =/= taken)
-        scThreshold := newThres
-        XSDebug(p"scThres update: old d${useThreshold} --> new ${newThres.thres}\n")
-      }
-      when (scPred =/= taken || sumAbs < updateThreshold) {
+      when (scPred =/= taken || sumAbs < useThresholds(w)) {
+        val newThres = scThresholds(w).update(scPred =/= taken)
+        scThresholds(w) := newThres
+        XSDebug(p"scThres $w update: old ${useThresholds(w)} --> new ${newThres.thres}\n")
+
         scUpdateMask.foreach(t => t(w) := true.B)
         XSDebug(sum < 0.S,
           p"scUpdate: bank(${w}), scPred(${scPred}), tagePred(${tagePred}), " +
diff --git a/src/main/scala/xiangshan/frontend/Tage.scala b/src/main/scala/xiangshan/frontend/Tage.scala
index 2dae24ded80..0c574a786ef 100644
--- a/src/main/scala/xiangshan/frontend/Tage.scala
+++ b/src/main/scala/xiangshan/frontend/Tage.scala
@@ -261,14 +261,14 @@ class TageTable(val nRows: Int, val histLen: Int, val tagLen: Int, val uBitPerio
         when (io.update.mask(w)) {
           wrbypass_ctr_valids(wrbypass_enq_idx)(w) := true.B
           wrbypass_ctrs(wrbypass_enq_idx)(w) := update_wdata(w).ctr
-          wrbypass_tags(wrbypass_enq_idx) := update_tag
-          wrbypass_idxs(wrbypass_enq_idx) := update_idx
         }
       }
     }
   }
-
+  
   when (io.update.mask.reduce(_||_) && !wrbypass_hit) {
+    wrbypass_tags(wrbypass_enq_idx) := update_tag
+    wrbypass_idxs(wrbypass_enq_idx) := update_idx
     wrbypass_enq_idx := (wrbypass_enq_idx + 1.U)(log2Ceil(wrBypassEntries)-1,0)
   }