From f32b48cc533845dd23ea34f3692dad9d3176321e Mon Sep 17 00:00:00 2001
From: Lingrui98 <goulingrui15@gmail.com>
Date: Sat, 20 Feb 2021 17:29:26 +0800
Subject: [PATCH 01/12] core: enable sc

---
 src/main/scala/xiangshan/XSCore.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/xiangshan/XSCore.scala b/src/main/scala/xiangshan/XSCore.scala
index c3be93fb412..0f8a2a38f2e 100644
--- a/src/main/scala/xiangshan/XSCore.scala
+++ b/src/main/scala/xiangshan/XSCore.scala
@@ -49,7 +49,7 @@ case class XSCoreParameters
   EnableRAS: Boolean = true,
   EnableLB: Boolean = false,
   EnableLoop: Boolean = true,
-  EnableSC: Boolean = false,
+  EnableSC: Boolean = true,
   EnbaleTlbDebug: Boolean = false,
   EnableJal: Boolean = false,
   EnableUBTB: Boolean = true,

From 9f8dc49bd6bd2ede7df0541a998744acb9696270 Mon Sep 17 00:00:00 2001
From: Lingrui98 <goulingrui15@gmail.com>
Date: Sat, 20 Feb 2021 18:50:14 +0800
Subject: [PATCH 02/12] sc: calculate sum again on update

---
 src/main/scala/xiangshan/Bundle.scala      |  1 -
 src/main/scala/xiangshan/frontend/SC.scala | 17 +++++++++++------
 2 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/src/main/scala/xiangshan/Bundle.scala b/src/main/scala/xiangshan/Bundle.scala
index a1d00e53663..0cbd2dee9fb 100644
--- a/src/main/scala/xiangshan/Bundle.scala
+++ b/src/main/scala/xiangshan/Bundle.scala
@@ -59,7 +59,6 @@ class SCMeta(val useSC: Boolean) extends XSBundle with HasSCParameter {
   val scPred = if (useSC) Bool() else UInt(0.W)
   // Suppose ctrbits of all tables are identical
   val ctrs = if (useSC) Vec(SCNTables, SInt(SCCtrBits.W)) else Vec(SCNTables, SInt(0.W))
-  val sumAbs = if (useSC) UInt(sumCtrBits.W) else UInt(0.W)
 }
 
 class TageMeta extends XSBundle with HasTageParameter {
diff --git a/src/main/scala/xiangshan/frontend/SC.scala b/src/main/scala/xiangshan/frontend/SC.scala
index 8d9cab338da..158dc799f6d 100644
--- a/src/main/scala/xiangshan/frontend/SC.scala
+++ b/src/main/scala/xiangshan/frontend/SC.scala
@@ -42,7 +42,6 @@ class SCTableIO extends SCBundle {
 
 abstract class BaseSCTable(val r: Int = 1024, val cb: Int = 6, val h: Int = 0) extends SCModule {
   val io = IO(new SCTableIO)
-  def getCenteredValue(ctr: SInt): SInt = (ctr << 1).asSInt + 1.S
 }
 
 class FakeSCTable extends BaseSCTable {
@@ -174,6 +173,11 @@ trait HasSC extends HasSCParameter { this: Tage =>
 
   val updateSCMetas = VecInit(u.metas.map(_.tageMeta.scMeta))
 
+  // for sc ctrs
+  def getCentered(ctr: SInt): SInt = (ctr << 1).asSInt + 1.S
+  // for tage ctrs
+  def getPvdrCentered(ctr: UInt): SInt = ((((ctr.zext - 4.S) << 1).asSInt + 1.S) << 3).asSInt
+
   for (w <- 0 until TageBanks) {
     val scMeta = io.meta(w).scMeta
     scMeta := DontCare
@@ -182,15 +186,15 @@ trait HasSC extends HasSCParameter { this: Tage =>
       (0 to 1) map { i => {
           if (EnableSC) {
             (0 until SCNTables) map { j => 
-              scTables(j).getCenteredValue(if3_scResps(j)(w).ctr(i))
+              getCentered(if3_scResps(j)(w).ctr(i))
             } reduce (_+_) // TODO: rewrite with adder tree
           }
           else 0.S
         }
       }
     )
-    val providerCtr = if3_providerCtrs(w).zext()
-    val if3_pvdrCtrCentered = ((((providerCtr - 4.S) << 1).asSInt + 1.S) << 3).asSInt
+    val providerCtr = if3_providerCtrs(w)
+    val if3_pvdrCtrCentered = getPvdrCentered(providerCtr)
     val if3_totalSums = VecInit(if3_scTableSums.map(_  + if3_pvdrCtrCentered))
     val if3_sumAbs = VecInit(if3_totalSums.map(_.abs.asUInt))
     val if3_sumBelowThresholds = VecInit(if3_sumAbs.map(_ < useThreshold))
@@ -205,7 +209,6 @@ trait HasSC extends HasSCParameter { this: Tage =>
     scMeta.tageTaken := if4_tageTakens(w)
     scMeta.scUsed := if4_provideds(w)
     scMeta.scPred := if4_scPreds(if4_chooseBit)
-    scMeta.sumAbs := if4_sumAbs(if4_chooseBit)
     scMeta.ctrs   := if4_scCtrs
 
     
@@ -221,12 +224,14 @@ trait HasSC extends HasSCParameter { this: Tage =>
     }
     if (EnableSC) {
       val updateSCMeta = updateSCMetas(w)
+      val updateTageMeta = updateMetas(w)
       when (updateValids(w) && updateSCMeta.scUsed.asBool && updateBrMask(w)) {
         val scPred = updateSCMeta.scPred
         val tagePred = updateSCMeta.tageTaken
         val taken = u.takens(w)
-        val sumAbs = updateSCMeta.sumAbs.asUInt
         val scOldCtrs = updateSCMeta.ctrs
+        val pvdrCtr = updateTageMeta.providerCtr
+        val sumAbs = (scOldCtrs.map(getCentered).reduce(_+_) + getPvdrCentered(pvdrCtr)).abs.asUInt
         scUpdateTagePreds(w) := tagePred
         scUpdateTakens(w) := taken
         (scUpdateOldCtrs(w) zip scOldCtrs).foreach{case (t, c) => t := c}

From 332ecc4e5116d811a73e90b6e5560e09d23feaf5 Mon Sep 17 00:00:00 2001
From: Lingrui98 <goulingrui15@gmail.com>
Date: Sat, 20 Feb 2021 20:04:48 +0800
Subject: [PATCH 03/12] sc: clean ups

---
 src/main/scala/xiangshan/frontend/SC.scala | 86 ++++++++++------------
 1 file changed, 37 insertions(+), 49 deletions(-)

diff --git a/src/main/scala/xiangshan/frontend/SC.scala b/src/main/scala/xiangshan/frontend/SC.scala
index 158dc799f6d..f7cedba5b4e 100644
--- a/src/main/scala/xiangshan/frontend/SC.scala
+++ b/src/main/scala/xiangshan/frontend/SC.scala
@@ -40,17 +40,10 @@ class SCTableIO extends SCBundle {
   val update = Input(new SCUpdate)
 }
 
-abstract class BaseSCTable(val r: Int = 1024, val cb: Int = 6, val h: Int = 0) extends SCModule {
-  val io = IO(new SCTableIO)
-}
-
-class FakeSCTable extends BaseSCTable {
-  io.resp := 0.U.asTypeOf(Vec(TageBanks, new SCResp))
-}
-
 @chiselName
 class SCTable(val nRows: Int, val ctrBits: Int, val histLen: Int)
-  extends BaseSCTable(nRows, ctrBits, histLen) with HasFoldedHistory {
+  extends SCModule with HasFoldedHistory {
+  val io = IO(new SCTableIO)
 
   val table = Module(new SRAMTemplate(SInt(ctrBits.W), set=nRows, way=2*TageBanks, shouldReset=true, holdRead=true, singlePort=false))
 
@@ -146,7 +139,7 @@ object SCThreshold {
 trait HasSC extends HasSCParameter { this: Tage =>
   val scTables = SCTableInfo.map {
     case (nRows, ctrBits, histLen) => {
-      val t = if (EnableSC) Module(new SCTable(nRows/TageBanks, ctrBits, histLen)) else Module(new FakeSCTable)
+      val t = Module(new SCTable(nRows/TageBanks, ctrBits, histLen))
       val req = t.io.req
       req.valid := io.pc.valid
       req.bits.pc := io.pc.bits
@@ -184,15 +177,13 @@ trait HasSC extends HasSCParameter { this: Tage =>
     // do summation in if3
     val if3_scTableSums = VecInit(
       (0 to 1) map { i => {
-          if (EnableSC) {
-            (0 until SCNTables) map { j => 
-              getCentered(if3_scResps(j)(w).ctr(i))
-            } reduce (_+_) // TODO: rewrite with adder tree
-          }
-          else 0.S
+          (0 until SCNTables) map { j => 
+            getCentered(if3_scResps(j)(w).ctr(i))
+          } reduce (_+_) // TODO: rewrite with adder tree
         }
       }
     )
+
     val providerCtr = if3_providerCtrs(w)
     val if3_pvdrCtrCentered = getPvdrCentered(providerCtr)
     val if3_totalSums = VecInit(if3_scTableSums.map(_  + if3_pvdrCtrCentered))
@@ -211,43 +202,40 @@ trait HasSC extends HasSCParameter { this: Tage =>
     scMeta.scPred := if4_scPreds(if4_chooseBit)
     scMeta.ctrs   := if4_scCtrs
 
-    
-    if (EnableSC) {
-      when (if4_provideds(w)) {
-        // Use prediction from Statistical Corrector
-        when (!if4_sumBelowThresholds(if4_chooseBit)) {
-          val pred = if4_scPreds(if4_chooseBit)
-          XSDebug(RegNext(s3_fire), p"SC(${w.U}) overriden pred to ${pred}\n")
-          io.resp.takens(w) := pred
-        }
+    when (if4_provideds(w)) {
+      // Use prediction from Statistical Corrector
+      when (!if4_sumBelowThresholds(if4_chooseBit)) {
+        val pred = if4_scPreds(if4_chooseBit)
+        XSDebug(RegNext(s3_fire), p"SC(${w.U}) overriden pred to ${pred}\n")
+        io.resp.takens(w) := pred
       }
     }
-    if (EnableSC) {
-      val updateSCMeta = updateSCMetas(w)
-      val updateTageMeta = updateMetas(w)
-      when (updateValids(w) && updateSCMeta.scUsed.asBool && updateBrMask(w)) {
-        val scPred = updateSCMeta.scPred
-        val tagePred = updateSCMeta.tageTaken
-        val taken = u.takens(w)
-        val scOldCtrs = updateSCMeta.ctrs
-        val pvdrCtr = updateTageMeta.providerCtr
-        val sumAbs = (scOldCtrs.map(getCentered).reduce(_+_) + getPvdrCentered(pvdrCtr)).abs.asUInt
-        scUpdateTagePreds(w) := tagePred
-        scUpdateTakens(w) := taken
-        (scUpdateOldCtrs(w) zip scOldCtrs).foreach{case (t, c) => t := c}
-
-        when (scPred =/= tagePred && sumAbs < useThreshold - 2.U) {
-          val newThres = scThreshold.update(scPred =/= taken)
-          scThreshold := newThres
-          XSDebug(p"scThres update: old d${useThreshold} --> new ${newThres.thres}\n")
-        }
-        when (scPred =/= taken || sumAbs < updateThreshold) {
-          scUpdateMask.foreach(t => t(w) := true.B)
-          XSDebug(p"scUpdate: bank(${w}), scPred(${scPred}), tagePred(${tagePred}), scSumAbs(${sumAbs}), mispred: sc(${updateMisPred}), tage(${updateTageMisPreds(w)})\n")
-          XSDebug(p"update: sc: ${updateSCMeta}\n")
-        }
+
+    val updateSCMeta = updateSCMetas(w)
+    val updateTageMeta = updateMetas(w)
+    when (updateValids(w) && updateSCMeta.scUsed.asBool && updateBrMask(w)) {
+      val scPred = updateSCMeta.scPred
+      val tagePred = updateSCMeta.tageTaken
+      val taken = u.takens(w)
+      val scOldCtrs = updateSCMeta.ctrs
+      val pvdrCtr = updateTageMeta.providerCtr
+      val sumAbs = (scOldCtrs.map(getCentered).reduce(_+_) + getPvdrCentered(pvdrCtr)).abs.asUInt
+      scUpdateTagePreds(w) := tagePred
+      scUpdateTakens(w) := taken
+      (scUpdateOldCtrs(w) zip scOldCtrs).foreach{case (t, c) => t := c}
+
+      when (scPred =/= tagePred && sumAbs < useThreshold - 2.U) {
+        val newThres = scThreshold.update(scPred =/= taken)
+        scThreshold := newThres
+        XSDebug(p"scThres update: old d${useThreshold} --> new ${newThres.thres}\n")
+      }
+      when (scPred =/= taken || sumAbs < updateThreshold) {
+        scUpdateMask.foreach(t => t(w) := true.B)
+        XSDebug(p"scUpdate: bank(${w}), scPred(${scPred}), tagePred(${tagePred}), scSumAbs(${sumAbs}), mispred: sc(${updateMisPred}), tage(${updateTageMisPreds(w)})\n")
+        XSDebug(p"update: sc: ${updateSCMeta}\n")
       }
     }
+
     for (i <- 0 until SCNTables) {
       scTables(i).io.update.mask := RegNext(scUpdateMask(i))
       scTables(i).io.update.tagePreds := RegNext(scUpdateTagePreds)

From e0c8f22351035df8ec9c8f34d8d06e8789d2d346 Mon Sep 17 00:00:00 2001
From: Lingrui98 <goulingrui15@gmail.com>
Date: Sat, 20 Feb 2021 22:31:40 +0800
Subject: [PATCH 04/12] sc: add some debug info

---
 src/main/scala/xiangshan/frontend/SC.scala | 26 +++++++++++++++-------
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/src/main/scala/xiangshan/frontend/SC.scala b/src/main/scala/xiangshan/frontend/SC.scala
index f7cedba5b4e..0f06e95478e 100644
--- a/src/main/scala/xiangshan/frontend/SC.scala
+++ b/src/main/scala/xiangshan/frontend/SC.scala
@@ -89,9 +89,8 @@ class SCTable(val nRows: Int, val ctrBits: Int, val histLen: Int)
 
   if (BPUDebug && debug) {
     val u = io.update
-    val b = PriorityEncoder(u.mask)
-    XSDebug(io.req.valid, p"scTableReq: pc=0x${Hexadecimal(io.req.bits.pc)}" +
-                          p"if2_idx=${if2_idx}, hist=${Hexadecimal(io.req.bits.hist)}," +
+    XSDebug(io.req.valid, p"scTableReq: pc=0x${Hexadecimal(io.req.bits.pc)}, " +
+                          p"if2_idx=${if2_idx}, hist=${Hexadecimal(io.req.bits.hist)}, " +
                           p"if2_mask=${Binary(if2_mask)}\n")
     for (i <- 0 until TageBanks) {
       XSDebug(RegNext(io.req.valid), 
@@ -99,7 +98,7 @@ class SCTable(val nRows: Int, val ctrBits: Int, val histLen: Int)
               p"ctr:${io.resp(i).ctr}, if3_mask=${Binary(if3_mask)}\n")
       XSDebug(io.update.mask(i),
               p"update Table: pc:${Hexadecimal(u.pc)}, hist:${Hexadecimal(u.hist)}," +
-              p"bank:${b}%d, tageTaken:${u.tagePreds(i)}%d, taken:${u.takens(i)}%d, oldCtr:${u.oldCtrs(i)}%d\n")
+              p"bank:${i}, tageTaken:${u.tagePreds(i)}, taken:${u.takens(i)}, oldCtr:${u.oldCtrs(i)}\n")
     }
   }
 
@@ -204,9 +203,12 @@ trait HasSC extends HasSCParameter { this: Tage =>
 
     when (if4_provideds(w)) {
       // Use prediction from Statistical Corrector
+      XSDebug(p"---------tage${w} provided so that sc used---------\n")
+      XSDebug(p"scCtrs:$if4_scCtrs, prdrCtr:${if4_providerCtrs(w)}, sumAbs:$if4_sumAbs, tageTaken:${if4_chooseBit}\n")
       when (!if4_sumBelowThresholds(if4_chooseBit)) {
         val pred = if4_scPreds(if4_chooseBit)
-        XSDebug(RegNext(s3_fire), p"SC(${w.U}) overriden pred to ${pred}\n")
+        val debug_pc = Cat(packetIdx(debug_pc_s3), w.U, 0.U(instOffsetBits.W))
+        XSDebug(p"pc(${Hexadecimal(debug_pc)}) SC(${w.U}) overriden pred to ${pred}\n")
         io.resp.takens(w) := pred
       }
     }
@@ -219,7 +221,8 @@ trait HasSC extends HasSCParameter { this: Tage =>
       val taken = u.takens(w)
       val scOldCtrs = updateSCMeta.ctrs
       val pvdrCtr = updateTageMeta.providerCtr
-      val sumAbs = (scOldCtrs.map(getCentered).reduce(_+_) + getPvdrCentered(pvdrCtr)).abs.asUInt
+      val sum = scOldCtrs.map(getCentered).reduce(_+_) + getPvdrCentered(pvdrCtr)
+      val sumAbs = sum.abs.asUInt
       scUpdateTagePreds(w) := tagePred
       scUpdateTakens(w) := taken
       (scUpdateOldCtrs(w) zip scOldCtrs).foreach{case (t, c) => t := c}
@@ -231,8 +234,15 @@ trait HasSC extends HasSCParameter { this: Tage =>
       }
       when (scPred =/= taken || sumAbs < updateThreshold) {
         scUpdateMask.foreach(t => t(w) := true.B)
-        XSDebug(p"scUpdate: bank(${w}), scPred(${scPred}), tagePred(${tagePred}), scSumAbs(${sumAbs}), mispred: sc(${updateMisPred}), tage(${updateTageMisPreds(w)})\n")
-        XSDebug(p"update: sc: ${updateSCMeta}\n")
+        XSDebug(sum < 0.S,
+          p"scUpdate: bank(${w}), scPred(${scPred}), tagePred(${tagePred}), " +
+          p"scSum(-$sumAbs), mispred: sc(${scPred =/= taken}), tage(${updateTageMisPreds(w)})\n"
+        )
+        XSDebug(sum >= 0.S,
+          p"scUpdate: bank(${w}), scPred(${scPred}), tagePred(${tagePred}), " +
+          p"scSum(+$sumAbs), mispred: sc(${scPred =/= taken}), tage(${updateTageMisPreds(w)})\n"
+        )
+        XSDebug(p"bank(${w}), update: sc: ${updateSCMeta}\n")
       }
     }
 

From 1fb174fca29e4ac3d5b51e0fd7ed55078796ddab Mon Sep 17 00:00:00 2001
From: Lingrui98 <goulingrui15@gmail.com>
Date: Wed, 24 Feb 2021 22:42:28 +0800
Subject: [PATCH 05/12] sc, tage, bim: fix wrbypass logic, add wrbypass for SC

---
 src/main/scala/xiangshan/Bundle.scala        |  6 --
 src/main/scala/xiangshan/frontend/Bim.scala  | 35 ++++++----
 src/main/scala/xiangshan/frontend/SC.scala   | 67 +++++++++++++++++--
 src/main/scala/xiangshan/frontend/Tage.scala | 69 +++++++++++---------
 4 files changed, 123 insertions(+), 54 deletions(-)

diff --git a/src/main/scala/xiangshan/Bundle.scala b/src/main/scala/xiangshan/Bundle.scala
index 0cbd2dee9fb..f3d3c298ba7 100644
--- a/src/main/scala/xiangshan/Bundle.scala
+++ b/src/main/scala/xiangshan/Bundle.scala
@@ -48,12 +48,6 @@ object ValidUndirectioned {
 }
 
 class SCMeta(val useSC: Boolean) extends XSBundle with HasSCParameter {
-  def maxVal = 8 * ((1 << TageCtrBits) - 1) + SCTableInfo.map { case (_, cb, _) => (1 << cb) - 1 }.reduce(_ + _)
-
-  def minVal = -(8 * (1 << TageCtrBits) + SCTableInfo.map { case (_, cb, _) => 1 << cb }.reduce(_ + _))
-
-  def sumCtrBits = max(log2Ceil(-minVal), log2Ceil(maxVal + 1)) + 1
-
   val tageTaken = if (useSC) Bool() else UInt(0.W)
   val scUsed = if (useSC) Bool() else UInt(0.W)
   val scPred = if (useSC) Bool() else UInt(0.W)
diff --git a/src/main/scala/xiangshan/frontend/Bim.scala b/src/main/scala/xiangshan/frontend/Bim.scala
index da0042b4d0e..3b85b4fa3c7 100644
--- a/src/main/scala/xiangshan/frontend/Bim.scala
+++ b/src/main/scala/xiangshan/frontend/Bim.scala
@@ -81,19 +81,26 @@ class BIM extends BasePredictor with BimParams {
   when (reset.asBool) { wrbypass_ctr_valids.foreach(_.foreach(_ := false.B))}
   
   for (b <- 0 until BimBanks) {
-    when (needToUpdate(b)) {
+    when (needToUpdate.reduce(_||_)) {
       when (wrbypass_hit) {
-        wrbypass_ctrs(wrbypass_hit_idx)(b) := newCtrs(b)
-        wrbypass_ctr_valids(wrbypass_hit_idx)(b) := true.B
-      } .otherwise {
-        wrbypass_ctrs(wrbypass_enq_idx)(b) := newCtrs(b)
-        (0 until BimBanks).foreach(b => wrbypass_ctr_valids(wrbypass_enq_idx)(b) := false.B) // reset valid bits
-        wrbypass_ctr_valids(wrbypass_enq_idx)(b) := true.B
-        wrbypass_rows(wrbypass_enq_idx) := updateRow
-        wrbypass_enq_idx := (wrbypass_enq_idx + 1.U)(log2Up(bypassEntries)-1,0)
+        when (needToUpdate(b)) {
+          wrbypass_ctrs(wrbypass_hit_idx)(b) := newCtrs(b)
+          wrbypass_ctr_valids(wrbypass_hit_idx)(b) := true.B
+        }
+      }.otherwise {
+        wrbypass_ctr_valids(wrbypass_enq_idx)(b) := false.B
+        when (needToUpdate(b)) {
+          wrbypass_ctr_valids(wrbypass_enq_idx)(b) := true.B
+          wrbypass_ctrs(wrbypass_enq_idx)(b) := newCtrs(b)
+          wrbypass_rows(wrbypass_enq_idx) := updateRow
+        }
       }
     }
   }
+  
+  when (needToUpdate.reduce(_||_) && !wrbypass_hit) {
+    wrbypass_enq_idx := (wrbypass_enq_idx + 1.U)(log2Up(bypassEntries)-1,0)
+  }
 
   bim.io.w.apply(
     valid = needToUpdate.asUInt.orR || doing_reset,
@@ -103,15 +110,21 @@ class BIM extends BasePredictor with BimParams {
   )
 
   if (BPUDebug && debug) {
+    val u = io.update.bits
     XSDebug(doing_reset, "Reseting...\n")
     XSDebug("[update] v=%d pc=%x valids=%b, tgt=%x\n", io.update.valid, u.ftqPC, u.valids.asUInt, u.target)
     
     XSDebug("[update] brMask=%b, taken=%b isMisPred=%b\n", u.br_mask.asUInt, newTakens.asUInt, u.mispred.asUInt)
     for (i <- 0 until BimBanks) {
+      XSDebug(RegNext(io.pc.valid && io.inMask(i)), p"BimResp[$i]: ctr = ${io.resp.ctrs(i)}\n")
+      XSDebug(needToUpdate(i),
+        p"update bim bank $i: pc:${Hexadecimal(u.ftqPC)}, taken:${u.takens(i)}, " +
+        p"oldCtr:${oldCtrs(i)}, newCtr:${newCtrs(i)}\n")
+      XSDebug(wrbypass_hit && wrbypass_ctr_valids(wrbypass_hit_idx)(i) && needToUpdate(i),
+        p"bank $i wrbypass hit wridx $wrbypass_hit_idx: row:$updateRow, " +
+        p"ctr:${oldCtrs(i)}, newCtr:${newCtrs(i)}\n")
       XSDebug(true.B, p"bimCtr(${i.U})=${Binary(u.metas(i).bimCtr)} oldCtr=${Binary(oldCtrs(i))} newCtr=${Binary(newCtrs(i))}\n")
     }
-    XSDebug("needToUpdate=%b updateRow=%x\n", needToUpdate.asUInt, updateRow)
-    XSDebug("[wrbypass] hit=%d hits=%b\n", wrbypass_hit, wrbypass_hits.asUInt)
   }
   
 }
\ No newline at end of file
diff --git a/src/main/scala/xiangshan/frontend/SC.scala b/src/main/scala/xiangshan/frontend/SC.scala
index 0f06e95478e..29e05b381af 100644
--- a/src/main/scala/xiangshan/frontend/SC.scala
+++ b/src/main/scala/xiangshan/frontend/SC.scala
@@ -87,18 +87,71 @@ class SCTable(val nRows: Int, val ctrBits: Int, val histLen: Int)
     io.resp(b).ctr := table_r(b)
   })
 
+  val wrBypassEntries = 4
+  
+  val wrbypass_idxs = RegInit(0.U.asTypeOf(Vec(wrBypassEntries, UInt(log2Ceil(nRows).W))))
+  val wrbypass_ctrs = RegInit(0.U.asTypeOf(Vec(wrBypassEntries, Vec(2*TageBanks, SInt(ctrBits.W)))))
+  val wrbypass_ctr_valids = RegInit(0.U.asTypeOf(Vec(wrBypassEntries, Vec(2*TageBanks, Bool()))))
+  val wrbypass_enq_idx = RegInit(0.U(log2Ceil(wrBypassEntries).W))
+
+  when (reset.asBool) {
+    wrbypass_ctr_valids := 0.U.asTypeOf(Vec(wrBypassEntries, Vec(2*TageBanks, Bool())))
+  }
+
+  val wrbypass_hits = VecInit((0 until wrBypassEntries) map (i => wrbypass_idxs(i) === update_idx))
+  val wrbypass_hit = wrbypass_hits.asUInt.orR
+  val wrbypass_hit_idx = ParallelPriorityEncoder(wrbypass_hits)
+
+  for (w <- 0 until TageBanks) {
+    val ctrPos = (w << 1).U | io.update.tagePreds(w).asUInt
+    val altPos = (w << 1).U | ~io.update.tagePreds(w).asUInt
+    val bypass_ctr = wrbypass_ctrs(wrbypass_hit_idx)(ctrPos)
+    val hit_and_valid = wrbypass_hit && wrbypass_ctr_valids(wrbypass_hit_idx)(ctrPos)
+    val oldCtr = Mux(hit_and_valid, wrbypass_ctrs(wrbypass_hit_idx)(ctrPos), io.update.oldCtrs(w))
+    update_wdatas(w) := ctrUpdate(oldCtr, io.update.takens(w))
+
+    when (io.update.mask.reduce(_||_)) {
+      when (wrbypass_hit) {
+        when (io.update.mask(w)) {
+          wrbypass_ctrs(wrbypass_hit_idx)(ctrPos) := update_wdatas(w)
+          wrbypass_ctr_valids(wrbypass_hit_idx)(ctrPos) := true.B
+        }
+      }.otherwise {
+        // reset valid bit first
+        wrbypass_ctr_valids(wrbypass_enq_idx)(ctrPos) := false.B
+        wrbypass_ctr_valids(wrbypass_enq_idx)(altPos) := false.B
+        when (io.update.mask(w)) {
+          wrbypass_ctr_valids(wrbypass_enq_idx)(ctrPos) := true.B
+          wrbypass_ctrs(wrbypass_enq_idx)(w) := update_wdatas(w)
+          wrbypass_idxs(wrbypass_enq_idx) := update_idx
+        }
+      }
+    }
+  }
+
+  when (io.update.mask.reduce(_||_) && !wrbypass_hit) {
+    wrbypass_enq_idx := (wrbypass_enq_idx + 1.U)(log2Ceil(wrBypassEntries)-1,0)
+  }
+
+
   if (BPUDebug && debug) {
     val u = io.update
-    XSDebug(io.req.valid, p"scTableReq: pc=0x${Hexadecimal(io.req.bits.pc)}, " +
-                          p"if2_idx=${if2_idx}, hist=${Hexadecimal(io.req.bits.hist)}, " +
-                          p"if2_mask=${Binary(if2_mask)}\n")
+    XSDebug(io.req.valid,
+      p"scTableReq: pc=0x${Hexadecimal(io.req.bits.pc)}, " +
+      p"if2_idx=${if2_idx}, hist=${Hexadecimal(io.req.bits.hist)}, " +
+      p"if2_mask=${Binary(if2_mask)}\n")
     for (i <- 0 until TageBanks) {
       XSDebug(RegNext(io.req.valid), 
-              p"scTableResp[${i.U}]: if3_idx=${if3_idx}," + 
-              p"ctr:${io.resp(i).ctr}, if3_mask=${Binary(if3_mask)}\n")
+        p"scTableResp[${i.U}]: if3_idx=${if3_idx}," + 
+        p"ctr:${io.resp(i).ctr}, if3_mask=${Binary(if3_mask)}\n")
       XSDebug(io.update.mask(i),
-              p"update Table: pc:${Hexadecimal(u.pc)}, hist:${Hexadecimal(u.hist)}," +
-              p"bank:${i}, tageTaken:${u.tagePreds(i)}, taken:${u.takens(i)}, oldCtr:${u.oldCtrs(i)}\n")
+        p"update Table: pc:${Hexadecimal(u.pc)}, hist:${Hexadecimal(u.hist)}, " +
+        p"bank:${i}, tageTaken:${u.tagePreds(i)}, taken:${u.takens(i)}, oldCtr:${u.oldCtrs(i)}\n")
+      val ctrPos = (i << 1).U | io.update.tagePreds(i).asUInt
+      val hitCtr = wrbypass_ctrs(wrbypass_hit_idx)(ctrPos)
+      XSDebug(wrbypass_hit && wrbypass_ctr_valids(wrbypass_hit_idx)(ctrPos) && io.update.mask(i),
+        p"bank $i wrbypass hit wridx:$wrbypass_hit_idx, idx:$update_idx, ctr:$hitCtr" +
+        p"taken:${io.update.takens(i)} newCtr:${update_wdatas(i)}\n")
     }
   }
 
diff --git a/src/main/scala/xiangshan/frontend/Tage.scala b/src/main/scala/xiangshan/frontend/Tage.scala
index e4e596548cf..88adf743074 100644
--- a/src/main/scala/xiangshan/frontend/Tage.scala
+++ b/src/main/scala/xiangshan/frontend/Tage.scala
@@ -215,7 +215,7 @@ class TageTable(val nRows: Int, val histLen: Int, val tagLen: Int, val uBitPerio
 
   val wrbypass_hit      = wrbypass_hits.reduce(_||_)
   // val wrbypass_rhit     = wrbypass_rhits.reduce(_||_)
-  val wrbypass_hit_idx  = PriorityEncoder(wrbypass_hits)
+  val wrbypass_hit_idx  = ParallelPriorityEncoder(wrbypass_hits)
   // val wrbypass_rhit_idx = PriorityEncoder(wrbypass_rhits)
 
   // val wrbypass_rctr_hits = VecInit((0 until TageBanks).map( b => wrbypass_ctr_valids(wrbypass_rhit_idx)(b)))
@@ -248,50 +248,59 @@ class TageTable(val nRows: Int, val histLen: Int, val tagLen: Int, val uBitPerio
 
     update_hi_wdata(w)    := io.update.u(w)(1)
     update_lo_wdata(w)    := io.update.u(w)(0)
-  }
 
-  when (io.update.mask.reduce(_||_)) {
-    when (wrbypass_hits.reduce(_||_)) {
-      wrbypass_ctrs(wrbypass_hit_idx)(updateBank) := update_wdata(updateBank).ctr
-      wrbypass_ctr_valids(wrbypass_hit_idx)(updateBank) := true.B
-    } .otherwise {
-      wrbypass_ctrs(wrbypass_enq_idx)(updateBank) := update_wdata(updateBank).ctr
-      (0 until TageBanks).foreach(b => wrbypass_ctr_valids(wrbypass_enq_idx)(b) := false.B) // reset valid bits
-      wrbypass_ctr_valids(wrbypass_enq_idx)(updateBank) := true.B
-      wrbypass_tags(wrbypass_enq_idx) := update_tag
-      wrbypass_idxs(wrbypass_enq_idx) := update_idx
-      wrbypass_enq_idx := (wrbypass_enq_idx + 1.U)(log2Ceil(wrBypassEntries)-1,0)
+    when (io.update.mask.reduce(_||_)) {
+      when (wrbypass_hit) {
+        when (io.update.mask(w)) {
+          wrbypass_ctrs(wrbypass_hit_idx)(w) := update_wdata(w).ctr
+          wrbypass_ctr_valids(wrbypass_hit_idx)(w) := true.B
+        }
+      } .otherwise {
+        // reset valid bit first
+        wrbypass_ctr_valids(wrbypass_enq_idx)(w) := false.B
+        when (io.update.mask(w)) {
+          wrbypass_ctr_valids(wrbypass_enq_idx)(w) := true.B
+          wrbypass_ctrs(wrbypass_enq_idx)(w) := update_wdata(w).ctr
+          wrbypass_tags(wrbypass_enq_idx) := update_tag
+          wrbypass_idxs(wrbypass_enq_idx) := update_idx
+        }
+      }
     }
   }
 
+  when (io.update.mask.reduce(_||_) && !wrbypass_hit) {
+    wrbypass_enq_idx := (wrbypass_enq_idx + 1.U)(log2Ceil(wrBypassEntries)-1,0)
+  }
+
+
   if (BPUDebug && debug) {
     val u = io.update
     val b = PriorityEncoder(u.mask)
     val ub = PriorityEncoder(u.uMask)
     val idx = if2_idx
     val tag = if2_tag
-    XSDebug(io.req.valid, "tableReq: pc=0x%x, hist=%x, idx=%d, tag=%x, mask=%b, mask=%b\n",
-      io.req.bits.pc, io.req.bits.hist, idx, tag, io.req.bits.mask, if2_mask)
+    XSDebug(io.req.valid, 
+      p"tableReq: pc=0x${Hexadecimal(io.req.bits.pc)}, " +
+      p"hist=${Hexadecimal(io.req.bits.hist)}, idx=$idx, " +
+      p"tag=$tag, mask=${Binary(if2_mask)}\n")
     for (i <- 0 until TageBanks) {
-      XSDebug(RegNext(io.req.valid) && if3_req_rhits(i), "TageTableResp[%d]: idx=%d, hit:%d, ctr:%d, u:%d\n",
-        i.U, if3_idx, if3_req_rhits(i), io.resp(i).bits.ctr, io.resp(i).bits.u)
+      XSDebug(RegNext(io.req.valid && io.req.bits.mask(i)) && if3_req_rhits(i),
+        p"TageTableResp[$i]: idx=$if3_idx, hit:${if3_req_rhits(i)}, " +
+        p"ctr:${io.resp(i).bits.ctr}, u:${io.resp(i).bits.u}\n")
+      XSDebug(io.update.mask(i),
+        p"update Table bank $i: pc:${Hexadecimal(u.pc)}, hist:${Hexadecimal(u.hist)}, " +
+        p"taken:${u.taken(i)}, alloc:${u.alloc(i)}, oldCtr:${u.oldCtr(i)}\n")
+      XSDebug(io.update.mask(i),
+        p"update Table bank $i: writing tag:${update_tag}, " +
+        p"ctr: ${update_wdata(b).ctr} in idx $update_idx\n")
+      val hitCtr = wrbypass_ctrs(wrbypass_hit_idx)(i)
+      XSDebug(wrbypass_hit && wrbypass_ctr_valids(wrbypass_hit_idx)(i) && io.update.mask(i),
+        p"bank $i wrbypass hit wridx:$wrbypass_hit_idx, idx:$update_idx, tag: $update_tag, " +
+        p"ctr:$hitCtr, newCtr:${update_wdata(i).ctr}")
     }
 
-    XSDebug(RegNext(io.req.valid), "TageTableResp: hits:%b, maskLatch is %b\n", if3_req_rhits.asUInt, if3_mask)
     XSDebug(RegNext(io.req.valid) && !if3_req_rhits.reduce(_||_), "TageTableResp: no hits!\n")
 
-    XSDebug(io.update.mask.reduce(_||_), "update Table: pc:%x, hist:%x, bank:%d, taken:%d, alloc:%d, oldCtr:%d\n",
-      u.pc, u.hist, b, u.taken(b), u.alloc(b), u.oldCtr(b))
-    XSDebug(io.update.mask.reduce(_||_), "update Table: writing tag:%b, ctr%d in idx:%d\n",
-      update_wdata(b).tag, update_wdata(b).ctr, update_idx)
-    XSDebug(io.update.mask.reduce(_||_), "update u: pc:%x, hist:%x, bank:%d, writing in u:%b\n",
-      u.pc, u.hist, ub, io.update.u(ub))
-
-    val updateBank = PriorityEncoder(io.update.mask)
-    XSDebug(wrbypass_hit && wrbypass_ctr_valids(wrbypass_hit_idx)(updateBank),
-      "wrbypass hits, wridx:%d, tag:%x, idx:%d, hitctr:%d, bank:%d\n",
-      wrbypass_hit_idx, update_tag, update_idx, wrbypass_ctrs(wrbypass_hit_idx)(updateBank), updateBank)
-
     // when (wrbypass_rhit && wrbypass_ctr_valids(wrbypass_rhit_idx).reduce(_||_)) {
     //   for (b <- 0 until TageBanks) {
     //     XSDebug(wrbypass_ctr_valids(wrbypass_rhit_idx)(b),

From 561d7267e0c3acccddb4008b129b68dbd8135498 Mon Sep 17 00:00:00 2001
From: Lingrui98 <goulingrui15@gmail.com>
Date: Fri, 26 Feb 2021 20:00:45 +0800
Subject: [PATCH 06/12] sc: restrict threshold update conditions and prevent
 overflow problem

---
 src/main/scala/xiangshan/frontend/SC.scala | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/xiangshan/frontend/SC.scala b/src/main/scala/xiangshan/frontend/SC.scala
index 29e05b381af..860fc40c790 100644
--- a/src/main/scala/xiangshan/frontend/SC.scala
+++ b/src/main/scala/xiangshan/frontend/SC.scala
@@ -168,8 +168,8 @@ class SCThreshold(val ctrBits: Int = 5) extends SCBundle {
   def update(cause: Bool): SCThreshold = {
     val res = Wire(new SCThreshold(this.ctrBits))
     val newCtr = satUpdate(this.ctr, this.ctrBits, cause)
-    val newThres = Mux(res.satPos(newCtr), this.thres + 1.U,
-                      Mux(res.satNeg(newCtr), this.thres - 1.U,
+    val newThres = Mux(res.satPos(newCtr) && this.thres <= maxThres, this.thres + 2.U,
+                      Mux(res.satNeg(newCtr) && this.thres >= minThres, this.thres - 2.U,
                       this.thres))
     res.thres := newThres
     res.ctr := Mux(res.satPos(newCtr) || res.satNeg(newCtr), res.neutralVal, newCtr)
@@ -280,10 +280,10 @@ trait HasSC extends HasSCParameter { this: Tage =>
       scUpdateTakens(w) := taken
       (scUpdateOldCtrs(w) zip scOldCtrs).foreach{case (t, c) => t := c}
 
-      when (scPred =/= tagePred && sumAbs < useThreshold - 2.U) {
+      when (scPred =/= tagePred && sumAbs <= useThreshold - 2.U && sumAbs >= useThreshold - 4.U) {
         val newThres = scThreshold.update(scPred =/= taken)
         scThreshold := newThres
-        XSDebug(p"scThres update: old d${useThreshold} --> new ${newThres.thres}\n")
+        XSDebug(p"scThres update: old ${useThreshold} --> new ${newThres.thres}\n")
       }
       when (scPred =/= taken || sumAbs < updateThreshold) {
         scUpdateMask.foreach(t => t(w) := true.B)

From e66e131f097ebaaea41973ad343158dccd13ff53 Mon Sep 17 00:00:00 2001
From: Lingrui98 <goulingrui15@gmail.com>
Date: Fri, 26 Feb 2021 20:27:06 +0800
Subject: [PATCH 07/12] sc: use seperative thresholds for each bank

---
 src/main/scala/xiangshan/frontend/SC.scala | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/main/scala/xiangshan/frontend/SC.scala b/src/main/scala/xiangshan/frontend/SC.scala
index 860fc40c790..877e24469fe 100644
--- a/src/main/scala/xiangshan/frontend/SC.scala
+++ b/src/main/scala/xiangshan/frontend/SC.scala
@@ -202,9 +202,9 @@ trait HasSC extends HasSCParameter { this: Tage =>
     }
   }
   
-  val scThreshold = RegInit(SCThreshold(5))
-  val useThreshold = WireInit(scThreshold.thres)
-  val updateThreshold = WireInit((useThreshold << 3) + 21.U)
+  val scThresholds = List.fill(TageBanks)(RegInit(SCThreshold(5)))
+  val useThresholds = VecInit(scThresholds map (_.thres))
+  val updateThresholds = VecInit(useThresholds map (t => (t << 3) + 21.U))
   
   val if3_scResps = VecInit(scTables.map(t => t.io.resp))
 
@@ -240,7 +240,7 @@ trait HasSC extends HasSCParameter { this: Tage =>
     val if3_pvdrCtrCentered = getPvdrCentered(providerCtr)
     val if3_totalSums = VecInit(if3_scTableSums.map(_  + if3_pvdrCtrCentered))
     val if3_sumAbs = VecInit(if3_totalSums.map(_.abs.asUInt))
-    val if3_sumBelowThresholds = VecInit(if3_sumAbs.map(_ < useThreshold))
+    val if3_sumBelowThresholds = VecInit(if3_sumAbs zip useThresholds map {case (s, t) => s < t})
     val if3_scPreds = VecInit(if3_totalSums.map (_ >= 0.S))
 
     val if4_sumBelowThresholds = RegEnable(if3_sumBelowThresholds, s3_fire)
@@ -280,12 +280,12 @@ trait HasSC extends HasSCParameter { this: Tage =>
       scUpdateTakens(w) := taken
       (scUpdateOldCtrs(w) zip scOldCtrs).foreach{case (t, c) => t := c}
 
-      when (scPred =/= tagePred && sumAbs <= useThreshold - 2.U && sumAbs >= useThreshold - 4.U) {
-        val newThres = scThreshold.update(scPred =/= taken)
-        scThreshold := newThres
-        XSDebug(p"scThres update: old ${useThreshold} --> new ${newThres.thres}\n")
+      when (scPred =/= tagePred && sumAbs <= useThresholds(w) - 2.U && sumAbs >= useThresholds(w) - 4.U) {
+        val newThres = scThresholds(w).update(scPred =/= taken)
+        scThresholds(w) := newThres
+        XSDebug(p"scThres update: old ${useThresholds(w)} --> new ${newThres.thres}\n")
       }
-      when (scPred =/= taken || sumAbs < updateThreshold) {
+      when (scPred =/= taken || sumAbs < updateThresholds(w)) {
         scUpdateMask.foreach(t => t(w) := true.B)
         XSDebug(sum < 0.S,
           p"scUpdate: bank(${w}), scPred(${scPred}), tagePred(${tagePred}), " +

From 3e382cd3aee06e372a076dec53696ac9e43c9cba Mon Sep 17 00:00:00 2001
From: Lingrui98 <goulingrui15@gmail.com>
Date: Tue, 2 Mar 2021 20:19:19 +0800
Subject: [PATCH 08/12] sc: update debug info

---
 src/main/scala/xiangshan/frontend/SC.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/xiangshan/frontend/SC.scala b/src/main/scala/xiangshan/frontend/SC.scala
index fda821bee9b..4ebaf6f25a8 100644
--- a/src/main/scala/xiangshan/frontend/SC.scala
+++ b/src/main/scala/xiangshan/frontend/SC.scala
@@ -285,7 +285,7 @@ trait HasSC extends HasSCParameter { this: Tage =>
       when (scPred =/= tagePred && sumAbs <= useThresholds(w) - 2.U && sumAbs >= useThresholds(w) - 4.U) {
         val newThres = scThresholds(w).update(scPred =/= taken)
         scThresholds(w) := newThres
-        XSDebug(p"scThres update: old ${useThresholds(w)} --> new ${newThres.thres}\n")
+        XSDebug(p"scThres $w update: old ${useThresholds(w)} --> new ${newThres.thres}\n")
       }
       when (scPred =/= taken || sumAbs < updateThresholds(w)) {
         scUpdateMask.foreach(t => t(w) := true.B)

From ba8cb2c2e8547c9341975d66afba67972834583b Mon Sep 17 00:00:00 2001
From: Lingrui98 <goulingrui15@gmail.com>
Date: Thu, 4 Mar 2021 19:00:22 +0800
Subject: [PATCH 09/12] sc: use adaptive threshold algorithm from the original
 O-GEHL

---
 src/main/scala/xiangshan/frontend/SC.scala | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/src/main/scala/xiangshan/frontend/SC.scala b/src/main/scala/xiangshan/frontend/SC.scala
index 4ebaf6f25a8..77c0e77e1d4 100644
--- a/src/main/scala/xiangshan/frontend/SC.scala
+++ b/src/main/scala/xiangshan/frontend/SC.scala
@@ -157,14 +157,14 @@ class SCTable(val nRows: Int, val ctrBits: Int, val histLen: Int)
 
 }
 
-class SCThreshold(val ctrBits: Int = 5) extends SCBundle {
+class SCThreshold(val ctrBits: Int = 6) extends SCBundle {
   val ctr = UInt(ctrBits.W)
   def satPos(ctr: UInt = this.ctr) = ctr === ((1.U << ctrBits) - 1.U)
   def satNeg(ctr: UInt = this.ctr) = ctr === 0.U
   def neutralVal = (1.U << (ctrBits - 1))
-  val thres = UInt(5.W)
-  def minThres = 5.U
-  def maxThres = 31.U
+  val thres = UInt(8.W)
+  def minThres = 6.U
+  def maxThres = 255.U
   def update(cause: Bool): SCThreshold = {
     val res = Wire(new SCThreshold(this.ctrBits))
     val newCtr = satUpdate(this.ctr, this.ctrBits, cause)
@@ -282,12 +282,11 @@ trait HasSC extends HasSCParameter { this: Tage =>
       scUpdateTakens(w) := taken
       (scUpdateOldCtrs(w) zip scOldCtrs).foreach{case (t, c) => t := c}
 
-      when (scPred =/= tagePred && sumAbs <= useThresholds(w) - 2.U && sumAbs >= useThresholds(w) - 4.U) {
+      when (scPred =/= taken || sumAbs < useThresholds(w)) {
         val newThres = scThresholds(w).update(scPred =/= taken)
         scThresholds(w) := newThres
         XSDebug(p"scThres $w update: old ${useThresholds(w)} --> new ${newThres.thres}\n")
-      }
-      when (scPred =/= taken || sumAbs < updateThresholds(w)) {
+
         scUpdateMask.foreach(t => t(w) := true.B)
         XSDebug(sum < 0.S,
           p"scUpdate: bank(${w}), scPred(${scPred}), tagePred(${tagePred}), " +

From d01fa15966a2a96d2e8cebdf00910686ca0f7b84 Mon Sep 17 00:00:00 2001
From: Lingrui98 <goulingrui15@gmail.com>
Date: Thu, 4 Mar 2021 21:04:59 +0800
Subject: [PATCH 10/12] tage, bim, sc: optimize wrbypass logic

---
 src/main/scala/xiangshan/frontend/Bim.scala  | 2 +-
 src/main/scala/xiangshan/frontend/SC.scala   | 4 ++--
 src/main/scala/xiangshan/frontend/Tage.scala | 6 +++---
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/main/scala/xiangshan/frontend/Bim.scala b/src/main/scala/xiangshan/frontend/Bim.scala
index 73759a1f1c7..3cccb938bf3 100644
--- a/src/main/scala/xiangshan/frontend/Bim.scala
+++ b/src/main/scala/xiangshan/frontend/Bim.scala
@@ -94,13 +94,13 @@ class BIM extends BasePredictor with BimParams {
         when (needToUpdate(b)) {
           wrbypass_ctr_valids(wrbypass_enq_idx)(b) := true.B
           wrbypass_ctrs(wrbypass_enq_idx)(b) := newCtrs(b)
-          wrbypass_rows(wrbypass_enq_idx) := updateRow
         }
       }
     }
   }
   
   when (needToUpdate.reduce(_||_) && !wrbypass_hit) {
+    wrbypass_rows(wrbypass_enq_idx) := updateRow
     wrbypass_enq_idx := (wrbypass_enq_idx + 1.U)(log2Up(bypassEntries)-1,0)
   }
 
diff --git a/src/main/scala/xiangshan/frontend/SC.scala b/src/main/scala/xiangshan/frontend/SC.scala
index 77c0e77e1d4..8a7a02910da 100644
--- a/src/main/scala/xiangshan/frontend/SC.scala
+++ b/src/main/scala/xiangshan/frontend/SC.scala
@@ -123,13 +123,13 @@ class SCTable(val nRows: Int, val ctrBits: Int, val histLen: Int)
         when (io.update.mask(w)) {
           wrbypass_ctr_valids(wrbypass_enq_idx)(ctrPos) := true.B
           wrbypass_ctrs(wrbypass_enq_idx)(w) := update_wdatas(w)
-          wrbypass_idxs(wrbypass_enq_idx) := update_idx
         }
       }
     }
   }
-
+  
   when (io.update.mask.reduce(_||_) && !wrbypass_hit) {
+    wrbypass_idxs(wrbypass_enq_idx) := update_idx
     wrbypass_enq_idx := (wrbypass_enq_idx + 1.U)(log2Ceil(wrBypassEntries)-1,0)
   }
 
diff --git a/src/main/scala/xiangshan/frontend/Tage.scala b/src/main/scala/xiangshan/frontend/Tage.scala
index 2dae24ded80..0c574a786ef 100644
--- a/src/main/scala/xiangshan/frontend/Tage.scala
+++ b/src/main/scala/xiangshan/frontend/Tage.scala
@@ -261,14 +261,14 @@ class TageTable(val nRows: Int, val histLen: Int, val tagLen: Int, val uBitPerio
         when (io.update.mask(w)) {
           wrbypass_ctr_valids(wrbypass_enq_idx)(w) := true.B
           wrbypass_ctrs(wrbypass_enq_idx)(w) := update_wdata(w).ctr
-          wrbypass_tags(wrbypass_enq_idx) := update_tag
-          wrbypass_idxs(wrbypass_enq_idx) := update_idx
         }
       }
     }
   }
-
+  
   when (io.update.mask.reduce(_||_) && !wrbypass_hit) {
+    wrbypass_tags(wrbypass_enq_idx) := update_tag
+    wrbypass_idxs(wrbypass_enq_idx) := update_idx
     wrbypass_enq_idx := (wrbypass_enq_idx + 1.U)(log2Ceil(wrBypassEntries)-1,0)
   }
 

From 08b1b2b0067ce03ee533203d0f3cc1ca4cb9f281 Mon Sep 17 00:00:00 2001
From: Lingrui98 <goulingrui15@gmail.com>
Date: Fri, 5 Mar 2021 14:36:36 +0800
Subject: [PATCH 11/12] sc: initialize threshold to 60

---
 src/main/scala/xiangshan/frontend/SC.scala | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/xiangshan/frontend/SC.scala b/src/main/scala/xiangshan/frontend/SC.scala
index 8a7a02910da..b157d20a1c0 100644
--- a/src/main/scala/xiangshan/frontend/SC.scala
+++ b/src/main/scala/xiangshan/frontend/SC.scala
@@ -163,6 +163,7 @@ class SCThreshold(val ctrBits: Int = 6) extends SCBundle {
   def satNeg(ctr: UInt = this.ctr) = ctr === 0.U
   def neutralVal = (1.U << (ctrBits - 1))
   val thres = UInt(8.W)
+  def initVal = 60.U
   def minThres = 6.U
   def maxThres = 255.U
   def update(cause: Bool): SCThreshold = {
@@ -182,7 +183,7 @@ object SCThreshold {
   def apply(bits: Int) = {
     val t = Wire(new SCThreshold(ctrBits=bits))
     t.ctr := t.neutralVal
-    t.thres := t.minThres
+    t.thres := t.initVal
     t
   }
 }

From 8c20acfde26d95944a1861160d831ebb1b71a84c Mon Sep 17 00:00:00 2001
From: Lingrui98 <goulingrui15@gmail.com>
Date: Fri, 5 Mar 2021 20:26:07 +0800
Subject: [PATCH 12/12] loop: remove unuseful RegNext on redirect

---
 src/main/scala/xiangshan/frontend/LoopPredictor.scala | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/main/scala/xiangshan/frontend/LoopPredictor.scala b/src/main/scala/xiangshan/frontend/LoopPredictor.scala
index 431a74b9843..8ce7f7e08ab 100644
--- a/src/main/scala/xiangshan/frontend/LoopPredictor.scala
+++ b/src/main/scala/xiangshan/frontend/LoopPredictor.scala
@@ -338,9 +338,8 @@ class LoopPredictor extends BasePredictor with LTBParams {
   val updateValid = io.update.valid
   val update = io.update.bits
 
-  val do_redirect = RegNext(io.redirect)
-  val redirectValid = do_redirect.valid
-  val redirect = do_redirect.bits.cfiUpdate
+  val redirectValid = io.redirect.valid
+  val redirect = io.redirect.bits.cfiUpdate
   val redirectPC = redirect.pc
   val redirectBank = ltbAddr.getBank(redirectPC)
  
@@ -363,7 +362,7 @@ class LoopPredictor extends BasePredictor with LTBParams {
     ltbs(i).io.redirect.bits.specCnt := redirect.specCnt(i)
     ltbs(i).io.redirect.bits.mispred := redirect.isMisPred
     ltbs(i).io.redirect.bits.taken := redirect.taken
-    ltbs(i).io.redirect.bits.isReplay := do_redirect.bits.flushItself
+    ltbs(i).io.redirect.bits.isReplay := io.redirect.bits.flushItself
 
     ltbs(i).io.repair := redirectValid && redirectBank =/= i.U
   }
@@ -394,7 +393,7 @@ class LoopPredictor extends BasePredictor with LTBParams {
     XSDebug("[IF4][req] inMask=%b\n", inMask)
 
     XSDebug("[IF4][req] updatePC=%x, updateValid=%d, isBr=%b\n", update.ftqPC, updateValid, update.br_mask.asUInt)
-    XSDebug("[IF4][req] redirectPC=%x redirectBank=%d, redirectValid=%d, isBr=%d, isReplay=%d\n", redirect.pc, redirectBank, redirectValid, redirect.pd.isBr, do_redirect.bits.flushItself)
+    XSDebug("[IF4][req] redirectPC=%x redirectBank=%d, redirectValid=%d, isBr=%d, isReplay=%d\n", redirect.pc, redirectBank, redirectValid, redirect.pd.isBr, io.redirect.bits.flushItself)
     XSDebug("[IF4][req] isMisPred=%d\n", redirect.isMisPred)
 
     XSDebug(redirectValid, "[redirect SpecCnt] ")