Commit f07ac8e
[XLA:CPU] Include
Remaining tileable ops will be tiled to size 1 and scalarized.
PiperOrigin-RevId: 507850026gml-tile-by-one pass in CPU pipeline before scalarization1 parent b677392 commit f07ac8e
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lines changed- tensorflow/compiler/xla/mlir_hlo
- gml_st/transforms/cpu_tiling
- tests/Dialect/gml_st/cpu_tiling
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