add vllm github link

Author: alec-flowers

components/backends/vllm/src/dynamo/vllm/args.py

@@ -163,6 +163,7 @@ async def configure_ports_with_etcd(config: Config, etcd_client):
         logger.info(f"Allocated ZMQ KV events port: {kv_port} (worker_id={worker_id})")
 
     # Allocate side channel ports
+    # https://github.com/vllm-project/vllm/blob/releases/v0.10.0/vllm/distributed/kv_transfer/kv_connector/v1/nixl_connector.py#L372
     # NIXL calculates ports as: base_port + (dp_rank * tp_size) + tp_rank
     # For dp_rank, we need to reserve tp_size consecutive ports
     tp_size = config.engine_args.tensor_parallel_size or 1
@@ -180,17 +181,16 @@ async def configure_ports_with_etcd(config: Config, etcd_client):
     first_port_for_dp_rank = allocated_ports[0]
 
     # Calculate the base port that NIXL expects
-    # first_port_for_dp_rank = base_port + (dp_rank * tp_size)
-    # Therefore: base_port = first_port_for_dp_rank - (dp_rank * tp_size)
+    # base_port = first_port_for_dp_rank - (dp_rank * tp_size)
     nixl_offset = dp_rank * tp_size
     base_side_channel_port = first_port_for_dp_rank - nixl_offset
 
-    # Validate that the base port is still valid
     if base_side_channel_port < 0:
         raise ValueError(
             f"NIXL base port calculation resulted in negative port: "
             f"first_allocated_port={first_port_for_dp_rank}, offset={nixl_offset}, "
-            f"base_port={base_side_channel_port}. Consider using a higher port range."
+            f"base_port={base_side_channel_port}. Current range: {config.port_range.min}-{config.port_range.max}. "
+            f"Consider using a higher port range."
         )
 
     config.side_channel_port = base_side_channel_port