From 6361f7794205e1fb0f3ce3589a1b8ece37cbaa93 Mon Sep 17 00:00:00 2001 From: billue Date: Sun, 15 Dec 2019 03:19:58 +0800 Subject: [PATCH 01/44] add hdl nh7020 --- projects/nh7020/Makefile | 6 + projects/nh7020/README.md | 64 +++ projects/nh7020/ccbob_cmos/Makefile | 26 + projects/nh7020/ccbob_cmos/system_bd.tcl | 11 + projects/nh7020/ccbob_cmos/system_project.tcl | 17 + projects/nh7020/ccbob_cmos/system_top.v | 223 ++++++++ projects/nh7020/ccbob_lvds/Makefile | 27 + projects/nh7020/ccbob_lvds/ad5683_spi.v | 71 +++ projects/nh7020/ccbob_lvds/system_bd.tcl | 8 + projects/nh7020/ccbob_lvds/system_project.tcl | 18 + projects/nh7020/ccbob_lvds/system_top.v | 243 +++++++++ projects/nh7020/common/adrv9364z7020_bd.tcl | 480 ++++++++++++++++++ .../nh7020/common/adrv9364z7020_constr.xdc | 196 +++++++ .../common/adrv9364z7020_constr_cmos.xdc | 41 ++ .../common/adrv9364z7020_constr_lvds.xdc | 41 ++ projects/nh7020/common/ccbob_bd.tcl | 19 + projects/nh7020/common/ccbob_constr.xdc | 82 +++ 17 files changed, 1573 insertions(+) create mode 100644 projects/nh7020/Makefile create mode 100644 projects/nh7020/README.md create mode 100644 projects/nh7020/ccbob_cmos/Makefile create mode 100644 projects/nh7020/ccbob_cmos/system_bd.tcl create mode 100644 projects/nh7020/ccbob_cmos/system_project.tcl create mode 100644 projects/nh7020/ccbob_cmos/system_top.v create mode 100644 projects/nh7020/ccbob_lvds/Makefile create mode 100644 projects/nh7020/ccbob_lvds/ad5683_spi.v create mode 100644 projects/nh7020/ccbob_lvds/system_bd.tcl create mode 100644 projects/nh7020/ccbob_lvds/system_project.tcl create mode 100644 projects/nh7020/ccbob_lvds/system_top.v create mode 100644 projects/nh7020/common/adrv9364z7020_bd.tcl create mode 100644 projects/nh7020/common/adrv9364z7020_constr.xdc create mode 100644 projects/nh7020/common/adrv9364z7020_constr_cmos.xdc create mode 100644 projects/nh7020/common/adrv9364z7020_constr_lvds.xdc create mode 100644 projects/nh7020/common/ccbob_bd.tcl create mode 100644 projects/nh7020/common/ccbob_constr.xdc diff --git a/projects/nh7020/Makefile b/projects/nh7020/Makefile new file mode 100644 index 00000000000..4af18d6e7d7 --- /dev/null +++ b/projects/nh7020/Makefile @@ -0,0 +1,6 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/nh7020/README.md b/projects/nh7020/README.md new file mode 100644 index 00000000000..6826ce45c4e --- /dev/null +++ b/projects/nh7020/README.md @@ -0,0 +1,64 @@ +# ADRV9364Z7020 SDR SOM + +This folder contains the ADRV9364Z7020 SOM projects for each of the carrier boards. + +# Supported SOM & Carriers + +|Directory | Description | +|---------------|----------------------------------------------------| +|ccbob\_cmos | ADRV9364Z7020\-SOM (CMOS Mode) \+ ADRV1CRR\-BOB | +|ccbob\_lvds | ADRV9364Z7020\-SOM (LVDS Mode) \+ ADRV1CRR\-BOB | +|ccbox\_lvds | ADRV9364Z7020\-SOM (LVDS Mode) \+ ADRV1CRR\-BOX | +|ccusb\_lvds | ADRV9364Z7020\-SOM (LVDS Mode) \+ ADRV1CRR\-USB | + +## Board Design Files (Vivado IPI) + +|Directory/File | Description | +|-----------------------------|----------------------------------------| +|common/ADRV9364Z7020\_bd.tcl | ADRV9364Z7020\-SOM board design file. | +|common/ccbob\_bd.tcl | carrier, break out board design file. | +|common/ccbox\_bd.tcl | carrier, box board design file. | +|common/ccusb\_bd.tcl | carrier, usb board design file. | + +FMC & BOB carrier designs includes loopback daughtercards for connectivity testing. + +## Board Constraint Files (pin-out & io-standard) + +|Directory/File | Description | +|----------------------------------------|-------------------------------------------------| +|common/ADRV9364Z7020\_constr.xdc | ADRV9364Z7020\-SOM base constraints file. | +|common/ADRV9364Z7020\_constr\_cmos.xdc | ADRV9364Z7020\-SOM CMOS mode constraints file. | +|common/ADRV9364Z7020\_constr\_lvds.xdc | ADRV9364Z7020\-SOM LVDS mode constraints file. | +|common/ccbob\_constr.xdc | carrier, break out board constraints file. | +|common/ccbox\_constr.xdc | carrier, box board constraints file. | +|common/ccusb\_constr.xdc | carrier, usb board constraints file. | + +FMC & BOB carrier designs includes loopback daughtercards for connectivity testing. + +## Building, Generating Bit Files (easy & efficient method) +``` +[some-directory]> git clone -b dev git@github.com:analogdevicesinc/hdl.git +[some-directory]> make -C hdl/projects/adrv9364z7020/ccbob_cmos +``` + +## Building, Generating Elf Files (easy & efficient method) +``` +[some-directory]> git clone -b dev git@github.com:analogdevicesinc/no-OS.git +[some-directory]> make -C no-OS/adrv9364z7020/ccbob_cmos +``` + +## Running, a quick test (easy & efficient method) +``` +[some-directory]> make -C no-OS/adrv9364z7020/ccbob_cmos run +``` + +## Documentation + + * [HDL Design User Guide] + * [IP User Guide] + * [ADRV9364Z7020 Wiki page] + +[HDL Design User Guide]:http://wiki.analog.com/resources/fpga/docs/hdl +[IP User Guide]:http://wiki.analog.com/resources/fpga/docs/axi_ad9361 +[ADRV9364Z7020 Wiki page]:https://wiki.analog.com/resources/eval/user-guides/picozed_sdr + diff --git a/projects/nh7020/ccbob_cmos/Makefile b/projects/nh7020/ccbob_cmos/Makefile new file mode 100644 index 00000000000..923023cd1b4 --- /dev/null +++ b/projects/nh7020/ccbob_cmos/Makefile @@ -0,0 +1,26 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := adrv9364z7020_ccbob_cmos + +M_DEPS += ../common/ccbob_constr.xdc +M_DEPS += ../common/ccbob_bd.tcl +M_DEPS += ../common/adrv9364z7020_constr_cmos.xdc +M_DEPS += ../common/adrv9364z7020_constr.xdc +M_DEPS += ../common/adrv9364z7020_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl + +LIB_DEPS += axi_ad9361 +LIB_DEPS += axi_dmac +LIB_DEPS += axi_gpreg +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 +LIB_DEPS += util_rfifo +LIB_DEPS += util_tdd_sync +LIB_DEPS += util_wfifo +LIB_DEPS += xilinx/util_clkdiv + +include ../../scripts/project-xilinx.mk diff --git a/projects/nh7020/ccbob_cmos/system_bd.tcl b/projects/nh7020/ccbob_cmos/system_bd.tcl new file mode 100644 index 00000000000..08f42059354 --- /dev/null +++ b/projects/nh7020/ccbob_cmos/system_bd.tcl @@ -0,0 +1,11 @@ + +source ../common/adrv9364z7020_bd.tcl +source ../common/ccbob_bd.tcl + +ad_ip_parameter util_ad9361_divclk CONFIG.SEL_0_DIV 2 +ad_ip_parameter util_ad9361_divclk CONFIG.SEL_1_DIV 1 + +cfg_ad9361_interface CMOS + +set_property CONFIG.ADC_INIT_DELAY 30 [get_bd_cells axi_ad9361] + diff --git a/projects/nh7020/ccbob_cmos/system_project.tcl b/projects/nh7020/ccbob_cmos/system_project.tcl new file mode 100644 index 00000000000..05f5438089c --- /dev/null +++ b/projects/nh7020/ccbob_cmos/system_project.tcl @@ -0,0 +1,17 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z020clg400-1" +adi_project adrv9364z7020_ccbob_cmos +adi_project_files adrv9364z7020_ccbob_cmos [list \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "../common/adrv9364z7020_constr.xdc" \ + "../common/adrv9364z7020_constr_cmos.xdc" \ + "../common/ccbob_constr.xdc" \ + "system_top.v" ] + +adi_project_run adrv9364z7020_ccbob_cmos +source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl + diff --git a/projects/nh7020/ccbob_cmos/system_top.v b/projects/nh7020/ccbob_cmos/system_top.v new file mode 100644 index 00000000000..778646ce626 --- /dev/null +++ b/projects/nh7020/ccbob_cmos/system_top.v @@ -0,0 +1,223 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout iic_scl, + inout iic_sda, + + inout [10:0] gpio_bd, + + input rx_clk_in, + input rx_frame_in, + input [11:0] rx_data_in, + output tx_clk_out, + output tx_frame_out, + output [11:0] tx_data_out, + output [ 1:0] tx_gnd, + + output enable, + output txnrx, + input clkout_in, + output clkout_out, + + inout gpio_clksel, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, + + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso, + + output [21:0] gp_out, + input [21:0] gp_in, + + output dac_spi_sdi, + output dac_spi_sclk, + output dac_spi_sync_n, + + input clk_40mhz +); + + + // internal signals + + wire [31:0] gp_out_s; + wire [31:0] gp_in_s; + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + wire clk_40_ibuf_s; + // assignments + + assign tx_gnd = 2'd0; + assign clkout_out = clkout_in; + assign gp_out[21:10] = gp_out_s[21:10]; + assign gp_out[7:4] = gp_out_s[7:4]; + assign gp_in_s[31:28] = gp_out_s[31:28]; + assign gp_in_s[21: 0] = gp_in[21:0]; + + + //CLK_40 + IBUFG clk_40_buf( + .I(clk_40mhz), + .O(clk_40_ibuf_s) + ); + + // board gpio - 31-0 + + assign gpio_i[31:11] = gpio_o[31:11]; + + ad_iobuf #(.DATA_WIDTH(11)) i_iobuf_bd ( + .dio_t (gpio_t[10:0]), + .dio_i (gpio_o[10:0]), + .dio_o (gpio_i[10:0]), + .dio_p (gpio_bd)); + + // ad9361 gpio - 63-32 + + assign gpio_i[63:52] = gpio_o[63:52]; + assign gpio_i[50:47] = gpio_o[50:47]; + + ad_iobuf #(.DATA_WIDTH(16)) i_iobuf ( + .dio_t ({gpio_t[51], gpio_t[46:32]}), + .dio_i ({gpio_o[51], gpio_o[46:32]}), + .dio_o ({gpio_i[51], gpio_i[46:32]}), + .dio_p ({ gpio_clksel, // 51:51 + gpio_resetb, // 46:46 + gpio_sync, // 45:45 + gpio_en_agc, // 44:44 + gpio_ctl, // 43:40 + gpio_status})); // 39:32 + + // instantiations + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gp_in_0 (gp_in_s[31:0]), + .gp_out_0 (gp_out_s[31:0]), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .gps_pps (1'b0), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .otg_vbusoc (1'b0), + .rx_clk_in (rx_clk_in), + .rx_data_in (rx_data_in), + .rx_frame_in (rx_frame_in), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (dac_spi_sclk), + .spi1_csn_0_o (dac_spi_sync_n), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (dac_spi_sdi), + .tdd_sync_i (1'b0), + .tdd_sync_o (), + .tdd_sync_t (), + .tx_clk_out (tx_clk_out), + .tx_data_out (tx_data_out), + .tx_frame_out (tx_frame_out), + .txnrx (txnrx), + .up_enable (gpio_o[47]), + .up_txnrx (gpio_o[48])); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/nh7020/ccbob_lvds/Makefile b/projects/nh7020/ccbob_lvds/Makefile new file mode 100644 index 00000000000..30b8d4c26a4 --- /dev/null +++ b/projects/nh7020/ccbob_lvds/Makefile @@ -0,0 +1,27 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := adrv9364z7020_ccbob_lvds + +M_DEPS += ../common/ccbob_constr.xdc +M_DEPS += ../common/ccbob_bd.tcl +M_DEPS += ../common/adrv9364z7020_constr_lvds.xdc +M_DEPS += ../common/adrv9364z7020_constr.xdc +M_DEPS += ../common/adrv9364z7020_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ad5683_spi.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl + +LIB_DEPS += axi_ad9361 +LIB_DEPS += axi_dmac +LIB_DEPS += axi_gpreg +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 +LIB_DEPS += util_rfifo +LIB_DEPS += util_tdd_sync +LIB_DEPS += util_wfifo +LIB_DEPS += xilinx/util_clkdiv + +include ../../scripts/project-xilinx.mk diff --git a/projects/nh7020/ccbob_lvds/ad5683_spi.v b/projects/nh7020/ccbob_lvds/ad5683_spi.v new file mode 100644 index 00000000000..374dcbcd89e --- /dev/null +++ b/projects/nh7020/ccbob_lvds/ad5683_spi.v @@ -0,0 +1,71 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 23:56:52 11/10/2019 +// Design Name: +// Module Name: ad5683_spi +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// dat -> update triger -> update dac -> software LDAC -> wait +// +////////////////////////////////////////////////////////////////////////////////// +module ad5683_spi( + input clk, + input[15:0] dat, + output sclk, + output mosi, + output sync_n + ); + + reg[15:0] ldat = 16'd0; + wire upd = (dat!=ldat); + + reg[5:0] scnt = 6'b0; + reg[3:0] cclk = 4'b0; + wire sclk_full = cclk == 4'b1111; + wire sclk_half = cclk == 4'b1000; + + reg sync_n_o = 1'b1; + reg sclk_o = 1'b0; + + reg[23:0] shift = 24'd0; + wire[23:0] nxt_shift = scnt == 1'b0 ? {4'b0011,dat,4'b0} : {shift[22:0], 1'b0}; + + assign sync_n = sync_n_o; + assign mosi = shift[23]; + assign sclk = sclk_o; + + always@(posedge clk) + begin + if(upd) cclk <= cclk + 1'b1; + + if(sclk_half | sclk_full) sclk_o <= ~sclk_o; + end + + always@(posedge sclk_o) + begin + shift <= nxt_shift; + scnt <= scnt + 1'b1; + sync_n_o <= 1'b0; + + if(scnt == 6'b011000)begin + sync_n_o<=1'b1; + shift <= {4'b0001,20'b0}; + end else if(scnt == 6'b110001)begin + ldat <= dat; + scnt <= 1'b0; + sync_n_o <= 1'b1; + end + end + +endmodule diff --git a/projects/nh7020/ccbob_lvds/system_bd.tcl b/projects/nh7020/ccbob_lvds/system_bd.tcl new file mode 100644 index 00000000000..eae7e851a7a --- /dev/null +++ b/projects/nh7020/ccbob_lvds/system_bd.tcl @@ -0,0 +1,8 @@ + +source ../common/adrv9364z7020_bd.tcl +source ../common/ccbob_bd.tcl + +cfg_ad9361_interface LVDS + +set_property CONFIG.ADC_INIT_DELAY 30 [get_bd_cells axi_ad9361] + diff --git a/projects/nh7020/ccbob_lvds/system_project.tcl b/projects/nh7020/ccbob_lvds/system_project.tcl new file mode 100644 index 00000000000..fb7a504f385 --- /dev/null +++ b/projects/nh7020/ccbob_lvds/system_project.tcl @@ -0,0 +1,18 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z020clg400-1" +adi_project adrv9364z7020_ccbob_lvds +adi_project_files adrv9364z7020_ccbob_lvds [list \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "../common/adrv9364z7020_constr.xdc" \ + "../common/adrv9364z7020_constr_lvds.xdc" \ + "../common/ccbob_constr.xdc" \ + "ad5683_spi.v" \ + "system_top.v" ] + +adi_project_run adrv9364z7020_ccbob_lvds +source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl + diff --git a/projects/nh7020/ccbob_lvds/system_top.v b/projects/nh7020/ccbob_lvds/system_top.v new file mode 100644 index 00000000000..60266158c7c --- /dev/null +++ b/projects/nh7020/ccbob_lvds/system_top.v @@ -0,0 +1,243 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout iic_scl, + inout iic_sda, + + inout [10:0] gpio_bd, + + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, + + output enable, + output txnrx, + input clkout_in, + output clkout_out, + + inout gpio_clksel, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, + + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso, + + output [21:0] gp_out, + input [21:0] gp_in, + + output dac_spi_sdi, + output dac_spi_sclk, + output dac_spi_sync_n, + + input clk_40mhz +); + + + // internal signals + + wire [31:0] gp_out_s; + wire [31:0] gp_in_s; + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + wire clk_40_ibuf_s; + reg[15:0] clk_dac_val = 16'd32767; + // assignments + + assign clkout_out = clkout_in; + assign gp_out[21:10] = gp_out_s[21:10]; + assign gp_out[7:4] = gp_out_s[7:4]; + assign gp_in_s[31:28] = gp_out_s[31:28]; + assign gp_in_s[21: 0] = gp_in[21:0]; + + //CLK_40 + IBUFG clk_40_buf( + .I(clk_40mhz), + .O(clk_40_ibuf_s) + ); + + ad5683_spi ad5683_inst( + .clk(clk_40_ibuf_s), + .dat(clk_dac_val), + .sclk(dac_spi_sclk), + .mosi(dac_spi_sdi), + .sync_n(dac_spi_sync_n) + ); + // board gpio - 31-0 + + assign gpio_i[31:11] = gpio_o[31:11]; + + ad_iobuf #(.DATA_WIDTH(11)) i_iobuf_bd ( + .dio_t (gpio_t[10:0]), + .dio_i (gpio_o[10:0]), + .dio_o (gpio_i[10:0]), + .dio_p (gpio_bd)); + + // ad9361 gpio - 63-32 + + assign gpio_i[63:52] = gpio_o[63:52]; + assign gpio_i[50:47] = gpio_o[50:47]; + + ad_iobuf #(.DATA_WIDTH(16)) i_iobuf ( + .dio_t ({gpio_t[51], gpio_t[46:32]}), + .dio_i ({gpio_o[51], gpio_o[46:32]}), + .dio_o ({gpio_i[51], gpio_i[46:32]}), + .dio_p ({ gpio_clksel, // 51:51 + gpio_resetb, // 46:46 + gpio_sync, // 45:45 + gpio_en_agc, // 44:44 + gpio_ctl, // 43:40 + gpio_status})); // 39:32 + + // instantiations + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gp_in_0 (gp_in_s[31:0]), + .gp_out_0 (gp_out_s[31:0]), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .gps_pps (1'b0), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .otg_vbusoc (1'b0), + .rx_clk_in_n (rx_clk_in_n), + .rx_clk_in_p (rx_clk_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_frame_in_p (rx_frame_in_p), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + .spi1_clk_i (1'b0), + // .spi1_clk_o (dac_spi_sclk), + //.spi1_csn_0_o (dac_spi_sync_n), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + //.spi1_sdo_o (dac_spi_sdi), + .spi1_sdo_o (), + .tdd_sync_i (1'b0), + .tdd_sync_o (), + .tdd_sync_t (), + .tx_clk_out_n (tx_clk_out_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_frame_out_p (tx_frame_out_p), + .txnrx (txnrx), + .up_enable (gpio_o[47]), + .up_txnrx (gpio_o[48])); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/nh7020/common/adrv9364z7020_bd.tcl b/projects/nh7020/common/adrv9364z7020_bd.tcl new file mode 100644 index 00000000000..97c103e8bae --- /dev/null +++ b/projects/nh7020/common/adrv9364z7020_bd.tcl @@ -0,0 +1,480 @@ + +# create board design +# default ports + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main +create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io + +create_bd_port -dir O spi0_csn_2_o +create_bd_port -dir O spi0_csn_1_o +create_bd_port -dir O spi0_csn_0_o +create_bd_port -dir I spi0_csn_i +create_bd_port -dir I spi0_clk_i +create_bd_port -dir O spi0_clk_o +create_bd_port -dir I spi0_sdo_i +create_bd_port -dir O spi0_sdo_o +create_bd_port -dir I spi0_sdi_i + +create_bd_port -dir O spi1_csn_2_o +create_bd_port -dir O spi1_csn_1_o +create_bd_port -dir O spi1_csn_0_o +create_bd_port -dir I spi1_csn_i +create_bd_port -dir I spi1_clk_i +create_bd_port -dir O spi1_clk_o +create_bd_port -dir I spi1_sdo_i +create_bd_port -dir O spi1_sdo_o +create_bd_port -dir I spi1_sdi_i + +create_bd_port -dir I -from 63 -to 0 gpio_i +create_bd_port -dir O -from 63 -to 0 gpio_o +create_bd_port -dir O -from 63 -to 0 gpio_t + +# otg + +set otg_vbusoc [create_bd_port -dir I otg_vbusoc] + +# interrupts + +create_bd_port -dir I -type intr ps_intr_00 +create_bd_port -dir I -type intr ps_intr_01 +create_bd_port -dir I -type intr ps_intr_02 +create_bd_port -dir I -type intr ps_intr_03 +create_bd_port -dir I -type intr ps_intr_04 +create_bd_port -dir I -type intr ps_intr_05 +create_bd_port -dir I -type intr ps_intr_06 +create_bd_port -dir I -type intr ps_intr_07 +create_bd_port -dir I -type intr ps_intr_08 +create_bd_port -dir I -type intr ps_intr_09 +create_bd_port -dir I -type intr ps_intr_10 +create_bd_port -dir I -type intr ps_intr_11 +create_bd_port -dir I -type intr ps_intr_12 +create_bd_port -dir I -type intr ps_intr_13 +create_bd_port -dir I -type intr ps_intr_15 + +# instance: sys_ps7 + +ad_ip_instance processing_system7 sys_ps7 +ad_ip_parameter sys_ps7 CONFIG.PCW_PRESET_BANK0_VOLTAGE "LVCMOS 1.8V" +ad_ip_parameter sys_ps7 CONFIG.PCW_PRESET_BANK1_VOLTAGE "LVCMOS 1.8V" +ad_ip_parameter sys_ps7 CONFIG.PCW_PACKAGE_NAME fbg676 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_MIO_GPIO_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_ENET0_IO "MIO 16 .. 27" +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_IO "MIO 52 .. 53" +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET_RESET_SELECT "Separate reset pins" +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_RESET_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_RESET_IO "MIO 8" +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_RESET_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_RESET_IO "MIO 51" +ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_GRP_CD_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_GRP_CD_IO "MIO 50" +ad_ip_parameter sys_ps7 CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ 50 +ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_IO "MIO 7" +ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_PARTNO "MT41K256M16 RE-125" +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH "32 Bit" +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF 0 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 0.110 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 0.095 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 0.249 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 0.249 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 0.202 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 0.217 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 0.216 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 0.217 +ad_ip_parameter sys_ps7 CONFIG.PCW_TTC0_PERIPHERAL_ENABLE 0 +ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK1_PORT 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_EN_RST1_PORT 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK2_PORT 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_EN_RST2_PORT 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ 100.0 +ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 200.0 +ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ 200.0 +ad_ip_parameter sys_ps7 CONFIG.PCW_USE_FABRIC_INTERRUPT 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_INTR 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO 64 +ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_MODE REVERSE +ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_SPI0_IO EMIO +ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_SPI1_IO EMIO + +ad_ip_instance axi_iic axi_iic_main +ad_ip_parameter axi_iic_main CONFIG.USE_BOARD_FLOW true +ad_ip_parameter axi_iic_main CONFIG.IIC_BOARD_INTERFACE Custom + +ad_ip_instance xlconcat sys_concat_intc +ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 16 + +ad_ip_instance proc_sys_reset sys_rstgen +ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1 + +ad_ip_instance util_vector_logic sys_logic_inv +ad_ip_parameter sys_logic_inv CONFIG.C_SIZE 1 +ad_ip_parameter sys_logic_inv CONFIG.C_OPERATION not + +# system reset/clock definitions + +ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0 +ad_connect sys_200m_clk sys_ps7/FCLK_CLK1 +ad_connect sys_cpu_reset sys_rstgen/peripheral_reset +ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn +ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk +ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N + +# interface connections + +ad_connect ddr sys_ps7/DDR +ad_connect gpio_i sys_ps7/GPIO_I +ad_connect gpio_o sys_ps7/GPIO_O +ad_connect gpio_t sys_ps7/GPIO_T +ad_connect fixed_io sys_ps7/FIXED_IO +ad_connect iic_main axi_iic_main/iic +ad_connect sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT +ad_connect sys_logic_inv/Op1 otg_vbusoc + +# spi connections + +ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O +ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O +ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O +ad_connect spi0_csn_i sys_ps7/SPI0_SS_I +ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I +ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O +ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I +ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O +ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I + +ad_connect spi1_csn_2_o sys_ps7/SPI1_SS2_O +ad_connect spi1_csn_1_o sys_ps7/SPI1_SS1_O +ad_connect spi1_csn_0_o sys_ps7/SPI1_SS_O +ad_connect spi1_csn_i sys_ps7/SPI1_SS_I +ad_connect spi1_clk_i sys_ps7/SPI1_SCLK_I +ad_connect spi1_clk_o sys_ps7/SPI1_SCLK_O +ad_connect spi1_sdo_i sys_ps7/SPI1_MOSI_I +ad_connect spi1_sdo_o sys_ps7/SPI1_MOSI_O +ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I + +# interrupts + +ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P +ad_connect sys_concat_intc/In15 ps_intr_15 +ad_connect sys_concat_intc/In14 axi_iic_main/iic2intc_irpt +ad_connect sys_concat_intc/In13 ps_intr_13 +ad_connect sys_concat_intc/In12 ps_intr_12 +ad_connect sys_concat_intc/In11 ps_intr_11 +ad_connect sys_concat_intc/In10 ps_intr_10 +ad_connect sys_concat_intc/In9 ps_intr_09 +ad_connect sys_concat_intc/In8 ps_intr_08 +ad_connect sys_concat_intc/In7 ps_intr_07 +ad_connect sys_concat_intc/In6 ps_intr_06 +ad_connect sys_concat_intc/In5 ps_intr_05 +ad_connect sys_concat_intc/In4 ps_intr_04 +ad_connect sys_concat_intc/In3 ps_intr_03 +ad_connect sys_concat_intc/In2 ps_intr_02 +ad_connect sys_concat_intc/In1 ps_intr_01 +ad_connect sys_concat_intc/In0 ps_intr_00 + +# interconnects + +ad_cpu_interconnect 0x41600000 axi_iic_main + +# ad9361 + +create_bd_port -dir O enable +create_bd_port -dir O txnrx +create_bd_port -dir I up_enable +create_bd_port -dir I up_txnrx + +create_bd_port -dir O tdd_sync_o +create_bd_port -dir I tdd_sync_i +create_bd_port -dir O tdd_sync_t +create_bd_port -dir I gps_pps + +# ad9361 core + +ad_ip_instance axi_ad9361 axi_ad9361 +ad_ip_parameter axi_ad9361 CONFIG.ID 0 +ad_ip_parameter axi_ad9361 CONFIG.DAC_IODELAY_ENABLE 0 +ad_connect sys_200m_clk axi_ad9361/delay_clk +ad_connect axi_ad9361/l_clk axi_ad9361/clk +ad_connect enable axi_ad9361/enable +ad_connect txnrx axi_ad9361/txnrx +ad_connect up_enable axi_ad9361/up_enable +ad_connect up_txnrx axi_ad9361/up_txnrx + +# tdd-sync + +ad_ip_instance util_tdd_sync util_ad9361_tdd_sync +ad_ip_parameter util_ad9361_tdd_sync CONFIG.TDD_SYNC_PERIOD 10000000 +ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk +ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn +ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync +ad_connect util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr +ad_connect tdd_sync_t axi_ad9361/tdd_sync_cntr +ad_connect tdd_sync_o util_ad9361_tdd_sync/sync_out +ad_connect tdd_sync_i util_ad9361_tdd_sync/sync_in +ad_connect gps_pps axi_ad9361/gps_pps + +# interface clock divider to generate sampling clock +# interface runs at 4x in 2r2t mode, and 2x in 1r1t mode + +ad_ip_instance xlconcat util_ad9361_divclk_sel_concat +ad_ip_parameter util_ad9361_divclk_sel_concat CONFIG.NUM_PORTS 2 +ad_connect axi_ad9361/adc_r1_mode util_ad9361_divclk_sel_concat/In0 +ad_connect axi_ad9361/dac_r1_mode util_ad9361_divclk_sel_concat/In1 + +ad_ip_instance util_reduced_logic util_ad9361_divclk_sel +ad_ip_parameter util_ad9361_divclk_sel CONFIG.C_SIZE 2 +ad_connect util_ad9361_divclk_sel_concat/dout util_ad9361_divclk_sel/Op1 + +ad_ip_instance util_clkdiv util_ad9361_divclk +ad_connect util_ad9361_divclk_sel/Res util_ad9361_divclk/clk_sel +ad_connect axi_ad9361/l_clk util_ad9361_divclk/clk + +# resets at divided clock + +ad_ip_instance proc_sys_reset util_ad9361_divclk_reset +ad_connect sys_rstgen/peripheral_aresetn util_ad9361_divclk_reset/ext_reset_in +ad_connect util_ad9361_divclk/clk_out util_ad9361_divclk_reset/slowest_sync_clk + +# adc-path wfifo + +ad_ip_instance util_wfifo util_ad9361_adc_fifo +ad_ip_parameter util_ad9361_adc_fifo CONFIG.NUM_OF_CHANNELS 4 +ad_ip_parameter util_ad9361_adc_fifo CONFIG.DIN_ADDRESS_WIDTH 4 +ad_ip_parameter util_ad9361_adc_fifo CONFIG.DIN_DATA_WIDTH 16 +ad_ip_parameter util_ad9361_adc_fifo CONFIG.DOUT_DATA_WIDTH 16 +ad_connect axi_ad9361/l_clk util_ad9361_adc_fifo/din_clk +ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst +ad_connect util_ad9361_divclk/clk_out util_ad9361_adc_fifo/dout_clk +ad_connect util_ad9361_divclk_reset/peripheral_aresetn util_ad9361_adc_fifo/dout_rstn +ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0 +ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0 +ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0 +ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_fifo/din_enable_1 +ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_fifo/din_valid_1 +ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_fifo/din_data_1 +ad_connect axi_ad9361/adc_enable_i1 util_ad9361_adc_fifo/din_enable_2 +ad_connect axi_ad9361/adc_valid_i1 util_ad9361_adc_fifo/din_valid_2 +ad_connect axi_ad9361/adc_data_i1 util_ad9361_adc_fifo/din_data_2 +ad_connect axi_ad9361/adc_enable_q1 util_ad9361_adc_fifo/din_enable_3 +ad_connect axi_ad9361/adc_valid_q1 util_ad9361_adc_fifo/din_valid_3 +ad_connect axi_ad9361/adc_data_q1 util_ad9361_adc_fifo/din_data_3 +ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf + +# adc-path channel pack + +ad_ip_instance util_cpack2 util_ad9361_adc_pack { \ + NUM_OF_CHANNELS 4 \ + SAMPLE_DATA_WIDTH 16 \ +} + +ad_connect util_ad9361_divclk/clk_out util_ad9361_adc_pack/clk +ad_connect util_ad9361_divclk_reset/peripheral_reset util_ad9361_adc_pack/reset + +ad_connect util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/fifo_wr_en +ad_connect util_ad9361_adc_pack/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf + +for {set i 0} {$i < 4} {incr i} { + ad_connect util_ad9361_adc_fifo/dout_enable_${i} util_ad9361_adc_pack/enable_${i} + ad_connect util_ad9361_adc_fifo/dout_data_${i} util_ad9361_adc_pack/fifo_wr_data_${i} +} + +# adc-path dma + +ad_ip_instance axi_dmac axi_ad9361_adc_dma +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_TYPE_SRC 2 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.SYNC_TRANSFER_START 1 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_DEST 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_SRC 64 +ad_connect util_ad9361_divclk/clk_out axi_ad9361_adc_dma/fifo_wr_clk +ad_connect util_ad9361_adc_pack/packed_fifo_wr axi_ad9361_adc_dma/fifo_wr +ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn + +# dac-path rfifo + +ad_ip_instance util_rfifo axi_ad9361_dac_fifo +ad_ip_parameter axi_ad9361_dac_fifo CONFIG.DIN_DATA_WIDTH 16 +ad_ip_parameter axi_ad9361_dac_fifo CONFIG.DOUT_DATA_WIDTH 16 +ad_ip_parameter axi_ad9361_dac_fifo CONFIG.DIN_ADDRESS_WIDTH 4 +ad_connect axi_ad9361/l_clk axi_ad9361_dac_fifo/dout_clk +ad_connect axi_ad9361/rst axi_ad9361_dac_fifo/dout_rst +ad_connect util_ad9361_divclk/clk_out axi_ad9361_dac_fifo/din_clk +ad_connect util_ad9361_divclk_reset/peripheral_aresetn axi_ad9361_dac_fifo/din_rstn +ad_connect axi_ad9361_dac_fifo/dout_enable_0 axi_ad9361/dac_enable_i0 +ad_connect axi_ad9361_dac_fifo/dout_valid_0 axi_ad9361/dac_valid_i0 +ad_connect axi_ad9361_dac_fifo/dout_data_0 axi_ad9361/dac_data_i0 +ad_connect axi_ad9361_dac_fifo/dout_enable_1 axi_ad9361/dac_enable_q0 +ad_connect axi_ad9361_dac_fifo/dout_valid_1 axi_ad9361/dac_valid_q0 +ad_connect axi_ad9361_dac_fifo/dout_data_1 axi_ad9361/dac_data_q0 +ad_connect axi_ad9361_dac_fifo/dout_enable_2 axi_ad9361/dac_enable_i1 +ad_connect axi_ad9361_dac_fifo/dout_valid_2 axi_ad9361/dac_valid_i1 +ad_connect axi_ad9361_dac_fifo/dout_data_2 axi_ad9361/dac_data_i1 +ad_connect axi_ad9361_dac_fifo/dout_enable_3 axi_ad9361/dac_enable_q1 +ad_connect axi_ad9361_dac_fifo/dout_valid_3 axi_ad9361/dac_valid_q1 +ad_connect axi_ad9361_dac_fifo/dout_data_3 axi_ad9361/dac_data_q1 +ad_connect axi_ad9361_dac_fifo/dout_unf axi_ad9361/dac_dunf + +# dac-path channel unpack + +ad_ip_instance util_upack2 util_ad9361_dac_upack { \ + NUM_OF_CHANNELS 4 \ + SAMPLE_DATA_WIDTH 16 \ +} + +ad_connect util_ad9361_divclk/clk_out util_ad9361_dac_upack/clk +ad_connect util_ad9361_divclk_reset/peripheral_reset util_ad9361_dac_upack/reset + +ad_connect util_ad9361_dac_upack/fifo_rd_en axi_ad9361_dac_fifo/din_valid_0 +ad_connect util_ad9361_dac_upack/fifo_rd_underflow axi_ad9361_dac_fifo/din_unf + +for {set i 0} {$i < 4} {incr i} { + ad_connect util_ad9361_dac_upack/enable_$i axi_ad9361_dac_fifo/din_enable_$i + ad_connect util_ad9361_dac_upack/fifo_rd_valid axi_ad9361_dac_fifo/din_valid_in_$i + ad_connect util_ad9361_dac_upack/fifo_rd_data_$i axi_ad9361_dac_fifo/din_data_$i +} + +# dac-path dma + +ad_ip_instance axi_dmac axi_ad9361_dac_dma +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_SRC 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_DEST 1 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.CYCLIC 1 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_DEST 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 64 + +ad_connect util_ad9361_divclk/clk_out axi_ad9361_dac_dma/m_axis_aclk +ad_connect axi_ad9361_dac_dma/m_axis util_ad9361_dac_upack/s_axis + +ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn + +# interconnects + +ad_cpu_interconnect 0x79020000 axi_ad9361 +ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma +ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma +ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi +ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi + +# interrupts + +ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq +ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq +ad_cpu_interrupt ps-11 mb-11 axi_ad9361/gps_pps_irq + +## customization of core to disable data path logic (less resources) +## interface type - 1R1T (1) or 2R2T (0) (default is 2R2T) +## 2R2T supports 1R1T as a run time option. +## 1R1T allows core to run at a lower rate (1/2 of 2R2T) + +set_property CONFIG.MODE_1R1T 0 [get_bd_cells axi_ad9361] + +## interface type - CMOS (1) or LVDS (0) (default is LVDS) +## CMOS allows core to run at a lower rate (1/2 of LVDS) + +set_property CONFIG.CMOS_OR_LVDS_N 0 [get_bd_cells axi_ad9361] + +## data-path disable (global control)- allows removal of DSP functions within the core. +## also removes the corresponding AXI control interface registers + +set_property CONFIG.ADC_DATAPATH_DISABLE 0 [get_bd_cells axi_ad9361] +set_property CONFIG.DAC_DATAPATH_DISABLE 0 [get_bd_cells axi_ad9361] + +## data-path disable (individual control)- effective ONLY if DATAPATH_DISABLE is 0x0. + +set_property CONFIG.ADC_DATAFORMAT_DISABLE 0 [get_bd_cells axi_ad9361] +set_property CONFIG.ADC_DCFILTER_DISABLE 0 [get_bd_cells axi_ad9361] +set_property CONFIG.ADC_IQCORRECTION_DISABLE 0 [get_bd_cells axi_ad9361] +set_property CONFIG.ADC_USERPORTS_DISABLE 0 [get_bd_cells axi_ad9361] + +set_property CONFIG.DAC_DDS_DISABLE 0 [get_bd_cells axi_ad9361] +set_property CONFIG.DAC_IQCORRECTION_DISABLE 0 [get_bd_cells axi_ad9361] +set_property CONFIG.DAC_USERPORTS_DISABLE 0 [get_bd_cells axi_ad9361] + +## tdd-disable (control is moved exclusively to GPIO) + +set_property CONFIG.TDD_DISABLE 0 [get_bd_cells axi_ad9361] + +## lvds/cmos configuration +## core digital interface -- cmos (1) or lvds (0) + +proc cfg_ad9361_interface {cmos_or_lvds} { + + if {$cmos_or_lvds eq "LVDS"} { + + set_property CONFIG.CMOS_OR_LVDS_N 0 [get_bd_cells axi_ad9361] + + create_bd_port -dir I rx_clk_in_p + create_bd_port -dir I rx_clk_in_n + create_bd_port -dir I rx_frame_in_p + create_bd_port -dir I rx_frame_in_n + create_bd_port -dir I -from 5 -to 0 rx_data_in_p + create_bd_port -dir I -from 5 -to 0 rx_data_in_n + + create_bd_port -dir O tx_clk_out_p + create_bd_port -dir O tx_clk_out_n + create_bd_port -dir O tx_frame_out_p + create_bd_port -dir O tx_frame_out_n + create_bd_port -dir O -from 5 -to 0 tx_data_out_p + create_bd_port -dir O -from 5 -to 0 tx_data_out_n + + ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p + ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n + ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p + ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n + ad_connect rx_data_in_p axi_ad9361/rx_data_in_p + ad_connect rx_data_in_n axi_ad9361/rx_data_in_n + ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p + ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n + ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p + ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n + ad_connect tx_data_out_p axi_ad9361/tx_data_out_p + ad_connect tx_data_out_n axi_ad9361/tx_data_out_n + + return + } + + if {$cmos_or_lvds eq "CMOS"} { + + set_property CONFIG.CMOS_OR_LVDS_N 1 [get_bd_cells axi_ad9361] + + create_bd_port -dir I rx_clk_in + create_bd_port -dir I rx_frame_in + create_bd_port -dir I -from 11 -to 0 rx_data_in + create_bd_port -dir O tx_clk_out + create_bd_port -dir O tx_frame_out + create_bd_port -dir O -from 11 -to 0 tx_data_out + + ad_connect rx_clk_in axi_ad9361/rx_clk_in + ad_connect rx_frame_in axi_ad9361/rx_frame_in + ad_connect rx_data_in axi_ad9361/rx_data_in + ad_connect tx_clk_out axi_ad9361/tx_clk_out + ad_connect tx_frame_out axi_ad9361/tx_frame_out + ad_connect tx_data_out axi_ad9361/tx_data_out + + return + } + +} + + diff --git a/projects/nh7020/common/adrv9364z7020_constr.xdc b/projects/nh7020/common/adrv9364z7020_constr.xdc new file mode 100644 index 00000000000..f16c70ac4d8 --- /dev/null +++ b/projects/nh7020/common/adrv9364z7020_constr.xdc @@ -0,0 +1,196 @@ + +# constraints (pzsdr1.b) +# ad9361 + +set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS25} [get_ports enable] ; ## IO_L10P_T1_AD11P_35 U1,K19,IO_L10_35_ENABLE +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## IO_L11N_T1_SRCC_35 U1,L17,IO_L11_35_TXNRX + +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS25} [get_ports gpio_status[0]] ; ## IO_L19P_T3_35 U1,H15,IO_L19_35_CTRL_OUT0 +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS25} [get_ports gpio_status[1]] ; ## IO_L19N_T3_VREF_35 U1,G15,IO_L19_35_CTRL_OUT1 +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports gpio_status[2]] ; ## IO_L20P_T3_AD6P_35 U1,K14,IO_L20_35_CTRL_OUT2 +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS25} [get_ports gpio_status[3]] ; ## IO_L20N_T3_AD6N_35 U1,J14,IO_L20_35_CTRL_OUT3 +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS25} [get_ports gpio_status[4]] ; ## IO_L21P_T3_DQS_AD14P_35 U1,N15,IO_L21_35_CTRL_OUT4 +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports gpio_status[5]] ; ## IO_L21N_T3_DQS_AD14N_35 U1,N16,IO_L21_35_CTRL_OUT5 +set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports gpio_status[6]] ; ## IO_L22P_T3_AD7P_35 U1,L14,IO_L22_35_CTRL_OUT6 +set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports gpio_status[7]] ; ## IO_L22N_T3_AD7N_35 U1,L15,IO_L22_35_CTRL_OUT7 +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[0]] ; ## IO_L23P_T3_34 U1,N17,IO_L23_34_CTRL_IN0 +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[1]] ; ## IO_L23N_T3_34 U1,P18,IO_L23_34_CTRL_IN1 +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[2]] ; ## IO_L24P_T3_34 U1,P15,IO_L24_34_CTRL_IN2 +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[3]] ; ## IO_L24N_T3_34 U1,P16,IO_L24_34_CTRL_IN3 +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## IO_L11P_T1_SRCC_35 U1,L16,IO_L11_35_EN_AGC +set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## IO_L10N_T1_AD11N_35 U1,J19,IO_L10_35_SYNC_IN +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## IO_0_35 U1,G14,IO_00_35_AD9364_RST +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports gpio_clksel] ; ## IO_0_34 U1,R19,IO_00_34_AD9364_CLKSEL + +set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## IO_L23P_T3_35 U1,M14,IO_L23_35_SPI_ENB +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## IO_L23N_T3_35 U1,M15,IO_L23_35_SPI_CLK +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## IO_L24P_T3_AD15P_35 U1,K16,IO_L24_35_SPI_DI +set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## IO_L24N_T3_AD15N_35 U1,J16,IO_L24_35_SPI_DO + +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS25} [get_ports clkout_in] ; ## IO_25_35 U1,J15,IO_25_35_AD9364_CLKOUT + +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports clk_40mhz] ; ## IO_L14P_T2_SRCC_34 + +# iic + +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_scl] ; ## IO_L22N_T3_13 U1,W6,SCL,JX2,17,I2C_SCL +set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_sda] ; ## IO_L22P_T3_13 U1,V6,SDA,JX2,19,I2C_SDA + +#dac + +set_property -dict {PACKAGE_PIN U8 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports dac_spi_sdi] ; ## IO_L16P_T2_13 +set_property -dict {PACKAGE_PIN W10 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports dac_spi_sclk] ; ## IO_L17N_T2_13 +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports dac_spi_sync_n] ; ## IO_L17P_T2_13 + +## reference-only +## -------------- +## ad9361 (optional rf-card) +## -------------------------- +## JX4,1,GPO0 +## JX4,2,GPO1 +## JX4,3,GPO2 +## JX4,4,GPO3 +## JX4,7,AUXADC +## JX4,8,AUXDAC1 +## JX4,10,AUXDAC2 +## JX4,63,AD9364_CLK + +## fixed-io (ps7) (som only, others are carrier specific) +## ------------------------------------------------------ +## U1,A7,PS_MIO01_500_QSPI0_SS_B +## U1,A5,PS_MIO06_500_QSPI0_SCLK +## U1,B8,PS_MIO02_500_QSPI0_IO0 +## U1,D6,PS_MIO03_500_QSPI0_IO1 +## U1,B7,PS_MIO04_500_QSPI0_IO2 +## U1,A6,PS_MIO05_500_QSPI0_IO3 +## U1,D5,PS_MIO08_500_ETH0_RESETN (magnetics-RJ45- JX3,47,ETH_PHY_LED0) +## U1,C11,PS_MIO53_501_ETH0_MDIO (magnetics-RJ45- JX3,48,ETH_PHY_LED1) +## U1,C10,PS_MIO52_501_ETH0_MDC (magnetics-RJ45- JX3,51,ETH_MD1_P) +## U1,B17,PS_MIO22_501_ETH0_RX_CLK (magnetics-RJ45- JX3,53,ETH_MD1_N) +## U1,D13,PS_MIO27_501_ETH0_RX_CTL (magnetics-RJ45- JX3,52,ETH_MD2_P) +## U1,D11,PS_MIO23_501_ETH0_RX_D0 (magnetics-RJ45- JX3,54,ETH_MD2_N) +## U1,A16,PS_MIO24_501_ETH0_RX_D1 (magnetics-RJ45- JX3,57,ETH_MD3_P) +## U1,F15,PS_MIO25_501_ETH0_RX_D2 (magnetics-RJ45- JX3,59,ETH_MD3_P) +## U1,A15,PS_MIO26_501_ETH0_RX_D3 (magnetics-RJ45- JX3,58,ETH_MD4_P) +## U1,A19,PS_MIO16_501_ETH0_TX_CLK (magnetics-RJ45- JX3,60,ETH_MD4_P) +## U1,F14,PS_MIO21_501_ETH0_TX_CTL +## U1,E14,PS_MIO17_501_ETH0_TX_D0 +## U1,B18,PS_MIO18_501_ETH0_TX_D1 +## U1,D10,PS_MIO19_501_ETH0_TX_D2 +## U1,A17,PS_MIO20_501_ETH0_TX_D3 +## U1,B12,PS_MIO48_501_JX4,JX4,99,USB_UART_RXD +## U1,C12,PS_MIO49_501_JX4,JX4,98,USB_UART_TXD +## U1,D14,PS_MIO40_501_SD0_CLK (off-board- JX3,43,SDIO_CLKB1) +## U1,C17,PS_MIO41_501_SD0_CMD (off-board- JX3,34,SDIO_CMDB1) +## U1,E12,PS_MIO42_501_SD0_DATA0 (off-board- JX3,37,SDIO_DAT0B1) +## U1,A9,PS_MIO43_501_SD0_DATA1 (off-board- JX3,36,SDIO_DAT1B1) +## U1,F13,PS_MIO44_501_SD0_DATA2 (off-board- JX3,39,SDIO_DAT2B1) +## U1,B15,PS_MIO45_501_SD0_DATA3 (off-board- JX3,38,SDIO_DAT3B1) +## U1,B13,PS_MIO50_501_SD0_CD (off-board- JX3,41,JX3_SD1_CDN) +## U1,D8,PS_MIO07_500_USB_RESET_B (usb- JX3,63,USB_ID) +## U1,B5,PS_MIO09_500_USB_CLK_PD (usb- JX3,67,USB_OTG_P) +## U1,C13,PS_MIO29_501_USB0_DIR (usb- JX3,69,USB_OTG_N) +## U1,C15,PS_MIO30_501_USB0_STP (usb- JX3,68,USB_VBUS_OTG) +## U1,E16,PS_MIO31_501_USB0_NXT (usb- JX3,70,USB_OTG_CPEN) +## U1,A11,PS_MIO36_501_USB0_CLK +## U1,A14,PS_MIO32_501_USB0_D0 +## U1,D15,PS_MIO33_501_USB0_D1 +## U1,A12,PS_MIO34_501_USB0_D2 +## U1,F12,PS_MIO35_501_USB0_D3 +## U1,C16,PS_MIO28_501_USB0_D4 +## U1,A10,PS_MIO37_501_USB0_D5 +## U1,E13,PS_MIO38_501_USB0_D6 +## U1,C18,PS_MIO39_501_USB0_D7 + +## ddr (fixed-io) +## -------------- +## U1,C2,DDR3_DQS0_P +## U1,B2,DDR3_DQS0_N +## U1,G2,DDR3_DQS1_P +## U1,F2,DDR3_DQS1_N +## U1,R2,DDR3_DQS2_P +## U1,T2,DDR3_DQS2_N +## U1,W5,DDR3_DQS3_P +## U1,W4,DDR3_DQS3_N +## U1,C3,DDR3_DQ0 +## U1,B3,DDR3_DQ1 +## U1,A2,DDR3_DQ2 +## U1,A4,DDR3_DQ3 +## U1,D3,DDR3_DQ4 +## U1,D1,DDR3_DQ5 +## U1,C1,DDR3_DQ6 +## U1,E1,DDR3_DQ7 +## U1,E2,DDR3_DQ8 +## U1,E3,DDR3_DQ9 +## U1,G3,DDR3_DQ10 +## U1,H3,DDR3_DQ11 +## U1,J3,DDR3_DQ12 +## U1,H2,DDR3_DQ13 +## U1,H1,DDR3_DQ14 +## U1,J1,DDR3_DQ15 +## U1,P1,DDR3_DQ16 +## U1,P3,DDR3_DQ17 +## U1,R3,DDR3_DQ18 +## U1,R1,DDR3_DQ19 +## U1,T4,DDR3_DQ20 +## U1,U4,DDR3_DQ21 +## U1,U2,DDR3_DQ22 +## U1,U3,DDR3_DQ23 +## U1,V1,DDR3_DQ24 +## U1,Y3,DDR3_DQ25 +## U1,W1,DDR3_DQ26 +## U1,Y4,DDR3_DQ27 +## U1,Y2,DDR3_DQ28 +## U1,W3,DDR3_DQ29 +## U1,V2,DDR3_DQ30 +## U1,V3,DDR3_DQ31 +## U1,A1,DDR3_DM0 +## U1,F1,DDR3_DM1 +## U1,T1,DDR3_DM2 +## U1,Y1,DDR3_DM3 +## U1,N2,DDR3_A0 +## U1,K2,DDR3_A1 +## U1,M3,DDR3_A2 +## U1,K3,DDR3_A3 +## U1,M4,DDR3_A4 +## U1,L1,DDR3_A5 +## U1,L4,DDR3_A6 +## U1,K4,DDR3_A7 +## U1,K1,DDR3_A8 +## U1,J4,DDR3_A9 +## U1,F5,DDR3_A10 +## U1,G4,DDR3_A11 +## U1,E4,DDR3_A12 +## U1,D4,DDR3_A13 +## U1,F4,DDR3_A14 +## U1,L5,DDR3_BA0 +## U1,R4,DDR3_BA1 +## U1,J5,DDR3_BA2 +## U1,L2,DDR3_CK_P +## U1,M2,DDR3_CK_N +## U1,N3,DDR3_CKE +## U1,B4,DDR3_RST# +## U1,N1,DDR3_CS# +## U1,M5,DDR3_WE# +## U1,P4,DDR3_RAS# +## U1,P5,DDR3_CAS# +## U1,N5,DDR3_ODT + +## resets, clock and power controls +## -------------------------------- +## U1,E7,UNNAMED_3_ICXC7Z20_I217_PSCLK50,33.33MEGHZ +## U1,B10,PS-SRST# +## U1,C7,PWR_GD_1.35V +## JX2,10,PG_1P8V +## JX2,11,PG_MODULE +## JX1,5,PWR_ENABLE +## JX1,6,CARRIER_RESET + +## JTAG +## ---- +## U1,J6,JTAG_TMS,JX1,2,JTAG_TMS +## U1,F9,JTAG_TCK,JX1,1,JTAG_TCK +## U1,F6,JTAG_TDO,JX1,3,JTAG_TDO +## U1,G6,JTAG_TDI,JX1,4,JTAG_TDI +## U1,R11,FPGA_DONE,JX1,8,CFG_DONE + diff --git a/projects/nh7020/common/adrv9364z7020_constr_cmos.xdc b/projects/nh7020/common/adrv9364z7020_constr_cmos.xdc new file mode 100644 index 00000000000..ac72fc59e75 --- /dev/null +++ b/projects/nh7020/common/adrv9364z7020_constr_cmos.xdc @@ -0,0 +1,41 @@ + +# constraints (pzsdr1.b) +# ad9361 (SWAP == 0x0) + +set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS25} [get_ports rx_clk_in] ; ## IO_L12P_T1_MRCC_35 U1,K17,IO_L12_MRCC_35_DATA_CLK_P +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports rx_frame_in] ; ## IO_L7P_T1_AD2P_35 U1,M19,IO_L07_35_RX_FRAME_P +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS25} [get_ports rx_data_in[0]] ; ## IO_L13N_T2_MRCC_35 U1,H17,IO_L13_35_TX_D0_N +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS25} [get_ports rx_data_in[1]] ; ## IO_L13P_T2_MRCC_35 U1,H16,IO_L13_35_TX_D0_P +set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS25} [get_ports rx_data_in[2]] ; ## IO_L14N_T2_AD4N_SRCC_35 U1,H18,IO_L14_35_TX_D1_N +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports rx_data_in[3]] ; ## IO_L14P_T2_AD4P_SRCC_35 U1,J18,IO_L14_35_TX_D1_P +set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVCMOS25} [get_ports rx_data_in[4]] ; ## IO_L15N_T2_DQS_AD12N_35 U1,F20,IO_L15_35_TX_D2_N +set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports rx_data_in[5]] ; ## IO_L15P_T2_DQS_AD12P_35 U1,F19,IO_L15_35_TX_D2_P +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS25} [get_ports rx_data_in[6]] ; ## IO_L16N_T2_35 U1,G18,IO_L16_35_TX_D3_N +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS25} [get_ports rx_data_in[7]] ; ## IO_L16P_T2_35 U1,G17,IO_L16_35_TX_D3_P +set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS25} [get_ports rx_data_in[8]] ; ## IO_L17N_T2_AD5N_35 U1,H20,IO_L17_35_TX_D4_N +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports rx_data_in[9]] ; ## IO_L17P_T2_AD5P_35 U1,J20,IO_L17_35_TX_D4_P +set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports rx_data_in[10]] ; ## IO_L18N_T2_AD13N_35 U1,G20,IO_L18_35_TX_D5_N +set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS25} [get_ports rx_data_in[11]] ; ## IO_L18P_T2_AD13P_35 U1,G19,IO_L18_35_TX_D5_P + +set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS25} [get_ports tx_clk_out] ; ## IO_L8P_T1_AD10P_35 U1,M17,IO_L08_35_FB_CLK_P +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports tx_frame_out] ; ## IO_L9P_T1_DQS_AD3P_35 U1,L19,IO_L09_35_TX_FRAME_P +set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS25} [get_ports tx_data_out[0]] ; ## IO_L1N_T0_AD0N_35 U1,B20,IO_L01_35_RX_D0_N +set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS25} [get_ports tx_data_out[1]] ; ## IO_L1P_T0_AD0P_35 U1,C20,IO_L01_35_RX_D0_P +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports tx_data_out[2]] ; ## IO_L2N_T0_AD8N_35 U1,A20,IO_L02_35_RX_D1_N +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports tx_data_out[3]] ; ## IO_L2P_T0_AD8P_35 U1,B19,IO_L02_35_RX_D1_P +set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports tx_data_out[4]] ; ## IO_L3N_T0_DQS_AD1N_35 U1,D18,IO_L03_35_RX_D2_N +set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS25} [get_ports tx_data_out[5]] ; ## IO_L3P_T0_DQS_AD1P_35 U1,E17,IO_L03_35_RX_D2_P +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS25} [get_ports tx_data_out[6]] ; ## IO_L4N_T0_35 U1,D20,IO_L04_35_RX_D3_N +set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS25} [get_ports tx_data_out[7]] ; ## IO_L4P_T0_35 U1,D19,IO_L04_35_RX_D3_P +set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS25} [get_ports tx_data_out[8]] ; ## IO_L5N_T0_AD9N_35 U1,E19,IO_L05_35_RX_D4_N +set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports tx_data_out[9]] ; ## IO_L5P_T0_AD9P_35 U1,E18,IO_L05_35_RX_D4_P +set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports tx_data_out[10]] ; ## IO_L6N_T0_VREF_35 U1,F17,IO_L06_35_RX_D5_N +set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS25} [get_ports tx_data_out[11]] ; ## IO_L6P_T0_35 U1,F16,IO_L06_35_RX_D5_P + +set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS25} [get_ports tx_gnd[0]] ; ## IO_L8N_T1_AD10N_35 U1,M18,IO_L08_35_FB_CLK_N +set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS25} [get_ports tx_gnd[1]] ; ## IO_L9N_T1_DQS_AD3N_35 U1,L20,IO_L09_35_TX_FRAME_N + +# clocks + +create_clock -name rx_clk -period 8 [get_ports rx_clk_in] + diff --git a/projects/nh7020/common/adrv9364z7020_constr_lvds.xdc b/projects/nh7020/common/adrv9364z7020_constr_lvds.xdc new file mode 100644 index 00000000000..958d6a6ad38 --- /dev/null +++ b/projects/nh7020/common/adrv9364z7020_constr_lvds.xdc @@ -0,0 +1,41 @@ + +# constraints (pzsdr1.b) +# ad9361 + +set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## IO_L12P_T1_MRCC_35 U1,K17,IO_L12_MRCC_35_DATA_CLK_P +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## IO_L12N_T1_MRCC_35 U1,K18,IO_L12_MRCC_35_DATA_CLK_N +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## IO_L7P_T1_AD2P_35 U1,M19,IO_L07_35_RX_FRAME_P +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## IO_L7N_T1_AD2N_35 U1,M20,IO_L07_35_RX_FRAME_N +set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## IO_L1P_T0_AD0P_35 U1,C20,IO_L01_35_RX_D0_P +set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## IO_L1N_T0_AD0N_35 U1,B20,IO_L01_35_RX_D0_N +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## IO_L2P_T0_AD8P_35 U1,B19,IO_L02_35_RX_D1_P +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## IO_L2N_T0_AD8N_35 U1,A20,IO_L02_35_RX_D1_N +set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## IO_L3P_T0_DQS_AD1P_35 U1,E17,IO_L03_35_RX_D2_P +set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## IO_L3N_T0_DQS_AD1N_35 U1,D18,IO_L03_35_RX_D2_N +set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## IO_L4P_T0_35 U1,D19,IO_L04_35_RX_D3_P +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## IO_L4N_T0_35 U1,D20,IO_L04_35_RX_D3_N +set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## IO_L5P_T0_AD9P_35 U1,E18,IO_L05_35_RX_D4_P +set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## IO_L5N_T0_AD9N_35 U1,E19,IO_L05_35_RX_D4_N +set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## IO_L6P_T0_35 U1,F16,IO_L06_35_RX_D5_P +set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## IO_L6N_T0_VREF_35 U1,F17,IO_L06_35_RX_D5_N +set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25} [get_ports tx_clk_out_p] ; ## IO_L8P_T1_AD10P_35 U1,M17,IO_L08_35_FB_CLK_P +set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVDS_25} [get_ports tx_clk_out_n] ; ## IO_L8N_T1_AD10N_35 U1,M18,IO_L08_35_FB_CLK_N +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25} [get_ports tx_frame_out_p] ; ## IO_L9P_T1_DQS_AD3P_35 U1,L19,IO_L09_35_TX_FRAME_P +set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVDS_25} [get_ports tx_frame_out_n] ; ## IO_L9N_T1_DQS_AD3N_35 U1,L20,IO_L09_35_TX_FRAME_N +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[0]] ; ## IO_L13P_T2_MRCC_35 U1,H16,IO_L13_35_TX_D0_P +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[0]] ; ## IO_L13N_T2_MRCC_35 U1,H17,IO_L13_35_TX_D0_N +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[1]] ; ## IO_L14P_T2_AD4P_SRCC_35 U1,J18,IO_L14_35_TX_D1_P +set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[1]] ; ## IO_L14N_T2_AD4N_SRCC_35 U1,H18,IO_L14_35_TX_D1_N +set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[2]] ; ## IO_L15P_T2_DQS_AD12P_35 U1,F19,IO_L15_35_TX_D2_P +set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[2]] ; ## IO_L15N_T2_DQS_AD12N_35 U1,F20,IO_L15_35_TX_D2_N +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[3]] ; ## IO_L16P_T2_35 U1,G17,IO_L16_35_TX_D3_P +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[3]] ; ## IO_L16N_T2_35 U1,G18,IO_L16_35_TX_D3_N +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[4]] ; ## IO_L17P_T2_AD5P_35 U1,J20,IO_L17_35_TX_D4_P +set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[4]] ; ## IO_L17N_T2_AD5N_35 U1,H20,IO_L17_35_TX_D4_N +set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[5]] ; ## IO_L18P_T2_AD13P_35 U1,G19,IO_L18_35_TX_D5_P +set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## IO_L18N_T2_AD13N_35 U1,G20,IO_L18_35_TX_D5_N + +# clocks + +create_clock -name rx_clk -period 8 [get_ports rx_clk_in_p] + diff --git a/projects/nh7020/common/ccbob_bd.tcl b/projects/nh7020/common/ccbob_bd.tcl new file mode 100644 index 00000000000..16086371fe9 --- /dev/null +++ b/projects/nh7020/common/ccbob_bd.tcl @@ -0,0 +1,19 @@ + +# lbfmc + +ad_connect sys_ps7/ENET1_GMII_RX_CLK GND +ad_connect sys_ps7/ENET1_GMII_TX_CLK GND + +# un-used io (regular) + +ad_ip_instance axi_gpreg axi_gpreg +ad_ip_parameter axi_gpreg CONFIG.NUM_OF_CLK_MONS 0 +ad_ip_parameter axi_gpreg CONFIG.NUM_OF_IO 1 + +create_bd_port -dir I -from 31 -to 0 gp_in_0 +create_bd_port -dir O -from 31 -to 0 gp_out_0 + +ad_connect gp_in_0 axi_gpreg/up_gp_in_0 +ad_connect gp_out_0 axi_gpreg/up_gp_out_0 +ad_cpu_interconnect 0x41200000 axi_gpreg + diff --git a/projects/nh7020/common/ccbob_constr.xdc b/projects/nh7020/common/ccbob_constr.xdc new file mode 100644 index 00000000000..f8ced254873 --- /dev/null +++ b/projects/nh7020/common/ccbob_constr.xdc @@ -0,0 +1,82 @@ + +## constraints (ccbrk.c + ccbrk_lb.a) +## ad9361 clkout forward + +set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS25} [get_ports clkout_out] ; ## (lb: none) U1,W16,IO_L18_34_JX4_N,JX4,70,IO_L18_34_JX4_N,P7,32 + +## push-buttons- led- dip-switches- loopbacks- (ps7 gpio) + +set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]] ; ## (lb: none) U1,Y14,IO_L08_34_JX4_N,JX4,38,PB_GPIO_1,P6,19 +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]] ; ## (lb: none) U1,T16,IO_L09_34_JX4_P,JX4,41,PB_GPIO_2,P6,26 +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]] ; ## (lb: none) U1,U17,IO_L09_34_JX4_N,JX4,43,PB_GPIO_3,P6,28 +set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]] ; ## (lb: none) U1,Y19,IO_L17_34_JX4_N,JX4,69,LED_GPIO_0,P7,16 + +## orphans- io- (ps7 gpio) + +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports gpio_bd[4]] ; ## (lb: none) U1,V5,IO_L06_13_JX2_P,JX2,18,IO_L06_13_JX2_P +set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports gpio_bd[5]] ; ## (lb: none) U1,V11,IO_L21_13_JX2_P,JX2,67,IO_L21_13_JX2_P,P2,52 +set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports gpio_bd[6]] ; ## (lb: none) U1,V10,IO_L21_13_JX2_N,JX2,69,IO_L21_13_JX2_N,P2,54 +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]] ; ## (lb: none) U1,V16,IO_L18_34_JX4_P,JX4,68,IO_L18_34_JX4_P,P7,30 + +## ps7- fixed io- to- fpga regular io (ps7 gpio) + +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[8]] ; ## U1,V15,IO_L10_34_JX4_P,JX4,42,IO_L10_34_JX4_P,P6,25 (U1,E9,PS_MIO10_500_JX4,JX4,87,PS_MIO10_500_JX4,P6,23) +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]] ; ## U1,Y18,IO_L17_34_JX4_P,JX4,67,IO_L17_34_JX4_P,P6,9 (U1,B9,PS_MIO51_501_JX4,JX4,100,PS_MIO51_501_JX4,P6,11) +set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[10]] ; ## U1,Y17,IO_L07_34_JX4_N,JX4,37,IO_L07_34_JX4_N,P6,20 (U1,C8,PS_MIO15_500_JX4,JX4,85,PS_MIO15_500_JX4,P6,21) + +## ps7- fixed io- to- ps7- fixed io (reference only) +## U1,B14,PS_MIO47_501_JX4,JX4,94,PS_MIO47_501_JX4,P7,24 == U1,D16,PS_MIO46_501_JX4,JX4,92,PS_MIO46_501_JX4,P7,22 + +## ps7- fixed io- orphans (reference only) +## U1,E6,PS_MIO00_500_JX4,JX4,97,PS_MIO00_500_JX4,P5,21 +## U1,E8,PS_MIO13_500_JX4,JX4,91,PS_MIO13_500_JX4,P5,9 +## U1,C5,PS_MIO14_500_JX4,JX4,93,PS_MIO14_500_JX4,P5,11 +## U1,D9,PS_MIO12_500_JX4,JX4,86,PS_MIO12_500_JX4,P7,10 +## U1,C6,PS_MIO11_500_JX4,JX4,88,PS_MIO11_500_JX4,P7,12 + +## fpga- regular io + +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports gp_out[0]] ; ## U1,U7,IO_L11_SRCC_13_JX2_P,JX2,35,IO_L11_SRCC_13_JX2_P,P2,28 +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports gp_in[0]] ; ## U1,T9,IO_L12_MRCC_13_JX2_P,JX2,36,IO_L12_MRCC_13_JX2_P,P2,27 +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports gp_out[1]] ; ## U1,V7,IO_L11_SRCC_13_JX2_N,JX2,37,IO_L11_SRCC_13_JX2_N,P2,30 +set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS33} [get_ports gp_in[1]] ; ## U1,U10,IO_L12_MRCC_13_JX2_N,JX2,38,IO_L12_MRCC_13_JX2_N,P2,29 +set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS33} [get_ports gp_out[2]] ; ## U1,Y7,IO_L13_MRCC_13_JX2_P,JX2,41,IO_L13_MRCC_13_JX2_P,P2,32 +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports gp_in[2]] ; ## U1,Y9,IO_L14_SRCC_13_JX2_P,JX2,42,IO_L14_SRCC_13_JX2_P,P2,31 +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports gp_out[3]] ; ## U1,Y6,IO_L13_MRCC_13_JX2_N,JX2,43,IO_L13_MRCC_13_JX2_N,P2,34 +set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports gp_in[3]] ; ## U1,Y8,IO_L14_SRCC_13_JX2_N,JX2,44,IO_L14_SRCC_13_JX2_N,P2,33 +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS33} [get_ports gp_out[4]] ; ## U1,V8,IO_L15_13_JX2_P,JX2,47,IO_L15_13_JX2_P,P2,38 +set_property -dict {PACKAGE_PIN W8 IOSTANDARD LVCMOS33} [get_ports gp_in[4]] ; ## U1,W8,IO_L15_13_JX2_N,JX2,49,IO_L15_13_JX2_N,P2,40 +set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVCMOS33} [get_ports gp_out[5]] ; ## U1,W9,IO_L16_13_JX2_N,JX2,50,IO_L16_13_JX2_N,P2,39 +set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS33} [get_ports gp_in[5]] ; ## U1,W11,IO_L18_13_JX2_P,JX2,54,IO_L18_13_JX2_P,P2,41 +set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports gp_out[6]] ; ## U1,Y11,IO_L18_13_JX2_N,JX2,56,IO_L18_13_JX2_N,P2,43 +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports gp_in[6]] ; ## U1,T5,IO_L19_13_JX2_P,JX2,61,IO_L19_13_JX2_P,P2,46 +set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS33} [get_ports gp_out[7]] ; ## U1,Y12,IO_L20_13_JX2_P,JX2,62,IO_L20_13_JX2_P,P2,45 +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports gp_in[7]] ; ## U1,U5,IO_L19_13_JX2_N,JX2,63,IO_L19_13_JX2_N,P2,48 +set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS33} [get_ports gp_out[8]] ; ## U1,Y13,IO_L20_13_JX2_N,JX2,64,IO_L20_13_JX2_N,P2,47 +set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS25} [get_ports gp_in[8]] ; ## U1,W15,IO_L10_34_JX4_N,JX4,44,IO_L10_34_JX4_N,P6,27 +set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports gp_out[9]] ; ## U1,T19,IO_25_34_JX4,JX4,64,IO_25_34_JX4,P5,23 +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS25} [get_ports gp_in[9]] ; ## U1,T11,IO_L01_34_JX4_P,JX4,19,IO_L01_34_JX4_P,P6,2 +set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS25} [get_ports gp_out[10]] ; ## U1,T12,IO_L02_34_JX4_P,JX4,20,IO_L02_34_JX4_P,P6,1 +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS25} [get_ports gp_in[10]] ; ## U1,T10,IO_L01_34_JX4_N,JX4,21,IO_L01_34_JX4_N,P6,4 +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS25} [get_ports gp_out[11]] ; ## U1,U12,IO_L02_34_JX4_N,JX4,22,IO_L02_34_JX4_N,P6,3 +set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS25} [get_ports gp_in[11]] ; ## U1,U13,IO_L03_34_JX4_P,JX4,25,IO_L03_34_JX4_P,P6,6 +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS25} [get_ports gp_out[12]] ; ## U1,V12,IO_L04_34_JX4_P,JX4,26,IO_L04_34_JX4_P,P6,5 +set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS25} [get_ports gp_in[12]] ; ## U1,V13,IO_L03_34_JX4_N,JX4,27,IO_L03_34_JX4_N,P6,8 +set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS25} [get_ports gp_out[13]] ; ## U1,W13,IO_L04_34_JX4_N,JX4,28,IO_L04_34_JX4_N,P6,7 +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS25} [get_ports gp_in[13]] ; ## U1,T14,IO_L05_34_JX4_P,JX4,31,IO_L05_34_JX4_P,P6,14 +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS25} [get_ports gp_out[14]] ; ## U1,P14,IO_L06_34_JX4_P,JX4,32,IO_L06_34_JX4_P,P6,13 +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS25} [get_ports gp_in[14]] ; ## U1,T15,IO_L05_34_JX4_N,JX4,33,IO_L05_34_JX4_N,P6,16 +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS25} [get_ports gp_out[15]] ; ## U1,R14,IO_L06_34_JX4_N,JX4,34,IO_L06_34_JX4_N,P6,15 +set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS25} [get_ports gp_in[15]] ; ## U1,Y16,IO_L07_34_JX4_P,JX4,35,IO_L07_34_JX4_P,P6,18 +set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS25} [get_ports gp_out[16]] ; ## U1,W14,IO_L08_34_JX4_P,JX4,36,IO_L08_34_JX4_P,P6,17 +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS25} [get_ports gp_in[16]] ; ## U1,U14,IO_L11_SRCC_34_JX4_P,JX4,45,IO_L11_SRCC_34_JX4_P,P6,30 +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS25} [get_ports gp_out[17]] ; ## U1,U18,IO_L12_MRCC_34_JX4_P,JX4,46,IO_L12_MRCC_34_JX4_P,P6,29 +set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS25} [get_ports gp_in[17]] ; ## U1,U15,IO_L11_SRCC_34_JX4_N,JX4,47,IO_L11_SRCC_34_JX4_N,P6,32 +set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS25} [get_ports gp_out[18]] ; ## U1,U19,IO_L12_MRCC_34_JX4_N,JX4,48,IO_L12_MRCC_34_JX4_N,P6,31 +set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports gp_in[18]] ; ## U1,N18,IO_L13_MRCC_34_JX4_P,JX4,51,IO_L13_MRCC_34_JX4_P,P7,2 +set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS25} [get_ports gp_out[19]] ; ## U1,P19,IO_L13_MRCC_34_JX4_N,JX4,53,IO_L13_MRCC_34_JX4_N,P7,4 +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports gp_in[19]] ; ## U1,P20,IO_L14_SRCC_34_JX4_N,JX4,54,IO_L14_SRCC_34_JX4_N,P7,3 +set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS25} [get_ports gp_out[20]] ; ## U1,T20,IO_L15_34_JX4_P,JX4,57,IO_L15_34_JX4_P,P7,6 +set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS25} [get_ports gp_in[20]] ; ## U1,V20,IO_L16_34_JX4_P,JX4,58,IO_L16_34_JX4_P,P7,5 +set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS25} [get_ports gp_out[21]] ; ## U1,U20,IO_L15_34_JX4_N,JX4,59,IO_L15_34_JX4_N,P7,8 +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports gp_in[21]] ; ## U1,W20,IO_L16_34_JX4_N,JX4,60,IO_L16_34_JX4_N,P7,7 From d44eca1521d749d5423227f7ea9164e60485d1a4 Mon Sep 17 00:00:00 2001 From: billue Date: Mon, 20 Apr 2020 04:04:47 +0800 Subject: [PATCH 02/44] nh7020 box-support --- library/Makefile | 2 + library/util_gpsdo/Makefile | 12 + library/util_gpsdo/ad5683_spi.v | 81 +++++ library/util_gpsdo/nh7020_ref_pll.v | 278 +++++++++++++++ library/util_gpsdo/util_gpsdo.v | 41 +++ library/util_gpsdo/util_gpsdo_constr.xdc | 9 + library/util_gpsdo/util_gpsdo_ip.tcl | 46 +++ projects/nh7020/ccbox_lvds/Makefile | 27 ++ projects/nh7020/ccbox_lvds/ad5683_spi.v | 81 +++++ projects/nh7020/ccbox_lvds/nh7020_ref_pll.v | 75 +++++ projects/nh7020/ccbox_lvds/system_bd.tcl | 11 + projects/nh7020/ccbox_lvds/system_project.tcl | 17 + projects/nh7020/ccbox_lvds/system_top.v | 316 ++++++++++++++++++ projects/nh7020/common/adrv9364z7020_bd.tcl | 22 +- .../nh7020/common/adrv9364z7020_constr.xdc | 2 + projects/nh7020/common/ccbob_bd.tcl | 4 +- projects/nh7020/common/ccbox_bd.tcl | 52 +++ projects/nh7020/common/ccbox_constr.xdc | 46 +++ 18 files changed, 1117 insertions(+), 5 deletions(-) create mode 100644 library/util_gpsdo/Makefile create mode 100644 library/util_gpsdo/ad5683_spi.v create mode 100644 library/util_gpsdo/nh7020_ref_pll.v create mode 100644 library/util_gpsdo/util_gpsdo.v create mode 100644 library/util_gpsdo/util_gpsdo_constr.xdc create mode 100644 library/util_gpsdo/util_gpsdo_ip.tcl create mode 100644 projects/nh7020/ccbox_lvds/Makefile create mode 100644 projects/nh7020/ccbox_lvds/ad5683_spi.v create mode 100644 projects/nh7020/ccbox_lvds/nh7020_ref_pll.v create mode 100644 projects/nh7020/ccbox_lvds/system_bd.tcl create mode 100644 projects/nh7020/ccbox_lvds/system_project.tcl create mode 100644 projects/nh7020/ccbox_lvds/system_top.v create mode 100644 projects/nh7020/common/ccbox_bd.tcl create mode 100644 projects/nh7020/common/ccbox_constr.xdc diff --git a/library/Makefile b/library/Makefile index e174ee10e2f..d784886bd13 100644 --- a/library/Makefile +++ b/library/Makefile @@ -117,6 +117,7 @@ clean: $(MAKE) -C xilinx/axi_xcvrlb clean $(MAKE) -C xilinx/util_adxcvr clean $(MAKE) -C xilinx/util_clkdiv clean + $(MAKE) -C util_gpsdo clean $(MAKE) -C interfaces clean @@ -230,6 +231,7 @@ lib: $(MAKE) -C xilinx/axi_xcvrlb $(MAKE) -C xilinx/util_adxcvr $(MAKE) -C xilinx/util_clkdiv + $(MAKE) -C util_gpsdo $(MAKE) -C interfaces diff --git a/library/util_gpsdo/Makefile b/library/util_gpsdo/Makefile new file mode 100644 index 00000000000..4feef5dd5f4 --- /dev/null +++ b/library/util_gpsdo/Makefile @@ -0,0 +1,12 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_gpsdo + +GENERIC_DEPS += util_gpsdo.v + +XILINX_DEPS += util_gpsdo_ip.tcl + +include ../scripts/library.mk diff --git a/library/util_gpsdo/ad5683_spi.v b/library/util_gpsdo/ad5683_spi.v new file mode 100644 index 00000000000..0729d53c9c7 --- /dev/null +++ b/library/util_gpsdo/ad5683_spi.v @@ -0,0 +1,81 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 23:56:52 11/10/2019 +// Design Name: +// Module Name: ad5683_spi +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// dat -> update triger -> update dac -> software LDAC -> wait +// +////////////////////////////////////////////////////////////////////////////////// +module ad5683_spi( + input clk, + input[15:0] dat, + output sclk, + output mosi, + output sync_n + ); + + reg[15:0] ldat; + wire upd = (dat!=ldat); + + reg[5:0] scnt; + reg[3:0] cclk; + wire sclk_full = cclk == 4'b1111; + wire sclk_half = cclk == 4'b1000; + + reg sync_n_o; + reg sclk_o; + + reg[23:0] shift; + wire[23:0] nxt_shift = scnt == 1'b0 ? {4'b0011,dat,4'b0} : {shift[22:0], 1'b0}; + + assign sync_n = sync_n_o; + assign mosi = shift[23]; + assign sclk = sclk_o; + + initial + begin + ldat = 16'd0; + scnt = 6'b0; + cclk = 4'b0; + sync_n_o = 1'b1; + sclk_o = 1'b0; + shift = 24'd0; + end + + always@(posedge clk) + begin + if(upd) cclk <= cclk + 1'b1; + + if(sclk_half | sclk_full) sclk_o <= ~sclk_o; + end + + always@(posedge sclk_o) + begin + shift <= nxt_shift; + scnt <= scnt + 1'b1; + sync_n_o <= 1'b0; + + if(scnt == 6'b011000)begin + sync_n_o<=1'b1; + shift <= {4'b0001,20'b0}; + end else if(scnt == 6'b110001)begin + ldat <= dat; + scnt <= 1'b0; + sync_n_o <= 1'b1; + end + end + +endmodule diff --git a/library/util_gpsdo/nh7020_ref_pll.v b/library/util_gpsdo/nh7020_ref_pll.v new file mode 100644 index 00000000000..0a497773916 --- /dev/null +++ b/library/util_gpsdo/nh7020_ref_pll.v @@ -0,0 +1,278 @@ +// +// Copyright 2015 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +module nh7020_ref_pll( + input reset, + input clk, // 200 MHz sample clock + input refclk, // 40 MHz reference clock + input ref, // PPS or 10 MHz external reference + output reg locked, + + // SPI lines to AD5683 + output sclk, + output mosi, + output sync_n + ); + + // Base parameters + localparam SAMPLE_CLOCK_FREQ=200_000_000; + localparam REF_FREQ_PPS=1; + localparam REF_FREQ_10MHZ=10_000_000; + localparam REF_CLK_FREQ=40_000_000; + localparam PFD_FREQ_PPS=1; + localparam PFD_FREQ_10MHZ=10; + + // Lock detection parameters + localparam LOCK_TOLERANCE_PPM=10; //0.1 + localparam LOCK_MARGIN_PPS=(SAMPLE_CLOCK_FREQ/PFD_FREQ_PPS)/LOCK_TOLERANCE_PPM/1_000_000; + localparam LOCK_MARGIN_10MHZ=(SAMPLE_CLOCK_FREQ/PFD_FREQ_10MHZ)/LOCK_TOLERANCE_PPM/1_000_000; + + // Reference frequency detection parameters + // References are only valid if they are +/-5ppm because that is the range of the VCTXCO + localparam REF_PERIOD_PPS=SAMPLE_CLOCK_FREQ/REF_FREQ_PPS; + localparam REF_PERIOD_10MHZ=SAMPLE_CLOCK_FREQ/REF_FREQ_10MHZ; + localparam REF_PERIOD_PPS_MIN=REF_PERIOD_PPS-(REF_PERIOD_PPS*5/1_000_000)-1; + localparam REF_PERIOD_PPS_MAX=REF_PERIOD_PPS+(REF_PERIOD_PPS*5/1_000_000)+1; + localparam REF_PERIOD_10MHZ_MIN=REF_PERIOD_10MHZ-(REF_PERIOD_10MHZ*5/1_000_000)-1; + localparam REF_PERIOD_10MHZ_MAX=REF_PERIOD_10MHZ+(REF_PERIOD_10MHZ*5/1_000_000)+1; + + // R divider parameters + localparam RDIV_PPS=REF_FREQ_PPS/PFD_FREQ_PPS; + localparam RDIV_10MHZ=REF_FREQ_10MHZ/PFD_FREQ_10MHZ; + + // N divider parameters (refclk is divided by 2) + localparam NDIV_PPS=REF_CLK_FREQ/2/PFD_FREQ_PPS; + localparam NDIV_10MHZ=REF_CLK_FREQ/2/PFD_FREQ_10MHZ; + + // PFD parameters + localparam PFD_PERIOD_PPS=SAMPLE_CLOCK_FREQ/PFD_FREQ_PPS; + localparam PFD_PERIOD_10MHZ=SAMPLE_CLOCK_FREQ/PFD_FREQ_10MHZ; + + + // Initial divide by 2 for 40 MHz clock + // (since refclk cannot be sampled directly) + reg refclk_div; + always @(posedge refclk) begin + refclk_div <= ~refclk_div; + end + + // flop signals into sample clock domain together + reg [3:0] refsmp; + reg [3:0] refclksmp; + always @(posedge clk) begin + refsmp <= {refsmp[2:0],ref}; + refclksmp <= {refclksmp[2:0],refclk_div}; + end + + // rising edge detection + wire ref_rising = (refsmp[3:2] == 2'b01); + wire refclk_rising = (refclksmp[3:2] == 2'b01); + + // reference frequency detection + reg [27:0] refcnt; + reg ref_detected; + reg ref_is_10M; + reg ref_is_pps; + wire valid_ref = ref_is_10M | ref_is_pps; + always @(posedge clk) begin + if (reset) begin + refcnt <= 28'd0; + ref_detected <= 1'b0; + ref_is_10M <= 1'b0; + ref_is_pps <= 1'b0; + end + else if (ref_rising) begin + refcnt <= 28'd1; + ref_detected <= 1'b1; + ref_is_10M <= ((refcnt >= REF_PERIOD_10MHZ_MIN) && (refcnt <= REF_PERIOD_10MHZ_MAX)); + ref_is_pps <= ((refcnt >= REF_PERIOD_PPS_MIN) && (refcnt <= REF_PERIOD_PPS_MAX)); + end + else if ((ref_is_10M && (refcnt > REF_PERIOD_10MHZ_MAX)) || (refcnt > REF_PERIOD_PPS_MAX)) begin + // consider the reference lost + refcnt <= 28'd0; + ref_detected <= 1'b0; + ref_is_10M <= 1'b0; + ref_is_pps <= 1'b0; + end + else if (ref_detected) + refcnt <= refcnt + 28'd1; + end + + // R divider + wire [23:0] rdiv = ref_is_10M ? RDIV_10MHZ : RDIV_PPS; + reg [23:0] rcnt; + wire [23:0] next_rcnt = ~valid_ref ? 24'd0 : (rcnt == rdiv) ? 24'd1 : rcnt + 1'b1; + reg r_rising; + always @(posedge clk) begin + if (ref_rising) + rcnt <= next_rcnt; + r_rising <= (ref_rising && ((ref_is_10M && (rcnt == rdiv)) || ref_is_pps)); + end + + // N divider + // Enable on rising edge of R after valid_ref + // is asserted so R and N signals start aligned. + // Disable if reference lost. + wire [25:0] ndiv = ref_is_10M ? NDIV_10MHZ : NDIV_PPS; + reg [25:0] ncnt; + wire [25:0] next_ncnt = ~valid_ref ? 26'd0 : ncnt == ndiv ? 26'd1 : ncnt + 1'b1; + reg n_rising; + always @(posedge clk) begin + if (refclk_rising) + ncnt <= next_ncnt; + n_rising <= (refclk_rising && (ncnt == ndiv)); + end + + // Frequency Counter + wire signed [28:0] period = ref_is_10M ? PFD_PERIOD_10MHZ : PFD_PERIOD_PPS; + reg signed [28:0] r_period_cnt; + reg signed [28:0] freq_err; + always @(posedge clk) begin + if (reset | ~valid_ref) begin + r_period_cnt <= 28'd0; + freq_err <= 29'sd0; + end + else if (r_rising) begin + r_period_cnt <= 28'd1; + freq_err <= period - r_period_cnt; + end + else + r_period_cnt <= r_period_cnt + 28'd1; + end + + // Phase Counter + reg signed [28:0] lead_cnt; + reg lead_cnt_ena; + reg signed [28:0] lead; + always @(posedge clk) begin + // Count how much N leads R + // The count is negative because it measures + // how much the VCTCXO must be slowed down. + if (~valid_ref | n_rising) begin + lead_cnt <= 29'sd0; + lead_cnt_ena <= 1'b1; + if (r_rising) + lead <= 29'sd0; + end + else if (r_rising) begin + if (lead_cnt_ena) + lead <= lead_cnt - 29'sd1; + else begin + // R rising with no preceding N rising. + // N has changed from leading to lagging R, + // but we don't yet know by how much so + // assume 1. + lead <= 29'sd1; + end + lead_cnt_ena <= 1'b0; + end + else if (lead_cnt_ena) + lead_cnt <= lead_cnt - 29'sd1; + end + + // PFD State Machine + localparam MEASURE=4'd0; + localparam CAPTURE=4'd1; + localparam CAPTURE_LAG=4'd2; + localparam CAPTURE_LEAD=4'd3; + localparam CALCULATE_ERROR=4'd4; + localparam CALCULATE_10M_GAIN=4'd5; + localparam CALCULATE_ADJUSTMENT=4'd6; + localparam CALCULATE_OUTPUT_VALUE=4'd7; + localparam APPLY_OUTPUT_VALUE=4'd8; + reg [3:0] state; + reg [15:0] daco = 16'd32767; + wire signed [28:0] lock_margin = ref_is_10M ? LOCK_MARGIN_10MHZ : LOCK_MARGIN_PPS; + wire signed [28:0] lag = lead + period; + reg signed [28:0] phase_err; + reg signed [28:0] err; + reg signed [28:0] shift; + reg signed [28:0] adj; + wire signed [28:0] dacv = {13'd0, daco}; + reg signed [28:0] sum; + reg [2:0] ld; + always @(posedge clk) begin + if (reset || ~valid_ref) begin + state <= MEASURE; + daco <= 16'd32767; + err <= 29'sd0; + shift <= 29'sd0; + adj <= 29'sd0; + ld <= 3'd0; + end + else begin + case(state) + MEASURE: begin + if (r_rising) + state <= CAPTURE; + end + CAPTURE: begin + if (lag < -lead) + state <= CAPTURE_LAG; + else + state <= CAPTURE_LEAD; + end + CAPTURE_LAG: begin + phase_err <= lag; + ld <= {ld[1:0], (lag <= lock_margin)}; + state <= CALCULATE_ERROR; + end + CAPTURE_LEAD: begin + phase_err <= lead; + ld <= {ld[1:0], (-lead <= lock_margin)}; + state <= CALCULATE_ERROR; + end + CALCULATE_ERROR: begin + err <= phase_err + freq_err; + state <= ref_is_10M ? CALCULATE_10M_GAIN : CALCULATE_ADJUSTMENT; + end + CALCULATE_10M_GAIN: begin + shift <= (err < -7 || err > 7) ? 7 : (err < 0 ? -err : err); + state <= CALCULATE_ADJUSTMENT; + end + CALCULATE_ADJUSTMENT: begin + // The VCTCXO is +/-5 ppm from 0.3V to 1.5V and the DAC is 16 bits, + // which works out to 0.000228885 ppm per DAC unit. + // The 200 MHz sampling clock means each unit of error is 0.005 ppm, + // which works out to 21.845 DAC units to correct each unit of error. + // Theory is nice, but the proportional and integral gains used here + // were determined through manual tuning. + if (ref_is_10M) + adj <= (err <<< shift); + else + adj <= (err <<< 4) - err; + state <= CALCULATE_OUTPUT_VALUE; + end + CALCULATE_OUTPUT_VALUE: begin + sum <= dacv + adj; + state <= APPLY_OUTPUT_VALUE; + end + APPLY_OUTPUT_VALUE: begin + // Clip and apply + if (sum < 29'sd0) + daco <= 16'd0; + else if (sum > 29'sd65535) + daco <= 16'd65535; + else + daco <= sum[15:0]; + state <= MEASURE; + end + endcase + end + end + + always @(posedge clk) + locked <= (ld == 3'b111); + + ad5683_spi dac + ( + .clk(refclk), + .dat(daco), + .sclk(sclk), + .mosi(mosi), + .sync_n(sync_n) + ); +endmodule diff --git a/library/util_gpsdo/util_gpsdo.v b/library/util_gpsdo/util_gpsdo.v new file mode 100644 index 00000000000..f2b53ea7f8a --- /dev/null +++ b/library/util_gpsdo/util_gpsdo.v @@ -0,0 +1,41 @@ +`timescale 1ns/100ps + +module util_gpsdo ( + input refclk, + input resetn, + input ref, + output locked, + // SPI lines to AD5683 + output sclk, + output mosi, + output sync_n +); + wire clk_ref_40; + wire clk_ref_200; + wire pll_locked; + wire rst_pll = ~pll_locked; + + clk_wiz_gps_ref clk_wiz_gps_ref_inst( + // Clock out ports + .clk_out_40(clk_ref_40), + .clk_out_200(clk_ref_200), + // Status and control signals + .resetn(resetn), + .locked(pll_locked), + // Clock in ports + .clk_in_40(refclk) + ); + + nh7020_ref_pll nh7020_ref_pll_inst( + .reset(rst_pll), + .clk(clk_ref_200), + .refclk(clk_ref_40), + .ref(ref), + .locked(locked), + .sclk(sclk), + .mosi(mosi), + .sync_n(sync_n) + ); + +endmodule // util_gpsdo + diff --git a/library/util_gpsdo/util_gpsdo_constr.xdc b/library/util_gpsdo/util_gpsdo_constr.xdc new file mode 100644 index 00000000000..b44fd555285 --- /dev/null +++ b/library/util_gpsdo/util_gpsdo_constr.xdc @@ -0,0 +1,9 @@ + +set_false_path -to [get_cells -hier -filter {name =~ *ld* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *refcnt* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *ref_is_10M* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *FSM_sequential_state* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *shift* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *adj* && IS_SEQUENTIAL}] + +set_false_path -from [get_cells -hier -filter {name =~ *lead* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *FSM_sequential_state* && IS_SEQUENTIAL}] + + diff --git a/library/util_gpsdo/util_gpsdo_ip.tcl b/library/util_gpsdo/util_gpsdo_ip.tcl new file mode 100644 index 00000000000..443358dca7f --- /dev/null +++ b/library/util_gpsdo/util_gpsdo_ip.tcl @@ -0,0 +1,46 @@ +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_gpsdo + +set clk_wiz_gps_ref [ create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name clk_wiz_gps_ref] +set_property -dict [list \ +CONFIG.PRIM_IN_FREQ {40.000} \ +CONFIG.CLKOUT2_USED {true} \ +CONFIG.PRIMARY_PORT {clk_in_40} \ +CONFIG.CLK_OUT1_PORT {clk_out_40} \ +CONFIG.CLK_OUT2_PORT {clk_out_200} \ +CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {40.000} \ +CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200.000} \ +CONFIG.CLKIN1_JITTER_PS {250.0} \ +CONFIG.MMCM_DIVCLK_DIVIDE {1} \ +CONFIG.MMCM_CLKFBOUT_MULT_F {25.000} \ +CONFIG.MMCM_CLKIN1_PERIOD {25.000} \ +CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ +CONFIG.MMCM_CLKOUT0_DIVIDE_F {25.000} \ +CONFIG.MMCM_CLKOUT1_DIVIDE {5} \ +CONFIG.NUM_OUT_CLKS {2} \ +CONFIG.CLKOUT1_JITTER {232.099} \ +CONFIG.CLKOUT1_PHASE_ERROR {191.950} \ +CONFIG.CLKOUT2_JITTER {158.299} \ +CONFIG.CLKOUT2_PHASE_ERROR {191.950} \ +CONFIG.RESET_TYPE {ACTIVE_LOW} \ +CONFIG.RESET_PORT {resetn} \ +] [get_ips clk_wiz_gps_ref] + + +generate_target {all} [get_files util_gpsdo.srcs/sources_1/ip/clk_wiz_gps_ref/clk_wiz_gps_ref.xci] + + +adi_ip_files util_gpsdo [list \ +"util_gpsdo_constr.xdc"\ +"ad5683_spi.v"\ +"nh7020_ref_pll.v"\ +"util_gpsdo.v" ] + +adi_ip_properties_lite util_gpsdo + +ipx::infer_bus_interface refclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface resetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] diff --git a/projects/nh7020/ccbox_lvds/Makefile b/projects/nh7020/ccbox_lvds/Makefile new file mode 100644 index 00000000000..3feaad7f4c4 --- /dev/null +++ b/projects/nh7020/ccbox_lvds/Makefile @@ -0,0 +1,27 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := adrv9364z7020_ccbox_lvds + +M_DEPS += ../common/ccbox_constr.xdc +M_DEPS += ../common/ccbox_bd.tcl +M_DEPS += ../common/adrv9364z7020_constr_lvds.xdc +M_DEPS += ../common/adrv9364z7020_constr.xdc +M_DEPS += ../common/adrv9364z7020_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl + +LIB_DEPS += axi_ad9361 +LIB_DEPS += axi_dmac +LIB_DEPS += axi_i2s_adi +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 +LIB_DEPS += util_rfifo +LIB_DEPS += util_tdd_sync +LIB_DEPS += util_wfifo +LIB_DEPS += util_gpsdo +LIB_DEPS += xilinx/util_clkdiv + +include ../../scripts/project-xilinx.mk diff --git a/projects/nh7020/ccbox_lvds/ad5683_spi.v b/projects/nh7020/ccbox_lvds/ad5683_spi.v new file mode 100644 index 00000000000..0729d53c9c7 --- /dev/null +++ b/projects/nh7020/ccbox_lvds/ad5683_spi.v @@ -0,0 +1,81 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 23:56:52 11/10/2019 +// Design Name: +// Module Name: ad5683_spi +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// dat -> update triger -> update dac -> software LDAC -> wait +// +////////////////////////////////////////////////////////////////////////////////// +module ad5683_spi( + input clk, + input[15:0] dat, + output sclk, + output mosi, + output sync_n + ); + + reg[15:0] ldat; + wire upd = (dat!=ldat); + + reg[5:0] scnt; + reg[3:0] cclk; + wire sclk_full = cclk == 4'b1111; + wire sclk_half = cclk == 4'b1000; + + reg sync_n_o; + reg sclk_o; + + reg[23:0] shift; + wire[23:0] nxt_shift = scnt == 1'b0 ? {4'b0011,dat,4'b0} : {shift[22:0], 1'b0}; + + assign sync_n = sync_n_o; + assign mosi = shift[23]; + assign sclk = sclk_o; + + initial + begin + ldat = 16'd0; + scnt = 6'b0; + cclk = 4'b0; + sync_n_o = 1'b1; + sclk_o = 1'b0; + shift = 24'd0; + end + + always@(posedge clk) + begin + if(upd) cclk <= cclk + 1'b1; + + if(sclk_half | sclk_full) sclk_o <= ~sclk_o; + end + + always@(posedge sclk_o) + begin + shift <= nxt_shift; + scnt <= scnt + 1'b1; + sync_n_o <= 1'b0; + + if(scnt == 6'b011000)begin + sync_n_o<=1'b1; + shift <= {4'b0001,20'b0}; + end else if(scnt == 6'b110001)begin + ldat <= dat; + scnt <= 1'b0; + sync_n_o <= 1'b1; + end + end + +endmodule diff --git a/projects/nh7020/ccbox_lvds/nh7020_ref_pll.v b/projects/nh7020/ccbox_lvds/nh7020_ref_pll.v new file mode 100644 index 00000000000..ea49e9d24fb --- /dev/null +++ b/projects/nh7020/ccbox_lvds/nh7020_ref_pll.v @@ -0,0 +1,75 @@ +// +// Copyright 2015 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +module nh7020_ref_pll( + input reset, + input clk, // 200 MHz sample clock + input refclk, // 40 MHz reference clock + input ref, // PPS or 10 MHz external reference + output reg locked, + + // SPI lines to AD5683 + output sclk, + output mosi, + output sync_n + ); + + + localparam BASE_REF_C = 100; + reg [5:0] refcounter; + reg main_ref; + reg dac_update; + reg [6:0] clkcounter; + reg [15:0] daco = 16'd32767; + + always@(posedge refclk) + begin + if(reset) + begin + refcounter <= 0; + main_ref <= 0; + end else begin + if(refcounter == 6'd39) + begin + main_ref <= ~main_ref; + refcounter <= 0; + end else + refcounter <= refcounter+1'b1; + end + end + + always@(posedge clk) + begin + if(reset) + begin + clkcounter <= 0; + dac_update <= 0; + end else + begin + if(main_ref) + begin + clkcounter <= clkcounter+1'b1; + dac_update <= 0; + end else begin + if(!dac_update) + begin + dac_update <= 1'b1; + daco <= daco + BASE_REF_C - clkcounter; + end + clkcounter <= 0; + end + end + end + + ad5683_spi dac + ( + .clk(refclk), + .dat(daco), + .sclk(sclk), + .mosi(mosi), + .sync_n(sync_n) + ); +endmodule diff --git a/projects/nh7020/ccbox_lvds/system_bd.tcl b/projects/nh7020/ccbox_lvds/system_bd.tcl new file mode 100644 index 00000000000..40a4a2df24c --- /dev/null +++ b/projects/nh7020/ccbox_lvds/system_bd.tcl @@ -0,0 +1,11 @@ + +source ../common/adrv9364z7020_bd.tcl +source ../common/ccbox_bd.tcl + +cfg_ad9361_interface LVDS + +create_bd_port -dir O sys_cpu_clk_out +ad_connect sys_cpu_clk sys_cpu_clk_out + +set_property CONFIG.ADC_INIT_DELAY 30 [get_bd_cells axi_ad9361] + diff --git a/projects/nh7020/ccbox_lvds/system_project.tcl b/projects/nh7020/ccbox_lvds/system_project.tcl new file mode 100644 index 00000000000..d4d8e543144 --- /dev/null +++ b/projects/nh7020/ccbox_lvds/system_project.tcl @@ -0,0 +1,17 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z020clg400-1" +adi_project adrv9364z7020_ccbox_lvds +adi_project_files adrv9364z7020_ccbox_lvds [list \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "../common/adrv9364z7020_constr.xdc" \ + "../common/adrv9364z7020_constr_lvds.xdc" \ + "../common/ccbox_constr.xdc" \ + "system_top.v" ] + +adi_project_run adrv9364z7020_ccbox_lvds +source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl + diff --git a/projects/nh7020/ccbox_lvds/system_top.v b/projects/nh7020/ccbox_lvds/system_top.v new file mode 100644 index 00000000000..e2b85ea6036 --- /dev/null +++ b/projects/nh7020/ccbox_lvds/system_top.v @@ -0,0 +1,316 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout iic_scl, + inout iic_sda, + inout [2:0] gpio_bd, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + output audio_pdn, + + output oled_csn, + output oled_clk, + output oled_mosi, + output oled_rst, + output oled_dc, + + input gps_pps, + output [5:0] gpio_led, + + inout tsw_s1, + inout tsw_s2, + inout tsw_s3, + inout tsw_s4, + inout tsw_s5, + inout tsw_a, + inout tsw_b, + + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, + + output enable, + output txnrx, + input clkout_in, + inout gpio_clksel, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, + + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso, + + output dac_spi_sdi, + output dac_spi_sclk, + output dac_spi_sync_n, + + input clk_40mhz +); + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + wire dac_locked; + + assign gpio_led[5:3] = {~gps_pps, ~dac_locked, 1'b1}; +/* + wire clk_200mhz_o; + wire dac_pll_locked; + wire dac_rest_n = ~(dac_pll_locked && gpio_o[9]); + + nh7020_ref_pll nh7020_ref_pll_inst( + .reset(dac_rest_n), + .clk(clk_100mhz_o), // 200 MHz sample clock + .refclk(clk_40mhz), // 40 MHz reference clock + .ref(gps_pps), // PPS or 10 MHz external reference + .locked(dac_locked), + + // SPI lines to AD5683 + .sclk(dac_spi_sclk), + .mosi(dac_spi_sdi), + .sync_n(dac_spi_sync_n) + ); + + clk_wiz_dac clk_wiz_dac_inst( + .clk_out_200mhz(clk_200mhz_o), + .clk_in_40mhz(clk_40mhz), + .resetn(1'b1), + .locked(dac_pll_locked) + ); + + //dac test only + //CLK_40 + IBUFG clk_40_buf( + .I(clk_40mhz), + .O(clk_40mhz_o) + ); + + reg[15:0] clk_dac_val = 16'd32767; + + ad5683_spi ad5683_inst( + .clk(clk_40mhz_o), + .dat(clk_dac_val), + .sclk(dac_spi_sclk), + .mosi(dac_spi_sdi), + .sync_n(dac_spi_sync_n) + ); +*/ + // assignments + assign audio_pdn = gpio_o[8]; + assign oled_clk = spi_clk; + assign oled_mosi = spi_mosi; + + // gpio[31:20] controls misc stuff (keep as io) + + assign gpio_i[31:12] = gpio_o[31:12]; + assign gpio_i[7:4] = {gps_pps, gpio_o[6:4]}; + + // gpio[3:0] controls the power switch led colors + assign gpio_led[2:0] = gpio_o[2:0]; + assign gpio_i[3:0] = gpio_o[3:0]; + + + // gpio[11:8] controls the imu/oled reset & such. + + assign oled_dc = gpio_o[11]; + assign oled_rst = gpio_o[10]; + assign gpio_i[11:8] = gpio_o[11:8]; + // unused gpio - 63:30 + assign gpio_i[63:60] = gpio_o[63:60]; + assign gpio_i[56:52] = gpio_o[56:52]; + + // tsw-part-2 gpio - 59:57 + + ad_iobuf #(.DATA_WIDTH(3)) i_iobuf_tsw_2 ( + .dio_t (gpio_t[59:57]), + .dio_i (gpio_o[59:57]), + .dio_o (gpio_i[59:57]), + .dio_p ({ tsw_a, // 59 + tsw_b, // 58 + tsw_s1})); // 57 + // tact-scroll-wheel gpio - 50:47 + + ad_iobuf #(.DATA_WIDTH(4)) i_iobuf_tsw_1 ( + .dio_t (gpio_t[50:47]), + .dio_i (gpio_o[50:47]), + .dio_o (gpio_i[50:47]), + .dio_p ({ tsw_s2, // 50 + tsw_s3, // 49 + tsw_s4, // 48 + tsw_s5})); // 47 + + ad_iobuf #(.DATA_WIDTH(16)) i_iobuf ( + .dio_t ({gpio_t[51], gpio_t[46:32]}), + .dio_i ({gpio_o[51], gpio_o[46:32]}), + .dio_o ({gpio_i[51], gpio_i[46:32]}), + .dio_p ({ gpio_clksel, // 51:51 + gpio_resetb, // 46:46 + gpio_sync, // 45:45 + gpio_en_agc, // 44:44 + gpio_ctl, // 43:40 + gpio_status})); // 39:32 + + + // instantiations + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .otg_vbusoc (1'b0), + .rx_clk_in_n (rx_clk_in_n), + .rx_clk_in_p (rx_clk_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_frame_in_p (rx_frame_in_p), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (oled_csn), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .tdd_sync_i (1'b0), + .tdd_sync_o (), + .tdd_sync_t (), + .gps_pps (gps_pps), + .gpsdo_ref_clk(clk_40mhz), + .gpsdo_locked(dac_locked), + .gpsdo_dac_sclk(dac_spi_sclk), + .gpsdo_dac_mosi(dac_spi_sdi), + .gpsdo_dac_sync_n(dac_spi_sync_n), + .sys_cpu_clk_out (sys_cpu_clk), + .tx_clk_out_n (tx_clk_out_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_frame_out_p (tx_frame_out_p), + .txnrx (txnrx), + .up_enable (gpio_o[47]), + .up_txnrx (gpio_o[48]) + ); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/nh7020/common/adrv9364z7020_bd.tcl b/projects/nh7020/common/adrv9364z7020_bd.tcl index 97c103e8bae..02fd0272030 100644 --- a/projects/nh7020/common/adrv9364z7020_bd.tcl +++ b/projects/nh7020/common/adrv9364z7020_bd.tcl @@ -63,12 +63,12 @@ ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_PERIPHERAL_ENABLE 1 ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_ENET0_IO "MIO 16 .. 27" ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_ENABLE 1 ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_IO "MIO 52 .. 53" -ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_PERIPHERAL_ENABLE 1 +#ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_PERIPHERAL_ENABLE 1 ad_ip_parameter sys_ps7 CONFIG.PCW_ENET_RESET_SELECT "Separate reset pins" ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_RESET_ENABLE 1 ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_RESET_IO "MIO 8" -ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_RESET_ENABLE 1 -ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_RESET_IO "MIO 51" +#ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_RESET_ENABLE 1 +#ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_RESET_IO "MIO 51" ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_PERIPHERAL_ENABLE 1 ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_GRP_CD_ENABLE 1 ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_GRP_CD_IO "MIO 50" @@ -214,6 +214,22 @@ ad_connect txnrx axi_ad9361/txnrx ad_connect up_enable axi_ad9361/up_enable ad_connect up_txnrx axi_ad9361/up_txnrx +# gpsdo +create_bd_port -dir I -type clk gpsdo_ref_clk +create_bd_port -dir O gpsdo_locked +create_bd_port -dir O gpsdo_dac_sclk +create_bd_port -dir O gpsdo_dac_mosi +create_bd_port -dir O gpsdo_dac_sync_n + +ad_ip_instance util_gpsdo util_gpsdo_ref +ad_connect gpsdo_ref_clk util_gpsdo_ref/refclk +ad_connect sys_cpu_resetn util_gpsdo_ref/resetn +ad_connect gps_pps util_gpsdo_ref/ref +ad_connect util_gpsdo_ref/locked gpsdo_locked +ad_connect util_gpsdo_ref/sclk gpsdo_dac_sclk +ad_connect util_gpsdo_ref/mosi gpsdo_dac_mosi +ad_connect util_gpsdo_ref/sync_n gpsdo_dac_sync_n + # tdd-sync ad_ip_instance util_tdd_sync util_ad9361_tdd_sync diff --git a/projects/nh7020/common/adrv9364z7020_constr.xdc b/projects/nh7020/common/adrv9364z7020_constr.xdc index f16c70ac4d8..5d3539e8d24 100644 --- a/projects/nh7020/common/adrv9364z7020_constr.xdc +++ b/projects/nh7020/common/adrv9364z7020_constr.xdc @@ -31,6 +31,7 @@ set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS25} [get_ports clkout_in set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports clk_40mhz] ; ## IO_L14P_T2_SRCC_34 +create_clock -name clock_txco -period 25 [get_ports clk_40mhz] # iic set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_scl] ; ## IO_L22N_T3_13 U1,W6,SCL,JX2,17,I2C_SCL @@ -42,6 +43,7 @@ set_property -dict {PACKAGE_PIN U8 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ set_property -dict {PACKAGE_PIN W10 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports dac_spi_sclk] ; ## IO_L17N_T2_13 set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports dac_spi_sync_n] ; ## IO_L17P_T2_13 + ## reference-only ## -------------- ## ad9361 (optional rf-card) diff --git a/projects/nh7020/common/ccbob_bd.tcl b/projects/nh7020/common/ccbob_bd.tcl index 16086371fe9..b30fda3fdcf 100644 --- a/projects/nh7020/common/ccbob_bd.tcl +++ b/projects/nh7020/common/ccbob_bd.tcl @@ -1,8 +1,8 @@ # lbfmc -ad_connect sys_ps7/ENET1_GMII_RX_CLK GND -ad_connect sys_ps7/ENET1_GMII_TX_CLK GND +#ad_connect sys_ps7/ENET1_GMII_RX_CLK GND +#ad_connect sys_ps7/ENET1_GMII_TX_CLK GND # un-used io (regular) diff --git a/projects/nh7020/common/ccbox_bd.tcl b/projects/nh7020/common/ccbox_bd.tcl new file mode 100644 index 00000000000..2779ddad7fe --- /dev/null +++ b/projects/nh7020/common/ccbox_bd.tcl @@ -0,0 +1,52 @@ + +# unused + +#ad_connect sys_ps7/ENET1_GMII_RX_CLK GND +#ad_connect sys_ps7/ENET1_GMII_TX_CLK GND + +# GPS-UART + +set_property CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_USE_DMA0 1 [get_bd_cells sys_ps7] +set_property CONFIG.PCW_USE_DMA1 1 [get_bd_cells sys_ps7] + +# enable PPS receiver + +ad_ip_parameter axi_ad9361 CONFIG.PPS_RECEIVER_ENABLE 1 + +# i2s + +create_bd_port -dir O -type clk i2s_mclk +create_bd_intf_port -mode Master -vlnv analog.com:interface:i2s_rtl:1.0 i2s + +ad_ip_instance clk_wiz sys_audio_clkgen +ad_ip_parameter sys_audio_clkgen CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 12.288 +ad_ip_parameter sys_audio_clkgen CONFIG.USE_LOCKED false +ad_ip_parameter sys_audio_clkgen CONFIG.USE_RESET true +ad_ip_parameter sys_audio_clkgen CONFIG.RESET_TYPE ACTIVE_LOW +ad_ip_parameter sys_audio_clkgen CONFIG.USE_PHASE_ALIGNMENT false +ad_ip_parameter sys_audio_clkgen CONFIG.PRIM_SOURCE No_buffer + +ad_ip_instance axi_i2s_adi axi_i2s_adi +ad_ip_parameter axi_i2s_adi CONFIG.DMA_TYPE 1 +ad_ip_parameter axi_i2s_adi CONFIG.S_AXI_ADDRESS_WIDTH 16 + +ad_connect sys_200m_clk sys_audio_clkgen/clk_in1 +ad_connect sys_cpu_resetn sys_audio_clkgen/resetn +ad_connect sys_cpu_clk axi_i2s_adi/DMA_REQ_RX_ACLK +ad_connect sys_cpu_clk axi_i2s_adi/DMA_REQ_TX_ACLK +ad_connect sys_cpu_clk sys_ps7/DMA0_ACLK +ad_connect sys_cpu_clk sys_ps7/DMA1_ACLK +ad_connect sys_cpu_resetn axi_i2s_adi/DMA_REQ_RX_RSTN +ad_connect sys_cpu_resetn axi_i2s_adi/DMA_REQ_TX_RSTN +ad_connect sys_ps7/DMA0_REQ axi_i2s_adi/DMA_REQ_TX +ad_connect sys_ps7/DMA0_ACK axi_i2s_adi/DMA_ACK_TX +ad_connect sys_ps7/DMA1_REQ axi_i2s_adi/DMA_REQ_RX +ad_connect sys_ps7/DMA1_ACK axi_i2s_adi/DMA_ACK_RX +ad_connect sys_audio_clkgen/clk_out1 i2s_mclk +ad_connect sys_audio_clkgen/clk_out1 axi_i2s_adi/DATA_CLK_I +ad_connect i2s axi_i2s_adi/I2S + +ad_cpu_interconnect 0x77600000 axi_i2s_adi + diff --git a/projects/nh7020/common/ccbox_constr.xdc b/projects/nh7020/common/ccbox_constr.xdc new file mode 100644 index 00000000000..f8e96fe6149 --- /dev/null +++ b/projects/nh7020/common/ccbox_constr.xdc @@ -0,0 +1,46 @@ + +## constraints (ccbox.a) + +## orphans- io- (ps7 gpio) +## oled + +set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS33} [get_ports oled_csn] ; ## U1,V5,IO_L06_13_JX2_P,JX2,18,OLED_CS# +set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports oled_clk] ; ## U1,V7,IO_L11_SRCC_13_JX2_N,JX2,37,OLED_SCL +set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports oled_mosi] ; ## U1,T9,IO_L12_MRCC_13_JX2_P,JX2,36,OLED_SDI +set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS33} [get_ports oled_rst] ; ## U1,U7,IO_L11_SRCC_13_JX2_P,JX2,35,OLED_/RES +set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports oled_dc] ; ## U1,U10,IO_L12_MRCC_13_JX2_N,JX2,38,OLED_D/C + +## GPS (DATA-UART) +## U1,C5,PS_MIO14_500_JX4,JX4,93,GPS_TXD1_1V8 +## U1,C8,PS_MIO15_500_JX4,JX4,85,GPS_RXD1_1V8 + +set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS33} [get_ports gps_pps] ; ## U1,T5,IO_L19_13_JX2_P,JX2,61,GPS_PPS + +## orphans- io- (ps7 gpio) + +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports gpio_led[0]] ; ## LED TRX R +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports gpio_led[1]] ; ## LED TRX G +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports gpio_led[2]] ; ## LED TRX B + +set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVCMOS33} [get_ports gpio_led[3]] ; ## LED RX2 R +set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS33} [get_ports gpio_led[4]] ; ## LED RX2 G +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports gpio_led[5]] ; ## LED RX2 B + +## audio + +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports i2s_bclk] ; ## U1,Y6,IO_L13_MRCC_13_JX2_N,JX2,43,AUD_BCLK +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports i2s_lrclk] ; ## U1,Y9,IO_L14_SRCC_13_JX2_P,JX2,42,AUD_LRCLK +set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS33} [get_ports i2s_mclk] ; ## U1,Y7,IO_L13_MRCC_13_JX2_P,JX2,41,AUD_MCLK +set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports i2s_sdata_in] ; ## U1,Y8,IO_L14_SRCC_13_JX2_N,JX2,44,AUD_SDATA_IN +set_property -dict {PACKAGE_PIN W8 IOSTANDARD LVCMOS33} [get_ports i2s_sdata_out] ; ## U1,W8,IO_L15_13_JX2_P,JX2,47,AUD_SDATA_OUT +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS33} [get_ports audio_pdn] ; ## U1,V8,IO_L15_13_JX2_N +## tsw + +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports tsw_s1] ; ## IO_L01_34_P,NAV_SWITCH_S1 +set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports tsw_s2] ; ## IO_L03_34_P,NAV_SWITCH_S2 +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports tsw_s3] ; ## IO_L01_34_N,NAV_SWITCH_S3 +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports tsw_s4] ; ## IO_L04_34_p,NAV_SWITCH_S4 +set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports tsw_s5] ; ## IO_L02_34_P,NAV_SWITCH_S5 +set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports tsw_a] ; ## IO_L03_34_N,NAV_SWITCH_A +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports tsw_b] ; ## IO_L02_34_N,NAV_SWITCH_B + From bbb23178d08a3f1489c9e625dba6dda0577869d4 Mon Sep 17 00:00:00 2001 From: billue Date: Fri, 12 Jun 2020 03:43:29 +0800 Subject: [PATCH 03/44] update mainline --- projects/adrv9361z7035/ccbob_lvds/system_project.tcl | 2 +- projects/nh7020/ccbob_cmos/system_bd.tcl | 2 +- projects/nh7020/ccbob_cmos/system_project.tcl | 10 +++++----- projects/nh7020/ccbob_lvds/Makefile | 8 ++++---- projects/nh7020/ccbob_lvds/system_bd.tcl | 2 +- projects/nh7020/ccbob_lvds/system_project.tcl | 10 +++++----- projects/nh7020/ccbox_lvds/Makefile | 8 ++++---- projects/nh7020/ccbox_lvds/system_bd.tcl | 2 +- projects/nh7020/ccbox_lvds/system_project.tcl | 10 +++++----- .../common/{adrv9364z7020_bd.tcl => nh7020_bd.tcl} | 0 .../{adrv9364z7020_constr.xdc => nh7020_constr.xdc} | 0 ...364z7020_constr_cmos.xdc => nh7020_constr_cmos.xdc} | 0 ...364z7020_constr_lvds.xdc => nh7020_constr_lvds.xdc} | 0 13 files changed, 27 insertions(+), 27 deletions(-) rename projects/nh7020/common/{adrv9364z7020_bd.tcl => nh7020_bd.tcl} (100%) rename projects/nh7020/common/{adrv9364z7020_constr.xdc => nh7020_constr.xdc} (100%) rename projects/nh7020/common/{adrv9364z7020_constr_cmos.xdc => nh7020_constr_cmos.xdc} (100%) rename projects/nh7020/common/{adrv9364z7020_constr_lvds.xdc => nh7020_constr_lvds.xdc} (100%) diff --git a/projects/adrv9361z7035/ccbob_lvds/system_project.tcl b/projects/adrv9361z7035/ccbob_lvds/system_project.tcl index 51f026e7fbd..74280cde9f3 100644 --- a/projects/adrv9361z7035/ccbob_lvds/system_project.tcl +++ b/projects/adrv9361z7035/ccbob_lvds/system_project.tcl @@ -3,7 +3,7 @@ source ../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl -set p_device "xc7z035ifbg676-2L" +set p_device "xc7z030ifbg676-2L" adi_project adrv9361z7035_ccbob_lvds adi_project_files adrv9361z7035_ccbob_lvds [list \ "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ diff --git a/projects/nh7020/ccbob_cmos/system_bd.tcl b/projects/nh7020/ccbob_cmos/system_bd.tcl index 08f42059354..c5ac54e2ec3 100644 --- a/projects/nh7020/ccbob_cmos/system_bd.tcl +++ b/projects/nh7020/ccbob_cmos/system_bd.tcl @@ -1,5 +1,5 @@ -source ../common/adrv9364z7020_bd.tcl +source ../common/nh7020_bd.tcl source ../common/ccbob_bd.tcl ad_ip_parameter util_ad9361_divclk CONFIG.SEL_0_DIV 2 diff --git a/projects/nh7020/ccbob_cmos/system_project.tcl b/projects/nh7020/ccbob_cmos/system_project.tcl index 05f5438089c..0bdf7825bda 100644 --- a/projects/nh7020/ccbob_cmos/system_project.tcl +++ b/projects/nh7020/ccbob_cmos/system_project.tcl @@ -4,14 +4,14 @@ source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl set p_device "xc7z020clg400-1" -adi_project adrv9364z7020_ccbob_cmos -adi_project_files adrv9364z7020_ccbob_cmos [list \ +adi_project nh7020_ccbob_cmos +adi_project_files nh7020_ccbob_cmos [list \ "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ - "../common/adrv9364z7020_constr.xdc" \ - "../common/adrv9364z7020_constr_cmos.xdc" \ + "../common/nh7020_constr.xdc" \ + "../common/nh7020_constr_cmos.xdc" \ "../common/ccbob_constr.xdc" \ "system_top.v" ] -adi_project_run adrv9364z7020_ccbob_cmos +adi_project_run nh7020_ccbob_cmos source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl diff --git a/projects/nh7020/ccbob_lvds/Makefile b/projects/nh7020/ccbob_lvds/Makefile index 30b8d4c26a4..ee7d45d6793 100644 --- a/projects/nh7020/ccbob_lvds/Makefile +++ b/projects/nh7020/ccbob_lvds/Makefile @@ -3,13 +3,13 @@ ## Auto-generated, do not modify! #################################################################################### -PROJECT_NAME := adrv9364z7020_ccbob_lvds +PROJECT_NAME := nh7020_ccbob_lvds M_DEPS += ../common/ccbob_constr.xdc M_DEPS += ../common/ccbob_bd.tcl -M_DEPS += ../common/adrv9364z7020_constr_lvds.xdc -M_DEPS += ../common/adrv9364z7020_constr.xdc -M_DEPS += ../common/adrv9364z7020_bd.tcl +M_DEPS += ../common/nh7020_constr_lvds.xdc +M_DEPS += ../common/nh7020_constr.xdc +M_DEPS += ../common/nh7020_bd.tcl M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ad5683_spi.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl diff --git a/projects/nh7020/ccbob_lvds/system_bd.tcl b/projects/nh7020/ccbob_lvds/system_bd.tcl index eae7e851a7a..94a6451e38d 100644 --- a/projects/nh7020/ccbob_lvds/system_bd.tcl +++ b/projects/nh7020/ccbob_lvds/system_bd.tcl @@ -1,5 +1,5 @@ -source ../common/adrv9364z7020_bd.tcl +source ../common/nh7020_bd.tcl source ../common/ccbob_bd.tcl cfg_ad9361_interface LVDS diff --git a/projects/nh7020/ccbob_lvds/system_project.tcl b/projects/nh7020/ccbob_lvds/system_project.tcl index fb7a504f385..b8bef75b4b6 100644 --- a/projects/nh7020/ccbob_lvds/system_project.tcl +++ b/projects/nh7020/ccbob_lvds/system_project.tcl @@ -4,15 +4,15 @@ source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl set p_device "xc7z020clg400-1" -adi_project adrv9364z7020_ccbob_lvds -adi_project_files adrv9364z7020_ccbob_lvds [list \ +adi_project nh7020_ccbob_lvds +adi_project_files nh7020_ccbob_lvds [list \ "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ - "../common/adrv9364z7020_constr.xdc" \ - "../common/adrv9364z7020_constr_lvds.xdc" \ + "../common/nh7020_constr.xdc" \ + "../common/nh7020_constr_lvds.xdc" \ "../common/ccbob_constr.xdc" \ "ad5683_spi.v" \ "system_top.v" ] -adi_project_run adrv9364z7020_ccbob_lvds +adi_project_run nh7020_ccbob_lvds source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl diff --git a/projects/nh7020/ccbox_lvds/Makefile b/projects/nh7020/ccbox_lvds/Makefile index 3feaad7f4c4..2e3620c0497 100644 --- a/projects/nh7020/ccbox_lvds/Makefile +++ b/projects/nh7020/ccbox_lvds/Makefile @@ -3,13 +3,13 @@ ## Auto-generated, do not modify! #################################################################################### -PROJECT_NAME := adrv9364z7020_ccbox_lvds +PROJECT_NAME := nh7020_ccbox_lvds M_DEPS += ../common/ccbox_constr.xdc M_DEPS += ../common/ccbox_bd.tcl -M_DEPS += ../common/adrv9364z7020_constr_lvds.xdc -M_DEPS += ../common/adrv9364z7020_constr.xdc -M_DEPS += ../common/adrv9364z7020_bd.tcl +M_DEPS += ../common/nh7020_constr_lvds.xdc +M_DEPS += ../common/nh7020_constr.xdc +M_DEPS += ../common/nh7020_bd.tcl M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl diff --git a/projects/nh7020/ccbox_lvds/system_bd.tcl b/projects/nh7020/ccbox_lvds/system_bd.tcl index 40a4a2df24c..4521f363278 100644 --- a/projects/nh7020/ccbox_lvds/system_bd.tcl +++ b/projects/nh7020/ccbox_lvds/system_bd.tcl @@ -1,5 +1,5 @@ -source ../common/adrv9364z7020_bd.tcl +source ../common/nh7020_bd.tcl source ../common/ccbox_bd.tcl cfg_ad9361_interface LVDS diff --git a/projects/nh7020/ccbox_lvds/system_project.tcl b/projects/nh7020/ccbox_lvds/system_project.tcl index d4d8e543144..b699ba51b70 100644 --- a/projects/nh7020/ccbox_lvds/system_project.tcl +++ b/projects/nh7020/ccbox_lvds/system_project.tcl @@ -4,14 +4,14 @@ source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl set p_device "xc7z020clg400-1" -adi_project adrv9364z7020_ccbox_lvds -adi_project_files adrv9364z7020_ccbox_lvds [list \ +adi_project nh7020_ccbox_lvds +adi_project_files nh7020_ccbox_lvds [list \ "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ - "../common/adrv9364z7020_constr.xdc" \ - "../common/adrv9364z7020_constr_lvds.xdc" \ + "../common/nh7020_constr.xdc" \ + "../common/nh7020_constr_lvds.xdc" \ "../common/ccbox_constr.xdc" \ "system_top.v" ] -adi_project_run adrv9364z7020_ccbox_lvds +adi_project_run nh7020_ccbox_lvds source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl diff --git a/projects/nh7020/common/adrv9364z7020_bd.tcl b/projects/nh7020/common/nh7020_bd.tcl similarity index 100% rename from projects/nh7020/common/adrv9364z7020_bd.tcl rename to projects/nh7020/common/nh7020_bd.tcl diff --git a/projects/nh7020/common/adrv9364z7020_constr.xdc b/projects/nh7020/common/nh7020_constr.xdc similarity index 100% rename from projects/nh7020/common/adrv9364z7020_constr.xdc rename to projects/nh7020/common/nh7020_constr.xdc diff --git a/projects/nh7020/common/adrv9364z7020_constr_cmos.xdc b/projects/nh7020/common/nh7020_constr_cmos.xdc similarity index 100% rename from projects/nh7020/common/adrv9364z7020_constr_cmos.xdc rename to projects/nh7020/common/nh7020_constr_cmos.xdc diff --git a/projects/nh7020/common/adrv9364z7020_constr_lvds.xdc b/projects/nh7020/common/nh7020_constr_lvds.xdc similarity index 100% rename from projects/nh7020/common/adrv9364z7020_constr_lvds.xdc rename to projects/nh7020/common/nh7020_constr_lvds.xdc From 1087faa7fb62fba3743fb13cc391c248214c2014 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Mon, 5 Oct 2020 11:51:35 +0300 Subject: [PATCH 04/44] common/de10nano: Full HD 60 FPS support -change the video memory interfacing from f2h_axi_slave to f2h_sdram0 - add f2h_sdram1 port as the default interface for converter DMA - set as default the full HD resolution at 60 FPS (pixel clock 148.5MHz) - use a second 200MHz(198MHz) clock from the pixel_clk_pll, as DMA source to destination clock. --- projects/cn0540/common/cn0540_qsys.tcl | 2 +- .../common/de10nano/de10nano_system_qsys.tcl | 61 ++++++++++--------- 2 files changed, 32 insertions(+), 31 deletions(-) diff --git a/projects/cn0540/common/cn0540_qsys.tcl b/projects/cn0540/common/cn0540_qsys.tcl index 3ae6e2cfa26..dcc864d8e8e 100755 --- a/projects/cn0540/common/cn0540_qsys.tcl +++ b/projects/cn0540/common/cn0540_qsys.tcl @@ -6,7 +6,7 @@ set_instance_parameter_value axi_dmac_0 {DMA_TYPE_SRC} {1} set_instance_parameter_value axi_dmac_0 {DMA_TYPE_DEST} {0} set_instance_parameter_value axi_dmac_0 {CYCLIC} {0} set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_SRC} {32} -set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_DEST} {64} +set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_DEST} {128} # axi_spi_engine diff --git a/projects/common/de10nano/de10nano_system_qsys.tcl b/projects/common/de10nano/de10nano_system_qsys.tcl index dc32d1070bb..d6c6bb910ba 100644 --- a/projects/common/de10nano/de10nano_system_qsys.tcl +++ b/projects/common/de10nano/de10nano_system_qsys.tcl @@ -14,8 +14,9 @@ set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset add_instance sys_hps altera_hps set_instance_parameter_value sys_hps {MPU_EVENTS_Enable} {0} -set_instance_parameter_value sys_hps {F2SDRAM_Type} {AXI-3} -set_instance_parameter_value sys_hps {F2SDRAM_Width} {64} +set_instance_parameter_value sys_hps {F2SCLK_SDRAMCLK_Enable} {0} +set_instance_parameter_value sys_hps {F2SDRAM_Type} {AXI-3 AXI-3} +set_instance_parameter_value sys_hps {F2SDRAM_Width} {128 128} set_instance_parameter_value sys_hps {F2SINTERRUPT_Enable} {1} set_instance_parameter_value sys_hps {EMAC0_PinMuxing} {Unused} set_instance_parameter_value sys_hps {EMAC0_Mode} {N/A} @@ -130,8 +131,8 @@ proc ad_cpu_interconnect {m_base m_port} { proc ad_dma_interconnect {m_port} { - add_connection ${m_port} sys_hps.f2h_sdram0_data - set_connection_parameter_value ${m_port}/sys_hps.f2h_sdram0_data baseAddress {0x0000} + add_connection ${m_port} sys_hps.f2h_sdram1_data + set_connection_parameter_value ${m_port}/sys_hps.f2h_sdram1_data baseAddress {0x0000} } @@ -140,7 +141,7 @@ proc ad_dma_interconnect {m_port} { add_instance sys_dma_clk clock_source add_connection sys_hps.h2f_user0_clock sys_dma_clk.clk_in add_connection sys_clk.clk_reset sys_dma_clk.clk_in_reset -add_connection sys_dma_clk.clk sys_hps.f2h_sdram0_clock +add_connection sys_dma_clk.clk sys_hps.f2h_sdram1_clock # internal memory @@ -232,9 +233,13 @@ set_instance_parameter_value axi_hdmi_tx_0 {ID} {0} add_instance pixel_clk_pll altera_pll set_instance_parameter_value pixel_clk_pll {gui_feedback_clock} {Global Clock} set_instance_parameter_value pixel_clk_pll {gui_operation_mode} {direct} -set_instance_parameter_value pixel_clk_pll {gui_output_clock_frequency0} {74.25} +set_instance_parameter_value pixel_clk_pll {gui_number_of_clocks} {2} +set_instance_parameter_value pixel_clk_pll {gui_output_clock_frequency0} {148.5} +set_instance_parameter_value pixel_clk_pll {gui_output_clock_frequency1} {200} set_instance_parameter_value pixel_clk_pll {gui_phase_shift0} {0} +set_instance_parameter_value pixel_clk_pll {gui_phase_shift1} {0} set_instance_parameter_value pixel_clk_pll {gui_phase_shift_deg0} {0.0} +set_instance_parameter_value pixel_clk_pll {gui_phase_shift_deg1} {0.0} set_instance_parameter_value pixel_clk_pll {gui_phout_division} {1} set_instance_parameter_value pixel_clk_pll {gui_pll_auto_reset} {Off} set_instance_parameter_value pixel_clk_pll {gui_pll_bandwidth_preset} {Auto} @@ -261,11 +266,11 @@ set_instance_parameter_value video_dmac {CYCLIC} {1} set_instance_parameter_value video_dmac {HAS_AXIS_TLAST} {1} set_instance_parameter_value video_dmac {DMA_2D_TRANSFER} {1} set_instance_parameter_value video_dmac {DMA_DATA_WIDTH_DEST} {64} -set_instance_parameter_value video_dmac {DMA_DATA_WIDTH_SRC} {64} +set_instance_parameter_value video_dmac {DMA_DATA_WIDTH_SRC} {128} set_instance_parameter_value video_dmac {DMA_LENGTH_WIDTH} {24} set_instance_parameter_value video_dmac {DMA_TYPE_DEST} {1} set_instance_parameter_value video_dmac {DMA_TYPE_SRC} {0} -set_instance_parameter_value video_dmac {FIFO_SIZE} {4} +set_instance_parameter_value video_dmac {FIFO_SIZE} {8} set_instance_parameter_value video_dmac {ID} {0} set_instance_parameter_value video_dmac {SYNC_TRANSFER_START} {0} @@ -288,28 +293,24 @@ set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_recon set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll startPortLSB {0} set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll width {0} -add_connection sys_clk.clk pixel_clk_pll.refclk -add_connection sys_clk.clk_reset pixel_clk_pll.reset - -add_connection sys_clk.clk pixel_clk_pll_reconfig.mgmt_clk -add_connection sys_clk.clk_reset pixel_clk_pll_reconfig.mgmt_reset - -add_connection sys_clk.clk axi_hdmi_tx_0.s_axi_clock -add_connection sys_clk.clk_reset axi_hdmi_tx_0.s_axi_reset - -add_connection sys_clk.clk video_dmac.s_axi_clock -add_connection sys_clk.clk_reset video_dmac.s_axi_reset - -add_connection pixel_clk_pll.outclk0 axi_hdmi_tx_0.hdmi_clock -add_connection sys_hps.h2f_user2_clock axi_hdmi_tx_0.vdma_clock -add_connection sys_hps.h2f_user2_clock video_dmac.if_m_axis_aclk -add_connection sys_hps.h2f_user2_clock video_dmac.m_src_axi_clock -add_connection sys_clk.clk_reset video_dmac.m_src_axi_reset - -add_connection video_dmac.m_src_axi sys_hps.f2h_axi_slave -set_connection_parameter_value video_dmac.m_src_axi/sys_hps.f2h_axi_slave arbitrationPriority {1} -set_connection_parameter_value video_dmac.m_src_axi/sys_hps.f2h_axi_slave baseAddress {0x0000} -set_connection_parameter_value video_dmac.m_src_axi/sys_hps.f2h_axi_slave defaultConnection {0} +add_connection sys_clk.clk pixel_clk_pll.refclk +add_connection sys_clk.clk pixel_clk_pll_reconfig.mgmt_clk +add_connection sys_clk.clk axi_hdmi_tx_0.s_axi_clock +add_connection sys_clk.clk video_dmac.s_axi_clock +add_connection pixel_clk_pll.outclk1 video_dmac.m_src_axi_clock +add_connection pixel_clk_pll.outclk1 video_dmac.if_m_axis_aclk +add_connection pixel_clk_pll.outclk1 sys_hps.f2h_sdram0_clock +add_connection pixel_clk_pll.outclk1 axi_hdmi_tx_0.vdma_clock +add_connection pixel_clk_pll.outclk0 axi_hdmi_tx_0.hdmi_clock + +add_connection sys_clk.clk_reset pixel_clk_pll.reset +add_connection sys_clk.clk_reset pixel_clk_pll_reconfig.mgmt_reset +add_connection sys_clk.clk_reset axi_hdmi_tx_0.s_axi_reset +add_connection sys_clk.clk_reset video_dmac.m_src_axi_reset +add_connection sys_clk.clk_reset video_dmac.s_axi_reset + +add_connection video_dmac.m_src_axi sys_hps.f2h_sdram0_data +set_connection_parameter_value video_dmac.m_src_axi/sys_hps.f2h_sdram0_data baseAddress {0x0000} # interrupts From 39abfea65a8329112f53f4f56e84ce6d6b32b20b Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Mon, 5 Oct 2020 12:06:27 +0300 Subject: [PATCH 05/44] common/de10nano: Cosmetic updates only --- .../common/de10nano/de10nano_system_qsys.tcl | 34 +++++++++---------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/projects/common/de10nano/de10nano_system_qsys.tcl b/projects/common/de10nano/de10nano_system_qsys.tcl index d6c6bb910ba..2f8639a406f 100644 --- a/projects/common/de10nano/de10nano_system_qsys.tcl +++ b/projects/common/de10nano/de10nano_system_qsys.tcl @@ -230,6 +230,9 @@ set_instance_parameter_value axi_hdmi_tx_0 {CR_CB_N} {0} set_instance_parameter_value axi_hdmi_tx_0 {INTERFACE} {24_BIT} set_instance_parameter_value axi_hdmi_tx_0 {ID} {0} +add_interface axi_hdmi_tx_0_hdmi_if conduit end +set_interface_property axi_hdmi_tx_0_hdmi_if EXPORT_OF axi_hdmi_tx_0.hdmi_if + add_instance pixel_clk_pll altera_pll set_instance_parameter_value pixel_clk_pll {gui_feedback_clock} {Global Clock} set_instance_parameter_value pixel_clk_pll {gui_operation_mode} {direct} @@ -255,6 +258,20 @@ set_instance_parameter_value pixel_clk_pll_reconfig {ENABLE_BYTEENABLE} {0} set_instance_parameter_value pixel_clk_pll_reconfig {ENABLE_MIF} {0} set_instance_parameter_value pixel_clk_pll_reconfig {MIF_FILE_NAME} {} +add_connection pixel_clk_pll.reconfig_from_pll pixel_clk_pll_reconfig.reconfig_from_pll +set_connection_parameter_value pixel_clk_pll.reconfig_from_pll/pixel_clk_pll_reconfig.reconfig_from_pll endPort {} +set_connection_parameter_value pixel_clk_pll.reconfig_from_pll/pixel_clk_pll_reconfig.reconfig_from_pll endPortLSB {0} +set_connection_parameter_value pixel_clk_pll.reconfig_from_pll/pixel_clk_pll_reconfig.reconfig_from_pll startPort {} +set_connection_parameter_value pixel_clk_pll.reconfig_from_pll/pixel_clk_pll_reconfig.reconfig_from_pll startPortLSB {0} +set_connection_parameter_value pixel_clk_pll.reconfig_from_pll/pixel_clk_pll_reconfig.reconfig_from_pll width {0} + +add_connection pixel_clk_pll.reconfig_to_pll pixel_clk_pll_reconfig.reconfig_to_pll +set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll endPort {} +set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll endPortLSB {0} +set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll startPort {} +set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll startPortLSB {0} +set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll width {0} + add_instance video_dmac axi_dmac set_instance_parameter_value video_dmac {ASYNC_CLK_DEST_REQ_MANUAL} {1} set_instance_parameter_value video_dmac {ASYNC_CLK_REQ_SRC_MANUAL} {1} @@ -276,23 +293,6 @@ set_instance_parameter_value video_dmac {SYNC_TRANSFER_START} {0} add_connection video_dmac.m_axis axi_hdmi_tx_0.vdma_if axi4stream -add_interface axi_hdmi_tx_0_hdmi_if conduit end -set_interface_property axi_hdmi_tx_0_hdmi_if EXPORT_OF axi_hdmi_tx_0.hdmi_if - -add_connection pixel_clk_pll.reconfig_from_pll pixel_clk_pll_reconfig.reconfig_from_pll -set_connection_parameter_value pixel_clk_pll.reconfig_from_pll/pixel_clk_pll_reconfig.reconfig_from_pll endPort {} -set_connection_parameter_value pixel_clk_pll.reconfig_from_pll/pixel_clk_pll_reconfig.reconfig_from_pll endPortLSB {0} -set_connection_parameter_value pixel_clk_pll.reconfig_from_pll/pixel_clk_pll_reconfig.reconfig_from_pll startPort {} -set_connection_parameter_value pixel_clk_pll.reconfig_from_pll/pixel_clk_pll_reconfig.reconfig_from_pll startPortLSB {0} -set_connection_parameter_value pixel_clk_pll.reconfig_from_pll/pixel_clk_pll_reconfig.reconfig_from_pll width {0} - -add_connection pixel_clk_pll.reconfig_to_pll pixel_clk_pll_reconfig.reconfig_to_pll -set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll endPort {} -set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll endPortLSB {0} -set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll startPort {} -set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll startPortLSB {0} -set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll width {0} - add_connection sys_clk.clk pixel_clk_pll.refclk add_connection sys_clk.clk pixel_clk_pll_reconfig.mgmt_clk add_connection sys_clk.clk axi_hdmi_tx_0.s_axi_clock From b7fef66772513105f3225d8514144dc06781bcbf Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Mon, 5 Oct 2020 11:31:04 +0300 Subject: [PATCH 06/44] adv7513_de10nano: Fix gpio_bd assignments --- projects/adv7513/de10nano/system_top.v | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/projects/adv7513/de10nano/system_top.v b/projects/adv7513/de10nano/system_top.v index 669611e5c3b..7258fd72f49 100644 --- a/projects/adv7513/de10nano/system_top.v +++ b/projects/adv7513/de10nano/system_top.v @@ -131,9 +131,8 @@ module system_top ( // instantiations - assign gpio_i[63:32] = gpio_o[63:32]; - assign gpio_i[31:12] = gpio_o[31:12]; - assign gpio_i[11:4] = gpio_bd_i[5:0]; + assign gpio_i[63:14] = gpio_o[63:14]; + assign gpio_i[13:8] = gpio_bd_i[5:0]; assign gpio_bd_o[7:0] = gpio_o[7:0]; assign ltc2308_cs = gpio_o[41]; From db2662ec7ac176638e4c4dacb9f5851322754276 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Mon, 5 Oct 2020 11:34:18 +0300 Subject: [PATCH 07/44] axi_hdmi_tx: Remove deprecated constraint --- library/axi_hdmi_tx/axi_hdmi_tx_constr.sdc | 1 - 1 file changed, 1 deletion(-) diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_constr.sdc b/library/axi_hdmi_tx/axi_hdmi_tx_constr.sdc index 7f715c9a21d..46ade77d36c 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx_constr.sdc +++ b/library/axi_hdmi_tx/axi_hdmi_tx_constr.sdc @@ -7,4 +7,3 @@ set_false_path -from [get_registers *vdma_fs_waddr*] set_false_path -from [get_registers *up_xfer_status:i_vdma_xfer_status|up_xfer_toggle*] -to [get_registers *up_xfer_status:i_vdma_xfer_status|d_xfer_state_m1*] set_false_path -from [get_registers *up_xfer_status:i_vdma_xfer_status|d_xfer_toggle*] -to [get_registers *up_xfer_status:i_vdma_xfer_status|up_xfer_toggle_m1*] set_false_path -from [get_registers *up_xfer_status:i_vdma_xfer_status|d_xfer_data*] -to [get_registers *up_xfer_status:i_vdma_xfer_status|up_data_status*] -set_false_path -from [get_registers *up_core_preset*] -to [get_registers *ad_rst_sync_m1] From d7fcfc5722f0261fe00525fdb6b8ea54967806a7 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Tue, 22 Dec 2020 09:35:00 +0000 Subject: [PATCH 08/44] de10nano: Add hps_conv_usb_n signal to stabilize UART lines Without defining this signal, the UART lines receive garbage data when no cable is connected to the J4 USB UART port. The GPIO9 is enabled in the reference base design along with the 4MA CURRENT_STRENGTH constraint on the UART pins --- projects/adv7513/de10nano/system_top.v | 2 ++ projects/cn0540/de10nano/system_top.v | 2 ++ projects/common/de10nano/de10nano_system_assign.tcl | 3 +++ projects/common/de10nano/de10nano_system_qsys.tcl | 2 ++ 4 files changed, 9 insertions(+) diff --git a/projects/adv7513/de10nano/system_top.v b/projects/adv7513/de10nano/system_top.v index 7258fd72f49..333018a1de4 100644 --- a/projects/adv7513/de10nano/system_top.v +++ b/projects/adv7513/de10nano/system_top.v @@ -96,6 +96,7 @@ module system_top ( input uart0_rx, output uart0_tx, + inout hps_conv_usb_n, // board gpio @@ -205,6 +206,7 @@ module system_top ( .sys_hps_hps_io_hps_io_spim1_inst_MOSI (spim1_mosi), .sys_hps_hps_io_hps_io_spim1_inst_MISO (spim1_miso), .sys_hps_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0), + .sys_hps_hps_io_hps_io_gpio_inst_GPIO09 (hps_conv_usb_n), .sys_gpio_bd_in_port (gpio_i[31:0]), .sys_gpio_bd_out_port (gpio_o[31:0]), .sys_gpio_in_export (gpio_i[63:32]), diff --git a/projects/cn0540/de10nano/system_top.v b/projects/cn0540/de10nano/system_top.v index c1bb9a226ee..85300f29563 100755 --- a/projects/cn0540/de10nano/system_top.v +++ b/projects/cn0540/de10nano/system_top.v @@ -96,6 +96,7 @@ module system_top ( input uart0_rx, output uart0_tx, + inout hps_conv_usb_n, // board gpio @@ -257,6 +258,7 @@ module system_top ( .sys_hps_hps_io_hps_io_spim1_inst_MOSI (spim1_mosi), .sys_hps_hps_io_hps_io_spim1_inst_MISO (spim1_miso), .sys_hps_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0), + .sys_hps_hps_io_hps_io_gpio_inst_GPIO09 (hps_conv_usb_n), .sys_hps_i2c1_sda (i2c1_sda), .sys_hps_i2c1_out_data (i2c1_sda_oe), .sys_hps_i2c1_clk_clk (i2c1_scl_oe), diff --git a/projects/common/de10nano/de10nano_system_assign.tcl b/projects/common/de10nano/de10nano_system_assign.tcl index 581788b78ac..964bdf5881c 100644 --- a/projects/common/de10nano/de10nano_system_assign.tcl +++ b/projects/common/de10nano/de10nano_system_assign.tcl @@ -47,8 +47,11 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_i[5] set_location_assignment PIN_A22 -to uart0_rx set_location_assignment PIN_B21 -to uart0_tx +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to uart0_rx +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to uart0_tx set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_rx set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_tx +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_conv_usb_n # hps spi master diff --git a/projects/common/de10nano/de10nano_system_qsys.tcl b/projects/common/de10nano/de10nano_system_qsys.tcl index 2f8639a406f..98dc3f4b0e7 100644 --- a/projects/common/de10nano/de10nano_system_qsys.tcl +++ b/projects/common/de10nano/de10nano_system_qsys.tcl @@ -40,6 +40,8 @@ set_instance_parameter_value sys_hps {I2C0_PinMuxing} {FPGA} set_instance_parameter_value sys_hps {I2C0_Mode} {Full} set_instance_parameter_value sys_hps {I2C1_PinMuxing} {FPGA} set_instance_parameter_value sys_hps {I2C1_Mode} {Full} +set_instance_parameter_value sys_hps {GPIO_Enable} {No No No No No No No No No Yes No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} +set_instance_parameter_value sys_hps {LOANIO_Enable} {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} set_instance_parameter_value sys_hps {desired_cfg_clk_mhz} {80.0} set_instance_parameter_value sys_hps {S2FCLK_USER0CLK_Enable} {1} set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_Enable} {1} From 95dbfd2443414bd802e7fe260b13676b7e9e4746 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Wed, 6 Jan 2021 10:09:31 +0000 Subject: [PATCH 09/44] Revert "intel: Update projects to use ad_iobuf instead of ALT_IOBUF" This reverts commit a3a610728c0bee96950ebd95d2e908ea6a7f3d49. For the Intel tools the IOBUF is not correctly inferred from the HDL description. --- projects/ad_fmclidar1_ebz/a10soc/Makefile | 1 - .../a10soc/system_project.tcl | 1 - projects/ad_fmclidar1_ebz/a10soc/system_top.v | 7 ++-- projects/adv7513/de10nano/Makefile | 1 - projects/adv7513/de10nano/system_project.tcl | 3 -- projects/adv7513/de10nano/system_top.v | 16 ++++++--- projects/arradio/c5soc/Makefile | 1 - projects/arradio/c5soc/system_project.tcl | 3 -- projects/arradio/c5soc/system_top.v | 7 ++-- projects/cn0506_mii/a10soc/Makefile | 1 - projects/cn0506_mii/a10soc/system_project.tcl | 3 -- projects/cn0506_mii/a10soc/system_top.v | 7 ++-- projects/cn0506_rgmii/a10soc/Makefile | 1 - .../cn0506_rgmii/a10soc/system_project.tcl | 3 -- projects/cn0506_rgmii/a10soc/system_top.v | 7 ++-- projects/cn0540/de10nano/Makefile | 1 - projects/cn0540/de10nano/system_project.tcl | 1 - projects/cn0540/de10nano/system_top.v | 34 +++++++++++++------ 18 files changed, 42 insertions(+), 56 deletions(-) diff --git a/projects/ad_fmclidar1_ebz/a10soc/Makefile b/projects/ad_fmclidar1_ebz/a10soc/Makefile index 1f4b0e270c0..cdc6b485ca8 100644 --- a/projects/ad_fmclidar1_ebz/a10soc/Makefile +++ b/projects/ad_fmclidar1_ebz/a10soc/Makefile @@ -12,7 +12,6 @@ M_DEPS += ../../scripts/adi_pd_intel.tcl M_DEPS += ../../common/a10soc/a10soc_system_qsys.tcl M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl M_DEPS += ../../../library/util_cdc/sync_bits.v -M_DEPS += ../../../library/common/ad_iobuf.v LIB_DEPS += axi_dmac LIB_DEPS += axi_laser_driver diff --git a/projects/ad_fmclidar1_ebz/a10soc/system_project.tcl b/projects/ad_fmclidar1_ebz/a10soc/system_project.tcl index 0117f677feb..ce68a85ae06 100644 --- a/projects/ad_fmclidar1_ebz/a10soc/system_project.tcl +++ b/projects/ad_fmclidar1_ebz/a10soc/system_project.tcl @@ -11,7 +11,6 @@ source $ad_hdl_dir/projects/common/a10soc/a10soc_system_assign.tcl set_global_assignment -name VERILOG_FILE ../common/util_tia_chsel.v set_global_assignment -name VERILOG_FILE ../common/util_axis_syncgen.v set_global_assignment -name VERILOG_FILE ../../../library/util_cdc/sync_bits.v -set_global_assignment -name VERILOG_FILE ../../../library/common/ad_iobuf.v # # Note: This project requires a hardware rework to function correctly. diff --git a/projects/ad_fmclidar1_ebz/a10soc/system_top.v b/projects/ad_fmclidar1_ebz/a10soc/system_top.v index 210c4d6bff4..0964c92b93e 100644 --- a/projects/ad_fmclidar1_ebz/a10soc/system_top.v +++ b/projects/ad_fmclidar1_ebz/a10soc/system_top.v @@ -240,11 +240,8 @@ module system_top ( wire i2c_0_sda_in; wire i2c_0_sda_oe; - ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_i2c ( - .dio_t ({i2c_0_scl_out,i2c_0_sda_oe}), - .dio_i (2'b0), - .dio_o ({i2c_0_scl_in,i2c_0_sda_in}), - .dio_p ({afe_dac_scl,afe_dac_sda})); + ALT_IOBUF scl_iobuf (.i(1'b0), .oe(i2c_0_scl_out), .o(i2c_0_scl_in), .io(afe_dac_scl)); + ALT_IOBUF sda_iobuf (.i(1'b0), .oe(i2c_0_sda_oe), .o(i2c_0_sda_in), .io(afe_dac_sda)); // Block design instance diff --git a/projects/adv7513/de10nano/Makefile b/projects/adv7513/de10nano/Makefile index 33d33c09fed..86ad2018d6e 100644 --- a/projects/adv7513/de10nano/Makefile +++ b/projects/adv7513/de10nano/Makefile @@ -7,7 +7,6 @@ PROJECT_NAME := adv7513_de10nano M_DEPS += ../../common/de10nano/de10nano_system_qsys.tcl M_DEPS += ../../common/de10nano/de10nano_system_assign.tcl -M_DEPS += ../../../library/common/ad_iobuf.v LIB_DEPS += axi_dmac LIB_DEPS += axi_hdmi_tx diff --git a/projects/adv7513/de10nano/system_project.tcl b/projects/adv7513/de10nano/system_project.tcl index a3b62cfd865..136b9897675 100644 --- a/projects/adv7513/de10nano/system_project.tcl +++ b/projects/adv7513/de10nano/system_project.tcl @@ -6,7 +6,4 @@ adi_project adv7513_de10nano source $ad_hdl_dir/projects/common/de10nano/de10nano_system_assign.tcl -# files -set_global_assignment -name VERILOG_FILE ../../../library/common/ad_iobuf.v - execute_flow -compile diff --git a/projects/adv7513/de10nano/system_top.v b/projects/adv7513/de10nano/system_top.v index 333018a1de4..2374180c4ee 100644 --- a/projects/adv7513/de10nano/system_top.v +++ b/projects/adv7513/de10nano/system_top.v @@ -138,11 +138,17 @@ module system_top ( assign gpio_bd_o[7:0] = gpio_o[7:0]; assign ltc2308_cs = gpio_o[41]; - ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_hdmi_i2c ( - .dio_t ({i2c0_out_clk,i2c0_out_data}), - .dio_i (2'b0), - .dio_o ({i2c0_scl_in_clk,i2c0_sda}), - .dio_p ({hdmi_i2c_scl,hdmi_i2c_sda})); + ALT_IOBUF scl_iobuf ( + .i(1'b0), + .oe(i2c0_out_clk), + .o(i2c0_scl_in_clk), + .io(hdmi_i2c_scl)); + + ALT_IOBUF sda_iobuf ( + .i(1'b0), + .oe(i2c0_out_data), + .o(i2c0_sda), + .io(hdmi_i2c_sda)); system_bd i_system_bd ( .sys_clk_clk (sys_clk), diff --git a/projects/arradio/c5soc/Makefile b/projects/arradio/c5soc/Makefile index c212ee0e043..7c03edce9ab 100644 --- a/projects/arradio/c5soc/Makefile +++ b/projects/arradio/c5soc/Makefile @@ -9,7 +9,6 @@ M_DEPS += ../common/arradio_qsys.tcl M_DEPS += ../../scripts/adi_pd_intel.tcl M_DEPS += ../../common/c5soc/c5soc_system_qsys.tcl M_DEPS += ../../common/c5soc/c5soc_system_assign.tcl -M_DEPS += ../../../library/common/ad_iobuf.v LIB_DEPS += axi_ad9361 LIB_DEPS += axi_dmac diff --git a/projects/arradio/c5soc/system_project.tcl b/projects/arradio/c5soc/system_project.tcl index a1966e84b6e..eda7fe744c0 100644 --- a/projects/arradio/c5soc/system_project.tcl +++ b/projects/arradio/c5soc/system_project.tcl @@ -6,9 +6,6 @@ adi_project arradio_c5soc source $ad_hdl_dir/projects/common/c5soc/c5soc_system_assign.tcl -# files -set_global_assignment -name VERILOG_FILE ../../../library/common/ad_iobuf.v - # ad9361 interface set_location_assignment PIN_H15 -to rx_clk_in ; ## HSMC_CLKIN_p2 P201.156 diff --git a/projects/arradio/c5soc/system_top.v b/projects/arradio/c5soc/system_top.v index 2517ca4d0a9..c67580527f7 100644 --- a/projects/arradio/c5soc/system_top.v +++ b/projects/arradio/c5soc/system_top.v @@ -187,11 +187,8 @@ module system_top ( assign ga0 = 1'b0; assign ga1 = 1'b0; - ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_i2c ( - .dio_t ({i2c0_out_clk,i2c0_out_data}), - .dio_i (2'b0), - .dio_o ({i2c0_scl_in_clk,i2c0_sda}), - .dio_p ({scl,sda})); + ALT_IOBUF scl_iobuf (.i(1'b0), .oe(i2c0_out_clk), .o(i2c0_scl_in_clk), .io(scl)); + ALT_IOBUF sda_iobuf (.i(1'b0), .oe(i2c0_out_data), .o(i2c0_sda), .io(sda)); // instantiations diff --git a/projects/cn0506_mii/a10soc/Makefile b/projects/cn0506_mii/a10soc/Makefile index c7aff330cd6..3f6fa96b09b 100644 --- a/projects/cn0506_mii/a10soc/Makefile +++ b/projects/cn0506_mii/a10soc/Makefile @@ -9,7 +9,6 @@ M_DEPS += ../common/cn0506_qsys.tcl M_DEPS += ../../scripts/adi_pd_intel.tcl M_DEPS += ../../common/a10soc/a10soc_system_qsys.tcl M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl -M_DEPS += ../../../library/common/ad_iobuf.v LIB_DEPS += axi_sysid LIB_DEPS += sysid_rom diff --git a/projects/cn0506_mii/a10soc/system_project.tcl b/projects/cn0506_mii/a10soc/system_project.tcl index 4621641b777..d1c87d73234 100644 --- a/projects/cn0506_mii/a10soc/system_project.tcl +++ b/projects/cn0506_mii/a10soc/system_project.tcl @@ -6,9 +6,6 @@ adi_project cn0506_mii_a10soc source $ad_hdl_dir/projects/common/a10soc/a10soc_system_assign.tcl -# files -set_global_assignment -name VERILOG_FILE ../../../library/common/ad_iobuf.v - # Note: This projects requires a hardware rework to function correctly. # The rework connects FMC header pins directly to the FPGA so that they can be # accessed by the fabric. diff --git a/projects/cn0506_mii/a10soc/system_top.v b/projects/cn0506_mii/a10soc/system_top.v index 61099021ca5..a7f51a9198f 100644 --- a/projects/cn0506_mii/a10soc/system_top.v +++ b/projects/cn0506_mii/a10soc/system_top.v @@ -210,11 +210,8 @@ module system_top ( assign gpio_i[11: 4] = gpio_bd_i; assign gpio_bd_o = gpio_o[3:0]; - ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_mdio ( - .dio_t ({hps_emac_mdo_o_e_b,hps_emac_mdo_o_e_a}), - .dio_i ({hps_emac_mdo_o_b,hps_emac_mdo_o_a}), - .dio_o ({hps_emac_mdi_i_b,hps_emac_mdi_i_a}), - .dio_p ({mdio_fmc_b,mdio_fmc_a})); + ALT_IOBUF md_iobuf_a (.i(hps_emac_mdo_o_a), .oe(hps_emac_mdo_o_e_a), .o(hps_emac_mdi_i_a), .io(mdio_fmc_a)); + ALT_IOBUF md_iobuf_b (.i(hps_emac_mdo_o_b), .oe(hps_emac_mdo_o_e_b), .o(hps_emac_mdi_i_b), .io(mdio_fmc_b)); // peripheral reset diff --git a/projects/cn0506_rgmii/a10soc/Makefile b/projects/cn0506_rgmii/a10soc/Makefile index 0496d404991..a4821a3248e 100644 --- a/projects/cn0506_rgmii/a10soc/Makefile +++ b/projects/cn0506_rgmii/a10soc/Makefile @@ -9,7 +9,6 @@ M_DEPS += ../common/cn0506_qsys.tcl M_DEPS += ../../scripts/adi_pd_intel.tcl M_DEPS += ../../common/a10soc/a10soc_system_qsys.tcl M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl -M_DEPS += ../../../library/common/ad_iobuf.v LIB_DEPS += axi_sysid LIB_DEPS += sysid_rom diff --git a/projects/cn0506_rgmii/a10soc/system_project.tcl b/projects/cn0506_rgmii/a10soc/system_project.tcl index 88513612bfb..44cc906bc5f 100644 --- a/projects/cn0506_rgmii/a10soc/system_project.tcl +++ b/projects/cn0506_rgmii/a10soc/system_project.tcl @@ -6,9 +6,6 @@ adi_project cn0506_rgmii_a10soc source $ad_hdl_dir/projects/common/a10soc/a10soc_system_assign.tcl -# files -set_global_assignment -name VERILOG_FILE ../../../library/common/ad_iobuf.v - set_location_assignment PIN_G14 -to rgmii_rxc_a ; ## G06 FMCA_HPC_LA00_CC_P set_location_assignment PIN_B9 -to rgmii_rx_ctl_a ; ## H14 FMCA_HPC_LA07_N set_location_assignment PIN_C13 -to rgmii_rxd_a[0] ; ## H07 FMCA_HPC_LA02_P diff --git a/projects/cn0506_rgmii/a10soc/system_top.v b/projects/cn0506_rgmii/a10soc/system_top.v index c148bbbf4d9..ba34828f777 100644 --- a/projects/cn0506_rgmii/a10soc/system_top.v +++ b/projects/cn0506_rgmii/a10soc/system_top.v @@ -233,11 +233,8 @@ module system_top ( assign gpio_i[11: 4] = gpio_bd_i; assign gpio_bd_o = gpio_o[3:0]; - ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_mdio ( - .dio_t ({hps_emac_mdo_o_e_b,hps_emac_mdo_o_e_a}), - .dio_i ({hps_emac_mdo_o_b,hps_emac_mdo_o_a}), - .dio_o ({hps_emac_mdi_i_b,hps_emac_mdi_i_a}), - .dio_p ({mdio_fmc_b,mdio_fmc_a})); + ALT_IOBUF md_iobuf_a (.i(hps_emac_mdo_o_a), .oe(hps_emac_mdo_o_e_a), .o(hps_emac_mdi_i_a), .io(mdio_fmc_a)); + ALT_IOBUF md_iobuf_b (.i(hps_emac_mdo_o_b), .oe(hps_emac_mdo_o_e_b), .o(hps_emac_mdi_i_b), .io(mdio_fmc_b)); // peripheral reset diff --git a/projects/cn0540/de10nano/Makefile b/projects/cn0540/de10nano/Makefile index fb75cc44f4d..4a83d4dc288 100755 --- a/projects/cn0540/de10nano/Makefile +++ b/projects/cn0540/de10nano/Makefile @@ -8,7 +8,6 @@ PROJECT_NAME := cn0540_de10nano M_DEPS += ../common/cn0540_qsys.tcl M_DEPS += ../../common/de10nano/de10nano_system_qsys.tcl M_DEPS += ../../common/de10nano/de10nano_system_assign.tcl -M_DEPS += ../../../library/common/ad_iobuf.v LIB_DEPS += axi_dmac LIB_DEPS += axi_hdmi_tx diff --git a/projects/cn0540/de10nano/system_project.tcl b/projects/cn0540/de10nano/system_project.tcl index 2be9d6ea6e9..27a88a2f135 100755 --- a/projects/cn0540/de10nano/system_project.tcl +++ b/projects/cn0540/de10nano/system_project.tcl @@ -13,7 +13,6 @@ source $ad_hdl_dir/projects/common/de10nano/de10nano_system_assign.tcl set_global_assignment -name MESSAGE_DISABLE 15003 # files -set_global_assignment -name VERILOG_FILE ../../../library/common/ad_iobuf.v # SPI interface for ad7768-1 diff --git a/projects/cn0540/de10nano/system_top.v b/projects/cn0540/de10nano/system_top.v index 85300f29563..77739a57363 100755 --- a/projects/cn0540/de10nano/system_top.v +++ b/projects/cn0540/de10nano/system_top.v @@ -184,17 +184,29 @@ module system_top ( // IO Buffers for I2C - ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_i2c ( - .dio_t ({i2c1_scl_oe,i2c1_sda_oe}), - .dio_i (2'b0), - .dio_o ({i2c1_scl,i2c1_sda}), - .dio_p ({i2c_scl,i2c_sda})); - - ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_hdmi_i2c ( - .dio_t ({i2c0_out_clk,i2c0_out_data}), - .dio_i (2'b0), - .dio_o ({i2c0_scl_in_clk,i2c0_sda}), - .dio_p ({hdmi_i2c_scl,hdmi_i2c_sda})); + ALT_IOBUF scl_iobuf ( + .i(1'b0), + .oe(i2c1_scl_oe), + .o(i2c1_scl), + .io(i2c_scl)); + + ALT_IOBUF sda_iobuf ( + .i(1'b0), + .oe(i2c1_sda_oe), + .o(i2c1_sda), + .io(i2c_sda)); + + ALT_IOBUF scl_video_iobuf ( + .i(1'b0), + .oe(i2c0_out_clk), + .o(i2c0_scl_in_clk), + .io(hdmi_i2c_scl)); + + ALT_IOBUF sda_video_iobuf ( + .i(1'b0), + .oe(i2c0_out_data), + .o(i2c0_sda), + .io(hdmi_i2c_sda)); system_bd i_system_bd ( .sys_clk_clk (sys_clk), From 19f7a0b279c28d13e7f8836842f4cd2040594253 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Fri, 6 Nov 2020 11:13:05 +0000 Subject: [PATCH 10/44] daq3:zcu102: Connect overflow pins for the AD9680 TPL --- projects/daq3/zcu102/system_bd.tcl | 1 + 1 file changed, 1 insertion(+) diff --git a/projects/daq3/zcu102/system_bd.tcl b/projects/daq3/zcu102/system_bd.tcl index 735fad27c6f..a640f5c7464 100644 --- a/projects/daq3/zcu102/system_bd.tcl +++ b/projects/daq3/zcu102/system_bd.tcl @@ -68,6 +68,7 @@ ad_connect axi_ad9152_fifo/bypass dac_fifo_bypass ad_connect sys_dma_resetn axi_ad9680_dma/m_dest_axi_aresetn ad_connect axi_ad9680_dma/fifo_wr_clk util_daq3_xcvr/rx_out_clk_0 ad_connect axi_ad9680_cpack/packed_fifo_wr axi_ad9680_dma/fifo_wr +ad_connect axi_ad9680_cpack/fifo_wr_overflow axi_ad9680_tpl_core/adc_dovf ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0 ad_mem_hp0_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi From 9494bdfdbfa6151abd47de47deebe274433f48d0 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 20 Jan 2021 15:19:24 +0000 Subject: [PATCH 11/44] fmcomms8: zcu102: Fix lane swapping --- projects/fmcomms8/common/fmcomms8_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/fmcomms8/common/fmcomms8_bd.tcl b/projects/fmcomms8/common/fmcomms8_bd.tcl index 1519806a3ad..233711ef655 100644 --- a/projects/fmcomms8/common/fmcomms8_bd.tcl +++ b/projects/fmcomms8/common/fmcomms8_bd.tcl @@ -162,7 +162,7 @@ ad_xcvrpll axi_adrv9009_fmc_obs_xcvr/up_pll_rst util_adrv9009_fmc_xcvr/up_cpll_ ad_connect sys_cpu_resetn util_adrv9009_fmc_xcvr/up_rstn ad_connect sys_cpu_clk util_adrv9009_fmc_xcvr/up_clk -ad_xcvrcon util_adrv9009_fmc_xcvr axi_adrv9009_fmc_tx_xcvr axi_adrv9009_fmc_tx_jesd {} core_clk_c +ad_xcvrcon util_adrv9009_fmc_xcvr axi_adrv9009_fmc_tx_xcvr axi_adrv9009_fmc_tx_jesd {1 0 2 3 4 5 6 7} core_clk_c ad_xcvrcon util_adrv9009_fmc_xcvr axi_adrv9009_fmc_rx_xcvr axi_adrv9009_fmc_rx_jesd {0 1 4 5} core_clk_d ad_xcvrcon util_adrv9009_fmc_xcvr axi_adrv9009_fmc_obs_xcvr axi_adrv9009_fmc_obs_jesd {2 3 6 7} core_clk_c From 4ae19031c0b8302472d081c01ca946cee3b84db7 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Fri, 29 Jan 2021 11:51:34 +0000 Subject: [PATCH 12/44] adrv9009zu11eg:fmcomms8: Fix lane swapping for TX channels 0 and 1 on the FMCOMMS8 --- projects/adrv9009zu11eg/common/adrv9009zu11eg_bd.tcl | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/projects/adrv9009zu11eg/common/adrv9009zu11eg_bd.tcl b/projects/adrv9009zu11eg/common/adrv9009zu11eg_bd.tcl index 5678edaf8dd..8b223483413 100644 --- a/projects/adrv9009zu11eg/common/adrv9009zu11eg_bd.tcl +++ b/projects/adrv9009zu11eg/common/adrv9009zu11eg_bd.tcl @@ -349,7 +349,11 @@ ad_xcvrpll axi_adrv9009_som_obs_xcvr/up_pll_rst util_adrv9009_som_xcvr/up_cpll_ ad_connect sys_cpu_resetn util_adrv9009_som_xcvr/up_rstn ad_connect sys_cpu_clk util_adrv9009_som_xcvr/up_clk +if {$TX_NUM_OF_LANES == 16} { +ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_tx_xcvr axi_adrv9009_som_tx_jesd {0 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 16} core_clk_a +} else { ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_tx_xcvr axi_adrv9009_som_tx_jesd {} core_clk_a +} if {$RX_NUM_OF_LANES == 8} { ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_rx_xcvr axi_adrv9009_som_rx_jesd {0 1 4 5 8 9 12 13} core_clk_b From 2cbb4f7b75cdb20b0b6c125dc493b86cdb837242 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Mon, 24 Aug 2020 11:34:48 +0100 Subject: [PATCH 13/44] axi_adrv9001: Add TDD support --- library/axi_adrv9001/axi_adrv9001.v | 29 +++ library/axi_adrv9001/axi_adrv9001_core.v | 121 ++++++++++- library/axi_adrv9001/axi_adrv9001_hw.tcl | 15 ++ library/axi_adrv9001/axi_adrv9001_ip.tcl | 4 + library/axi_adrv9001/axi_adrv9001_tdd.v | 258 +++++++++++++++++++++++ library/axi_adrv9001/axi_adrv9001_tx.v | 4 +- 6 files changed, 421 insertions(+), 10 deletions(-) create mode 100644 library/axi_adrv9001/axi_adrv9001_tdd.v diff --git a/library/axi_adrv9001/axi_adrv9001.v b/library/axi_adrv9001/axi_adrv9001.v index 2b8de2538f0..5e0cba5b8d5 100644 --- a/library/axi_adrv9001/axi_adrv9001.v +++ b/library/axi_adrv9001/axi_adrv9001.v @@ -38,6 +38,7 @@ module axi_adrv9001 #( parameter ID = 0, parameter CMOS_LVDS_N = 0, + parameter TDD_DISABLE = 0, parameter IO_DELAY_GROUP = "dev_if_delay_group", parameter FPGA_TECHNOLOGY = 0, parameter FPGA_FAMILY = 0, @@ -90,6 +91,11 @@ module axi_adrv9001 #( output tx2_strobe_out_n_NC, output tx2_strobe_out_p_strobe_out, + output rx1_enable, + output rx2_enable, + output tx1_enable, + output tx2_enable, + input delay_clk, // user interface @@ -147,6 +153,14 @@ module axi_adrv9001 #( input [15:0] dac_2_data_q0, input dac_2_dunf, + // TDD interface + input tdd_sync, + + input gpio_rx1_enable_in, + input gpio_rx2_enable_in, + input gpio_tx1_enable_in, + input gpio_tx2_enable_in, + // axi interface input s_axi_aclk, input s_axi_aresetn, @@ -360,6 +374,7 @@ module axi_adrv9001 #( .NUM_LANES (NUM_LANES), .CMOS_LVDS_N (CMOS_LVDS_N), .DRP_WIDTH (DRP_WIDTH), + .TDD_DISABLE (TDD_DISABLE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_FAMILY (FPGA_FAMILY), .SPEED_GRADE (SPEED_GRADE), @@ -456,6 +471,15 @@ module axi_adrv9001 #( .delay_rx2_rst (delay_rx2_rst), .delay_rx2_locked (delay_rx2_locked), + // TDD interface + .tdd_sync (tdd_sync), + .tdd_rx1_rf_en (tdd_rx1_rf_en), + .tdd_tx1_rf_en (tdd_tx1_rf_en), + .tdd_if1_mode (tdd_if1_mode), + .tdd_rx2_rf_en (tdd_rx2_rf_en), + .tdd_tx2_rf_en (tdd_tx2_rf_en), + .tdd_if2_mode (tdd_if2_mode), + .up_rstn (up_rstn), .up_clk (up_clk), .up_wreq (up_wreq_s), @@ -482,6 +506,11 @@ module axi_adrv9001 #( assign dac_2_valid_i0 = dac_2_valid; assign dac_2_valid_q0 = dac_2_valid; + assign rx1_enable = tdd_if1_mode ? tdd_rx1_rf_en : gpio_rx1_enable_in; + assign rx2_enable = tdd_if2_mode ? tdd_rx2_rf_en : gpio_rx2_enable_in; + assign tx1_enable = tdd_if1_mode ? tdd_tx1_rf_en : gpio_tx1_enable_in; + assign tx2_enable = tdd_if2_mode ? tdd_tx2_rf_en : gpio_tx2_enable_in; + // up bus interface up_axi #( .AXI_ADDRESS_WIDTH(15) diff --git a/library/axi_adrv9001/axi_adrv9001_core.v b/library/axi_adrv9001/axi_adrv9001_core.v index 67c4deb1815..8f5d5615c44 100644 --- a/library/axi_adrv9001/axi_adrv9001_core.v +++ b/library/axi_adrv9001/axi_adrv9001_core.v @@ -40,6 +40,7 @@ module axi_ad9001_core #( parameter CMOS_LVDS_N = 0, parameter NUM_LANES = 3, parameter DRP_WIDTH = 5, + parameter TDD_DISABLE = 0, parameter FPGA_TECHNOLOGY = 0, parameter FPGA_FAMILY = 0, parameter SPEED_GRADE = 0, @@ -140,6 +141,16 @@ module axi_ad9001_core #( output [DRP_WIDTH*NUM_LANES-1:0] up_rx2_dwdata, input [DRP_WIDTH*NUM_LANES-1:0] up_rx2_drdata, + // TDD interface + input tdd_sync, + + output tdd_rx1_rf_en, + output tdd_tx1_rf_en, + output tdd_if1_mode, + output tdd_rx2_rf_en, + output tdd_tx2_rf_en, + output tdd_if2_mode, + // processor interface input up_rstn, @@ -154,9 +165,9 @@ module axi_ad9001_core #( output reg up_rack ); - wire up_wack_s[0:5]; - wire [31:0] up_rdata_s[0:5]; - wire up_rack_s[0:5]; + wire [7:0] up_wack_s; + wire [31:0] up_rdata_s[0:7]; + wire [7:0] up_rack_s; wire tx1_data_valid_A; wire [15:0] tx1_data_i_A; @@ -235,9 +246,16 @@ module axi_ad9001_core #( up_rack <= 'd0; up_wack <= 'd0; end else begin - up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5]; - up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3] | up_rack_s[4] | up_rack_s[5]; - up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3] | up_wack_s[4] | up_wack_s[5]; + up_rdata <= up_rdata_s[0] | + up_rdata_s[1] | + up_rdata_s[2] | + up_rdata_s[3] | + up_rdata_s[4] | + up_rdata_s[5] | + up_rdata_s[6] | + up_rdata_s[7]; + up_rack <= |up_rack_s; + up_wack <= |up_wack_s; end end @@ -257,11 +275,11 @@ module axi_ad9001_core #( i_rx1 ( .adc_rst (rx1_rst), .adc_clk (rx1_clk), - .adc_valid_A (rx1_data_valid), + .adc_valid_A (rx1_data_valid & tdd_rx1_valid), .adc_data_i_A (rx1_data_i), .adc_data_q_A (rx1_data_q), - .adc_valid_B (rx2_data_valid), + .adc_valid_B (rx2_data_valid & tdd_rx1_valid), .adc_data_i_B (rx2_data_i), .adc_data_q_B (rx2_data_q), @@ -316,7 +334,7 @@ module axi_ad9001_core #( i_rx2 ( .adc_rst (rx2_rst_loc), .adc_clk (rx2_clk), - .adc_valid_A (rx2_data_valid), + .adc_valid_A (rx2_data_valid & tdd_rx2_valid), .adc_data_i_A (rx2_data_i), .adc_data_q_A (rx2_data_q), @@ -380,6 +398,7 @@ module axi_ad9001_core #( .dac_single_lane (tx1_single_lane), .dac_sdr_ddr_n (tx1_sdr_ddr_n), .dac_r1_mode (tx1_r1_mode), + .tdd_tx_valid (tdd_tx1_valid), .dac_sync_in (1'b0), .dac_sync_out (), .dac_enable_i0 (dac_1_enable_i0), @@ -441,6 +460,7 @@ module axi_ad9001_core #( .dac_enable_q1 (), .dac_data_q1 (16'b0), .dac_dunf (dac_2_dunf), + .tdd_tx_valid (tdd_tx2_valid), .up_rstn (up_rstn), .up_clk (up_clk), .up_wreq (up_wreq), @@ -497,5 +517,88 @@ module axi_ad9001_core #( .up_rdata (up_rdata_s[5]), .up_rack (up_rack_s[5])); + generate + if (TDD_DISABLE == 0) begin + + wire tdd_rx2_rf_en_loc; + wire tdd_tx2_rf_en_loc; + wire tdd_if2_mode_loc; + + axi_adrv9001_tdd #( + .BASE_ADDRESS (6'h12) + ) i_tdd_1 ( + .clk (rx1_clk), + .rst (rx1_rst), + .tdd_rx_vco_en (), + .tdd_tx_vco_en (), + .tdd_rx_rf_en (tdd_rx1_rf_en), + .tdd_tx_rf_en (tdd_tx1_rf_en), + .tdd_enabled (tdd_if1_mode), + .tdd_status (8'h0), + .tdd_sync (tdd_sync), + .tdd_sync_cntr (), + .tdd_tx_valid (tdd_tx1_valid), + .tdd_rx_valid (tdd_rx1_valid), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[6]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[6]), + .up_rack (up_rack_s[6])); + + axi_adrv9001_tdd #( + .BASE_ADDRESS (6'h13) + ) i_tdd_2 ( + .clk (rx2_clk), + .rst (rx2_rst), + .tdd_rx_vco_en (), + .tdd_tx_vco_en (), + .tdd_rx_rf_en (tdd_rx2_rf_en_loc), + .tdd_tx_rf_en (tdd_tx2_rf_en_loc), + .tdd_enabled (tdd_if2_mode_loc), + .tdd_status (8'h0), + .tdd_sync (tdd_sync), + .tdd_sync_cntr (), + .tdd_tx_valid (tdd_tx2_valid), + .tdd_rx_valid (tdd_rx2_valid), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[7]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[7]), + .up_rack (up_rack_s[7])); + + assign tdd_rx2_rf_en = tx1_r1_mode&rx1_r1_mode ? tdd_rx2_rf_en_loc : tdd_rx1_rf_en; + assign tdd_tx2_rf_en = tx1_r1_mode&rx1_r1_mode ? tdd_tx2_rf_en_loc : tdd_tx1_rf_en; + assign tdd_if2_mode = tx1_r1_mode&rx1_r1_mode ? tdd_if2_mode_loc : tdd_if1_mode; + + end else begin + assign up_wack_s[6] = 1'b0; + assign up_rack_s[6] = 1'b0; + assign up_rdata_s[6] = 32'h0; + assign up_wack_s[7] = 1'b0; + assign up_rack_s[7] = 1'b0; + assign up_rdata_s[7] = 32'h0; + assign tdd_rx1_rf_en = 1'b1; + assign tdd_tx1_rf_en = 1'b1; + assign tdd_if1_mode = 1'b0; + assign tdd_tx1_valid = 1'b1; + assign tdd_rx1_valid = 1'b1; + assign tdd_rx2_rf_en = 1'b1; + assign tdd_tx2_rf_en = 1'b1; + assign tdd_if2_mode = 1'b0; + assign tdd_tx2_valid = 1'b1; + assign tdd_rx2_valid = 1'b1; + end + endgenerate + endmodule diff --git a/library/axi_adrv9001/axi_adrv9001_hw.tcl b/library/axi_adrv9001/axi_adrv9001_hw.tcl index 3df858a03a5..66b7f80d157 100644 --- a/library/axi_adrv9001/axi_adrv9001_hw.tcl +++ b/library/axi_adrv9001/axi_adrv9001_hw.tcl @@ -17,6 +17,9 @@ ad_ip_files axi_adrv9001 [list\ "$ad_hdl_dir/library/common/ad_dds.v" \ "$ad_hdl_dir/library/common/ad_datafmt.v" \ "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_tdd_cntrl.v" \ + "$ad_hdl_dir/library/common/ad_tdd_control.v" \ + "$ad_hdl_dir/library/common/ad_addsub.v" \ "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ "$ad_hdl_dir/library/common/up_xfer_status.v" \ "$ad_hdl_dir/library/common/up_clock_mon.v" \ @@ -46,6 +49,7 @@ ad_ip_files axi_adrv9001 [list\ "axi_adrv9001_tx_channel.v" \ "axi_adrv9001_core.v" \ "axi_adrv9001_constr.sdc" \ + "axi_adrv9001_tdd.v" \ "axi_adrv9001.v" ] # parameters @@ -163,6 +167,13 @@ add_interface_port dac_2_ch_1 dac_2_data_q0 data Input 16 ad_interface signal dac_2_dunf input 1 unf +add_interface tdd_if conduit end +add_interface_port tdd_if gpio_rx1_enable_in rx1_enable_in Input 1 +add_interface_port tdd_if gpio_rx2_enable_in rx2_enable_in Input 1 +add_interface_port tdd_if gpio_tx1_enable_in tx1_enable_in Input 1 +add_interface_port tdd_if gpio_tx2_enable_in tx2_enable_in Input 1 +add_interface_port tdd_if tdd_sync tdd_sync_in Input 1 + # updates proc axi_adrv9001_elab {} { @@ -197,6 +208,7 @@ proc axi_adrv9001_elab {} { add_interface_port device_if rx1_qdata_in_n_qdata2 rx1_qdata_in_n_qdata2 Input 1 add_interface_port device_if rx1_qdata_in_p_qdata3 rx1_qdata_in_p_qdata3 Input 1 add_interface_port device_if rx1_strobe_in_p_strobe_in rx1_strobe_in_p_strobe_in Input 1 + add_interface_port device_if rx1_enable rx1_enable Output 1 add_interface_port device_if rx2_dclk_in_p_dclk_in rx2_dclk_in_p_dclk_in Input 1 add_interface_port device_if rx2_idata_in_n_idata0 rx2_idata_in_n_idata0 Input 1 @@ -204,6 +216,7 @@ proc axi_adrv9001_elab {} { add_interface_port device_if rx2_qdata_in_n_qdata2 rx2_qdata_in_n_qdata2 Input 1 add_interface_port device_if rx2_qdata_in_p_qdata3 rx2_qdata_in_p_qdata3 Input 1 add_interface_port device_if rx2_strobe_in_p_strobe_in rx2_strobe_in_p_strobe_in Input 1 + add_interface_port device_if rx2_enable rx2_enable Output 1 add_interface_port device_if tx1_dclk_out_p_dclk_out tx1_dclk_out_p_dclk_out Output 1 add_interface_port device_if tx1_dclk_in_p_dclk_in tx1_dclk_in_p_dclk_in Input 1 @@ -212,6 +225,7 @@ proc axi_adrv9001_elab {} { add_interface_port device_if tx1_qdata_out_n_qdata2 tx1_qdata_out_n_qdata2 Output 1 add_interface_port device_if tx1_qdata_out_p_qdata3 tx1_qdata_out_p_qdata3 Output 1 add_interface_port device_if tx1_strobe_out_p_strobe_out tx1_strobe_out_p_strobe_out Output 1 + add_interface_port device_if tx1_enable tx1_enable Output 1 add_interface_port device_if tx2_dclk_out_p_dclk_out tx2_dclk_out_p_dclk_out Output 1 add_interface_port device_if tx2_dclk_in_p_dclk_in tx2_dclk_in_p_dclk_in Input 1 @@ -220,6 +234,7 @@ proc axi_adrv9001_elab {} { add_interface_port device_if tx2_qdata_out_n_qdata2 tx2_qdata_out_n_qdata2 Output 1 add_interface_port device_if tx2_qdata_out_p_qdata3 tx2_qdata_out_p_qdata3 Output 1 add_interface_port device_if tx2_strobe_out_p_strobe_out tx2_strobe_out_p_strobe_out Output 1 + add_interface_port device_if tx2_enable tx2_enable Output 1 } } diff --git a/library/axi_adrv9001/axi_adrv9001_ip.tcl b/library/axi_adrv9001/axi_adrv9001_ip.tcl index f16e80c128f..fd8cc5c071d 100644 --- a/library/axi_adrv9001/axi_adrv9001_ip.tcl +++ b/library/axi_adrv9001/axi_adrv9001_ip.tcl @@ -17,6 +17,9 @@ adi_ip_files axi_adrv9001 [list \ "$ad_hdl_dir/library/common/ad_dds_2.v" \ "$ad_hdl_dir/library/common/ad_dds.v" \ "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/up_tdd_cntrl.v" \ + "$ad_hdl_dir/library/common/ad_tdd_control.v" \ + "$ad_hdl_dir/library/common/ad_addsub.v" \ "$ad_hdl_dir/library/common/ad_rst.v" \ "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ "$ad_hdl_dir/library/common/up_xfer_status.v" \ @@ -47,6 +50,7 @@ adi_ip_files axi_adrv9001 [list \ "axi_adrv9001_tx_channel.v" \ "axi_adrv9001_core.v" \ "axi_adrv9001_constr.xdc" \ + "axi_adrv9001_tdd.v" \ "axi_adrv9001.v" ] adi_ip_properties axi_adrv9001 diff --git a/library/axi_adrv9001/axi_adrv9001_tdd.v b/library/axi_adrv9001/axi_adrv9001_tdd.v new file mode 100644 index 00000000000..fe5f5d90507 --- /dev/null +++ b/library/axi_adrv9001/axi_adrv9001_tdd.v @@ -0,0 +1,258 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module axi_adrv9001_tdd #( + parameter ID = 0, + parameter BASE_ADDRESS = 6'h20 +) ( + + // clock + + input clk, + input rst, + + // control signals from the tdd control + + output tdd_rx_vco_en, + output tdd_tx_vco_en, + output tdd_rx_rf_en, + output tdd_tx_rf_en, + + // status signal + + output tdd_enabled, + input [ 7:0] tdd_status, + + // sync signal + + input tdd_sync, + output reg tdd_sync_cntr, + + // tx/rx data flow control + + output reg tdd_tx_valid, + output reg tdd_rx_valid, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); + + // internal signals + + wire tdd_enable_s; + wire tdd_secondary_s; + wire [ 7:0] tdd_burst_count_s; + wire tdd_rx_only_s; + wire tdd_tx_only_s; + wire tdd_gated_rx_dmapath_s; + wire tdd_gated_tx_dmapath_s; + wire [23:0] tdd_counter_init_s; + wire [23:0] tdd_frame_length_s; + wire tdd_terminal_type_s; + wire tdd_sync_enable_s; + wire [23:0] tdd_vco_rx_on_1_s; + wire [23:0] tdd_vco_rx_off_1_s; + wire [23:0] tdd_vco_tx_on_1_s; + wire [23:0] tdd_vco_tx_off_1_s; + wire [23:0] tdd_rx_on_1_s; + wire [23:0] tdd_rx_off_1_s; + wire [23:0] tdd_rx_dp_on_1_s; + wire [23:0] tdd_rx_dp_off_1_s; + wire [23:0] tdd_tx_on_1_s; + wire [23:0] tdd_tx_off_1_s; + wire [23:0] tdd_tx_dp_on_1_s; + wire [23:0] tdd_tx_dp_off_1_s; + wire [23:0] tdd_vco_rx_on_2_s; + wire [23:0] tdd_vco_rx_off_2_s; + wire [23:0] tdd_vco_tx_on_2_s; + wire [23:0] tdd_vco_tx_off_2_s; + wire [23:0] tdd_rx_on_2_s; + wire [23:0] tdd_rx_off_2_s; + wire [23:0] tdd_rx_dp_on_2_s; + wire [23:0] tdd_rx_dp_off_2_s; + wire [23:0] tdd_tx_on_2_s; + wire [23:0] tdd_tx_off_2_s; + wire [23:0] tdd_tx_dp_on_2_s; + wire [23:0] tdd_tx_dp_off_2_s; + + wire [23:0] tdd_counter_status; + + wire tdd_rx_dp_en_s; + wire tdd_tx_dp_en_s; + + assign tdd_enabled = tdd_enable_s; + + // syncronization control signal + + always @(posedge clk) begin + if (tdd_enable_s == 1'b1) begin + tdd_sync_cntr <= ~tdd_terminal_type_s; + end else begin + tdd_sync_cntr <= 1'b0; + end + end + + // tx/rx data flow control + + always @(posedge clk) begin + if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin + tdd_tx_valid <= tdd_tx_dp_en_s; + end else begin + tdd_tx_valid <= 1'b1; + end + end + + always @(posedge clk) begin + if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin + tdd_rx_valid <= tdd_rx_dp_en_s; + end else begin + tdd_rx_valid <= 1'b1; + end + end + + // instantiations + + up_tdd_cntrl #( + .BASE_ADDRESS (BASE_ADDRESS) + ) i_up_tdd_cntrl( + .clk(clk), + .rst(rst), + .tdd_enable(tdd_enable_s), + .tdd_secondary(tdd_secondary_s), + .tdd_burst_count(tdd_burst_count_s), + .tdd_tx_only(tdd_tx_only_s), + .tdd_rx_only(tdd_rx_only_s), + .tdd_gated_rx_dmapath(tdd_gated_rx_dmapath_s), + .tdd_gated_tx_dmapath(tdd_gated_tx_dmapath_s), + .tdd_counter_init(tdd_counter_init_s), + .tdd_frame_length(tdd_frame_length_s), + .tdd_terminal_type(tdd_terminal_type_s), + .tdd_vco_rx_on_1(tdd_vco_rx_on_1_s), + .tdd_vco_rx_off_1(tdd_vco_rx_off_1_s), + .tdd_vco_tx_on_1(tdd_vco_tx_on_1_s), + .tdd_vco_tx_off_1(tdd_vco_tx_off_1_s), + .tdd_rx_on_1(tdd_rx_on_1_s), + .tdd_rx_off_1(tdd_rx_off_1_s), + .tdd_rx_dp_on_1(tdd_rx_dp_on_1_s), + .tdd_rx_dp_off_1(tdd_rx_dp_off_1_s), + .tdd_tx_on_1(tdd_tx_on_1_s), + .tdd_tx_off_1(tdd_tx_off_1_s), + .tdd_tx_dp_on_1(tdd_tx_dp_on_1_s), + .tdd_tx_dp_off_1(tdd_tx_dp_off_1_s), + .tdd_vco_rx_on_2(tdd_vco_rx_on_2_s), + .tdd_vco_rx_off_2(tdd_vco_rx_off_2_s), + .tdd_vco_tx_on_2(tdd_vco_tx_on_2_s), + .tdd_vco_tx_off_2(tdd_vco_tx_off_2_s), + .tdd_rx_on_2(tdd_rx_on_2_s), + .tdd_rx_off_2(tdd_rx_off_2_s), + .tdd_rx_dp_on_2(tdd_rx_dp_on_2_s), + .tdd_rx_dp_off_2(tdd_rx_dp_off_2_s), + .tdd_tx_on_2(tdd_tx_on_2_s), + .tdd_tx_off_2(tdd_tx_off_2_s), + .tdd_tx_dp_on_2(tdd_tx_dp_on_2_s), + .tdd_tx_dp_off_2(tdd_tx_dp_off_2_s), + .tdd_status(tdd_status), + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_wack(up_wack), + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata), + .up_rack(up_rack)); + + // the TX_DATA_PATH_DELAY and CONTROL_PATH_DELAY are specificly defined + // for the axi_adrv9001 core + + ad_tdd_control #( + .TX_DATA_PATH_DELAY(), + .CONTROL_PATH_DELAY()) + i_tdd_control( + .clk(clk), + .rst(rst), + .tdd_enable(tdd_enable_s), + .tdd_secondary(tdd_secondary_s), + .tdd_counter_init(tdd_counter_init_s), + .tdd_frame_length(tdd_frame_length_s), + .tdd_burst_count(tdd_burst_count_s), + .tdd_rx_only(tdd_rx_only_s), + .tdd_tx_only(tdd_tx_only_s), + .tdd_sync (tdd_sync), + .tdd_vco_rx_on_1(tdd_vco_rx_on_1_s), + .tdd_vco_rx_off_1(tdd_vco_rx_off_1_s), + .tdd_vco_tx_on_1(tdd_vco_tx_on_1_s), + .tdd_vco_tx_off_1(tdd_vco_tx_off_1_s), + .tdd_rx_on_1(tdd_rx_on_1_s), + .tdd_rx_off_1(tdd_rx_off_1_s), + .tdd_rx_dp_on_1(tdd_rx_dp_on_1_s), + .tdd_rx_dp_off_1(tdd_rx_dp_off_1_s), + .tdd_tx_on_1(tdd_tx_on_1_s), + .tdd_tx_off_1(tdd_tx_off_1_s), + .tdd_tx_dp_on_1(tdd_tx_dp_on_1_s), + .tdd_tx_dp_off_1(tdd_tx_dp_off_1_s), + .tdd_vco_rx_on_2(tdd_vco_rx_on_2_s), + .tdd_vco_rx_off_2(tdd_vco_rx_off_2_s), + .tdd_vco_tx_on_2(tdd_vco_tx_on_2_s), + .tdd_vco_tx_off_2(tdd_vco_tx_off_2_s), + .tdd_rx_on_2(tdd_rx_on_2_s), + .tdd_rx_off_2(tdd_rx_off_2_s), + .tdd_rx_dp_on_2(tdd_rx_dp_on_2_s), + .tdd_rx_dp_off_2(tdd_rx_dp_off_2_s), + .tdd_tx_on_2(tdd_tx_on_2_s), + .tdd_tx_off_2(tdd_tx_off_2_s), + .tdd_tx_dp_on_2(tdd_tx_dp_on_2_s), + .tdd_tx_dp_off_2(tdd_tx_dp_off_2_s), + .tdd_rx_dp_en(tdd_rx_dp_en_s), + .tdd_tx_dp_en(tdd_tx_dp_en_s), + .tdd_rx_vco_en(tdd_rx_vco_en), + .tdd_tx_vco_en(tdd_tx_vco_en), + .tdd_rx_rf_en(tdd_rx_rf_en), + .tdd_tx_rf_en(tdd_tx_rf_en), + .tdd_counter_status(tdd_counter_status)); + +endmodule diff --git a/library/axi_adrv9001/axi_adrv9001_tx.v b/library/axi_adrv9001/axi_adrv9001_tx.v index c23f65e16e5..989b1016bd1 100644 --- a/library/axi_adrv9001/axi_adrv9001_tx.v +++ b/library/axi_adrv9001/axi_adrv9001_tx.v @@ -67,6 +67,8 @@ module axi_adrv9001_tx #( output dac_sdr_ddr_n, output dac_r1_mode, + input tdd_tx_valid, + // master/slave input dac_sync_in, output dac_sync_out, @@ -157,7 +159,7 @@ module axi_adrv9001_tx #( if (dac_rst == 1'b1) begin dac_valid_int <= 1'b0; end else begin - dac_valid_int <= (dac_rate_cnt == 16'd0) ? 1'b1 : 1'b0; + dac_valid_int <= (dac_rate_cnt == 16'd0) ? tdd_tx_valid : 1'b0; end end From 5dc1b6d7ccb0fc902b7cdefe11efb3f847d3ba82 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Mon, 24 Aug 2020 11:35:44 +0100 Subject: [PATCH 14/44] adrv9001/zcu102: Add TDD support --- projects/adrv9001/common/adrv9001_bd.tcl | 20 +++++++ projects/adrv9001/zcu102/system_top.v | 71 ++++++++++++++---------- 2 files changed, 63 insertions(+), 28 deletions(-) diff --git a/projects/adrv9001/common/adrv9001_bd.tcl b/projects/adrv9001/common/adrv9001_bd.tcl index 535c5ade300..a9f04586ac7 100644 --- a/projects/adrv9001/common/adrv9001_bd.tcl +++ b/projects/adrv9001/common/adrv9001_bd.tcl @@ -45,6 +45,16 @@ create_bd_port -dir O tx2_qdata_out_p create_bd_port -dir O tx2_strobe_out_n create_bd_port -dir O tx2_strobe_out_p +create_bd_port -dir O rx1_enable +create_bd_port -dir O rx2_enable +create_bd_port -dir O tx1_enable +create_bd_port -dir O tx2_enable + +create_bd_port -dir I gpio_rx1_enable_in +create_bd_port -dir I gpio_rx2_enable_in +create_bd_port -dir I gpio_tx1_enable_in +create_bd_port -dir I gpio_tx2_enable_in + # adrv9001 ad_ip_instance axi_adrv9001 axi_adrv9001 @@ -179,6 +189,16 @@ ad_connect tx2_qdata_out_p axi_adrv9001/tx2_qdata_out_p_qdata3 ad_connect tx2_strobe_out_n axi_adrv9001/tx2_strobe_out_n_NC ad_connect tx2_strobe_out_p axi_adrv9001/tx2_strobe_out_p_strobe_out +ad_connect rx1_enable axi_adrv9001/rx1_enable +ad_connect rx2_enable axi_adrv9001/rx2_enable +ad_connect tx1_enable axi_adrv9001/tx1_enable +ad_connect tx2_enable axi_adrv9001/tx2_enable + +ad_connect gpio_rx1_enable_in axi_adrv9001/gpio_rx1_enable_in +ad_connect gpio_rx2_enable_in axi_adrv9001/gpio_rx2_enable_in +ad_connect gpio_tx1_enable_in axi_adrv9001/gpio_tx1_enable_in +ad_connect gpio_tx2_enable_in axi_adrv9001/gpio_tx2_enable_in + # RX1_RX2 - CPACK - RX_DMA1 ad_connect axi_adrv9001/adc_1_rst util_adc_1_pack/reset ad_connect axi_adrv9001/adc_1_valid_i0 util_adc_1_pack/fifo_wr_en diff --git a/projects/adrv9001/zcu102/system_top.v b/projects/adrv9001/zcu102/system_top.v index f14decbfef1..ae6a6a1774e 100644 --- a/projects/adrv9001/zcu102/system_top.v +++ b/projects/adrv9001/zcu102/system_top.v @@ -78,7 +78,7 @@ module system_top ( input rx1_dclk_in_n, input rx1_dclk_in_p, - inout rx1_enable, + output rx1_enable, input rx1_idata_in_n, input rx1_idata_in_p, input rx1_qdata_in_n, @@ -88,7 +88,7 @@ module system_top ( input rx2_dclk_in_n, input rx2_dclk_in_p, - inout rx2_enable, + output rx2_enable, input rx2_idata_in_n, input rx2_idata_in_p, input rx2_qdata_in_n, @@ -100,7 +100,7 @@ module system_top ( output tx1_dclk_out_p, input tx1_dclk_in_n, input tx1_dclk_in_p, - inout tx1_enable, + output tx1_enable, output tx1_idata_out_n, output tx1_idata_out_p, output tx1_qdata_out_n, @@ -112,7 +112,7 @@ module system_top ( output tx2_dclk_out_p, input tx2_dclk_in_n, input tx2_dclk_in_p, - inout tx2_enable, + output tx2_enable, output tx2_idata_out_n, output tx2_idata_out_p, output tx2_qdata_out_n, @@ -132,6 +132,10 @@ module system_top ( wire [94:0] gpio_i; wire [94:0] gpio_o; wire [94:0] gpio_t; + wire gpio_rx1_enable_in; + wire gpio_rx2_enable_in; + wire gpio_tx1_enable_in; + wire gpio_tx2_enable_in; wire [ 2:0] spi_csn; wire fpga_ref_clk; @@ -167,36 +171,37 @@ module system_top ( assign platform_status = vadj_err; - ad_iobuf #(.DATA_WIDTH(20)) i_iobuf ( - .dio_t ({gpio_t[51:32]}), - .dio_i ({gpio_o[51:32]}), - .dio_o ({gpio_i[51:32]}), - .dio_p ({tx2_enable, - tx1_enable, - rx2_enable, - rx1_enable, - sm_fan_tach, - reset_trx, - mode, - gp_int, - dgpio_11, - dgpio_10, - dgpio_9, - dgpio_8, - dgpio_7, - dgpio_6, - dgpio_5, - dgpio_4, - dgpio_3, - dgpio_2, - dgpio_1, + ad_iobuf #(.DATA_WIDTH(16)) i_iobuf ( + .dio_t ({gpio_t[47:32]}), + .dio_i ({gpio_o[47:32]}), + .dio_o ({gpio_i[47:32]}), + .dio_p ({sm_fan_tach, // 47 + reset_trx, // 46 + mode, // 45 + gp_int, // 44 + dgpio_11, // 43 + dgpio_10, // 42 + dgpio_9, // 41 + dgpio_8, // 40 + dgpio_7, // 39 + dgpio_6, // 38 + dgpio_5, // 37 + dgpio_4, // 36 + dgpio_3, // 35 + dgpio_2, // 34 + dgpio_1, // 33 dgpio_0 })); // 32 + assign gpio_rx1_enable_in = gpio_o[48]; + assign gpio_rx2_enable_in = gpio_o[49]; + assign gpio_tx1_enable_in = gpio_o[50]; + assign gpio_tx2_enable_in = gpio_o[51]; + assign gpio_i[ 7: 0] = gpio_o[ 7: 0]; assign gpio_i[20: 8] = gpio_bd_i; assign gpio_bd_o = gpio_o[ 7: 0]; - assign gpio_i[54:52] = gpio_o[54:52]; + assign gpio_i[54:48] = gpio_o[54:48]; assign gpio_i[55] = vadj_err; assign gpio_i[94:56] = gpio_o[94:56]; assign gpio_i[31:21] = gpio_o[31:21]; @@ -249,6 +254,16 @@ module system_top ( .tx2_strobe_out_n (tx2_strobe_out_n), .tx2_strobe_out_p (tx2_strobe_out_p), + .rx1_enable (rx1_enable), + .rx2_enable (rx2_enable), + .tx1_enable (tx1_enable), + .tx2_enable (tx2_enable), + + .gpio_rx1_enable_in (gpio_rx1_enable_in), + .gpio_rx2_enable_in (gpio_rx2_enable_in), + .gpio_tx1_enable_in (gpio_tx1_enable_in), + .gpio_tx2_enable_in (gpio_tx2_enable_in), + .gpio_i (gpio_i), .gpio_o (gpio_o), .gpio_t (gpio_t), From ab070649024451d37a5fbfb164d2887194c9d9fa Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Mon, 24 Aug 2020 11:35:58 +0100 Subject: [PATCH 15/44] adrv9001/zed: Add TDD support --- projects/adrv9001/zed/system_top.v | 52 ++++++++++++++++++++++-------- 1 file changed, 38 insertions(+), 14 deletions(-) diff --git a/projects/adrv9001/zed/system_top.v b/projects/adrv9001/zed/system_top.v index 963aa534ea3..ce119ec2194 100644 --- a/projects/adrv9001/zed/system_top.v +++ b/projects/adrv9001/zed/system_top.v @@ -111,7 +111,7 @@ module system_top ( input rx1_dclk_in_n, input rx1_dclk_in_p, - inout rx1_enable, + output rx1_enable, input rx1_idata_in_n, input rx1_idata_in_p, input rx1_qdata_in_n, @@ -121,7 +121,7 @@ module system_top ( input rx2_dclk_in_n, input rx2_dclk_in_p, - inout rx2_enable, + output rx2_enable, input rx2_idata_in_n, input rx2_idata_in_p, input rx2_qdata_in_n, @@ -133,7 +133,7 @@ module system_top ( output tx1_dclk_out_p, input tx1_dclk_in_n, input tx1_dclk_in_p, - inout tx1_enable, + output tx1_enable, output tx1_idata_out_n, output tx1_idata_out_p, output tx1_qdata_out_n, @@ -145,7 +145,7 @@ module system_top ( output tx2_dclk_out_p, input tx2_dclk_in_n, input tx2_dclk_in_p, - inout tx2_enable, + output tx2_enable, output tx2_idata_out_n, output tx2_idata_out_p, output tx2_qdata_out_n, @@ -165,6 +165,10 @@ module system_top ( wire [63:0] gpio_i; wire [63:0] gpio_o; wire [63:0] gpio_t; + wire gpio_rx1_enable_in; + wire gpio_rx2_enable_in; + wire gpio_tx1_enable_in; + wire gpio_tx2_enable_in; wire [ 1:0] iic_mux_scl_i_s; wire [ 1:0] iic_mux_scl_o_s; wire iic_mux_scl_t_s; @@ -174,6 +178,10 @@ module system_top ( wire spi_clk_s; wire spi_en_s; wire spi_dio_s; + wire rx1_enable_s; + wire rx2_enable_s; + wire tx1_enable_s; + wire tx2_enable_s; // instantiations @@ -191,15 +199,11 @@ module system_top ( .dio_o(gpio_i[31:0]), .dio_p(gpio_bd)); - ad_iobuf #(.DATA_WIDTH(20)) i_iobuf ( - .dio_t (vadj_err ? {20{1'b1}} : gpio_t[51:32]), - .dio_i ({gpio_o[51:32]}), - .dio_o ({gpio_i[51:32]}), - .dio_p ({tx2_enable, // 51 - tx1_enable, // 50 - rx2_enable, // 49 - rx1_enable, // 48 - sm_fan_tach, // 47 + ad_iobuf #(.DATA_WIDTH(16)) i_iobuf ( + .dio_t (vadj_err ? {16{1'b1}} : gpio_t[47:32]), + .dio_i ({gpio_o[47:32]}), + .dio_o ({gpio_i[47:32]}), + .dio_p ({sm_fan_tach, // 47 reset_trx, // 46 mode, // 45 gp_int, // 44 @@ -216,7 +220,12 @@ module system_top ( dgpio_1, // 33 dgpio_0 })); // 32 - assign gpio_i[54:52] = gpio_o[54:52]; + assign gpio_rx1_enable_in = gpio_o[48]; + assign gpio_rx2_enable_in = gpio_o[49]; + assign gpio_tx1_enable_in = gpio_o[50]; + assign gpio_tx2_enable_in = gpio_o[51]; + + assign gpio_i[54:48] = gpio_o[54:48]; assign gpio_i[55] = vadj_err; assign gpio_i[63:56] = gpio_o[63:56]; @@ -323,6 +332,16 @@ module system_top ( .tx2_strobe_out_n (tx2_strobe_out_n), .tx2_strobe_out_p (tx2_strobe_out_p), + .rx1_enable (rx1_enable_s), + .rx2_enable (rx2_enable_s), + .tx1_enable (tx1_enable_s), + .tx2_enable (tx2_enable_s), + + .gpio_rx1_enable_in (gpio_rx1_enable_in), + .gpio_rx2_enable_in (gpio_rx2_enable_in), + .gpio_tx1_enable_in (gpio_tx1_enable_in), + .gpio_tx2_enable_in (gpio_tx2_enable_in), + .spi0_clk_i (1'b0), .spi0_clk_o (spi_clk_s), .spi0_csn_0_o (spi_en_s), @@ -347,6 +366,11 @@ module system_top ( assign spi_en = vadj_err ? 1'bz : spi_en_s; assign spi_dio = vadj_err ? 1'bz : spi_dio_s; + assign rx1_enable = vadj_err ? 1'bz : rx1_enable_s; + assign rx2_enable = vadj_err ? 1'bz : rx2_enable_s; + assign tx1_enable = vadj_err ? 1'bz : tx1_enable_s; + assign tx2_enable = vadj_err ? 1'bz : tx2_enable_s; + endmodule // *************************************************************************** From 846e2ccffa013565a726978402b5a926f28d2fc0 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Fri, 11 Sep 2020 13:12:55 +0100 Subject: [PATCH 16/44] axi_adrv9001: Export TDD mode --- library/axi_adrv9001/axi_adrv9001.v | 2 ++ library/axi_adrv9001/axi_adrv9001_core.v | 7 +++++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/library/axi_adrv9001/axi_adrv9001.v b/library/axi_adrv9001/axi_adrv9001.v index 5e0cba5b8d5..d4a4d68563c 100644 --- a/library/axi_adrv9001/axi_adrv9001.v +++ b/library/axi_adrv9001/axi_adrv9001.v @@ -155,6 +155,7 @@ module axi_adrv9001 #( // TDD interface input tdd_sync, + output tdd_sync_cntr, input gpio_rx1_enable_in, input gpio_rx2_enable_in, @@ -473,6 +474,7 @@ module axi_adrv9001 #( // TDD interface .tdd_sync (tdd_sync), + .tdd_sync_cntr (tdd_sync_cntr), .tdd_rx1_rf_en (tdd_rx1_rf_en), .tdd_tx1_rf_en (tdd_tx1_rf_en), .tdd_if1_mode (tdd_if1_mode), diff --git a/library/axi_adrv9001/axi_adrv9001_core.v b/library/axi_adrv9001/axi_adrv9001_core.v index 8f5d5615c44..92488d352fd 100644 --- a/library/axi_adrv9001/axi_adrv9001_core.v +++ b/library/axi_adrv9001/axi_adrv9001_core.v @@ -143,6 +143,7 @@ module axi_ad9001_core #( // TDD interface input tdd_sync, + output tdd_sync_cntr, output tdd_rx1_rf_en, output tdd_tx1_rf_en, @@ -536,7 +537,7 @@ module axi_ad9001_core #( .tdd_enabled (tdd_if1_mode), .tdd_status (8'h0), .tdd_sync (tdd_sync), - .tdd_sync_cntr (), + .tdd_sync_cntr (tdd_sync_cntr1), .tdd_tx_valid (tdd_tx1_valid), .tdd_rx_valid (tdd_rx1_valid), .up_rstn (up_rstn), @@ -562,7 +563,7 @@ module axi_ad9001_core #( .tdd_enabled (tdd_if2_mode_loc), .tdd_status (8'h0), .tdd_sync (tdd_sync), - .tdd_sync_cntr (), + .tdd_sync_cntr (tdd_sync_cntr2), .tdd_tx_valid (tdd_tx2_valid), .tdd_rx_valid (tdd_rx2_valid), .up_rstn (up_rstn), @@ -580,6 +581,8 @@ module axi_ad9001_core #( assign tdd_tx2_rf_en = tx1_r1_mode&rx1_r1_mode ? tdd_tx2_rf_en_loc : tdd_tx1_rf_en; assign tdd_if2_mode = tx1_r1_mode&rx1_r1_mode ? tdd_if2_mode_loc : tdd_if1_mode; + assign tdd_sync_cntr = tdd_sync_cntr1 | tdd_sync_cntr2; + end else begin assign up_wack_s[6] = 1'b0; assign up_rack_s[6] = 1'b0; From df7ff33b808506049197509d2756804fbb05c035 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Fri, 11 Sep 2020 13:13:23 +0100 Subject: [PATCH 17/44] adrv9001/common: Export TDD mode signal --- projects/adrv9001/common/adrv9001_bd.tcl | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/projects/adrv9001/common/adrv9001_bd.tcl b/projects/adrv9001/common/adrv9001_bd.tcl index a9f04586ac7..ef0e4149db3 100644 --- a/projects/adrv9001/common/adrv9001_bd.tcl +++ b/projects/adrv9001/common/adrv9001_bd.tcl @@ -55,6 +55,9 @@ create_bd_port -dir I gpio_rx2_enable_in create_bd_port -dir I gpio_tx1_enable_in create_bd_port -dir I gpio_tx2_enable_in +create_bd_port -dir I tdd_sync +create_bd_port -dir O tdd_sync_cntr + # adrv9001 ad_ip_instance axi_adrv9001 axi_adrv9001 @@ -199,6 +202,9 @@ ad_connect gpio_rx2_enable_in axi_adrv9001/gpio_rx2_enable_in ad_connect gpio_tx1_enable_in axi_adrv9001/gpio_tx1_enable_in ad_connect gpio_tx2_enable_in axi_adrv9001/gpio_tx2_enable_in +ad_connect tdd_sync axi_adrv9001/tdd_sync +ad_connect tdd_sync_cntr axi_adrv9001/tdd_sync_cntr + # RX1_RX2 - CPACK - RX_DMA1 ad_connect axi_adrv9001/adc_1_rst util_adc_1_pack/reset ad_connect axi_adrv9001/adc_1_valid_i0 util_adc_1_pack/fifo_wr_en From b897a29a47b96be6eb976cbc05338157515d2432 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Fri, 11 Sep 2020 13:14:33 +0100 Subject: [PATCH 18/44] adrv9001/zcu102: Add TDD sync to PMOD0 J55.1 --- projects/adrv9001/zcu102/system_constr.xdc | 2 ++ projects/adrv9001/zcu102/system_top.v | 20 ++++++++++++++++++-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/projects/adrv9001/zcu102/system_constr.xdc b/projects/adrv9001/zcu102/system_constr.xdc index 14dfdcb4d43..af18449fd21 100644 --- a/projects/adrv9001/zcu102/system_constr.xdc +++ b/projects/adrv9001/zcu102/system_constr.xdc @@ -42,3 +42,5 @@ set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS18} [get_ports platform set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports tx1_strobe_out_p] set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports tx2_idata_out_p] +set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS33} [get_ports tdd_sync] ;#PMOD0_0 J55.1 + diff --git a/projects/adrv9001/zcu102/system_top.v b/projects/adrv9001/zcu102/system_top.v index ae6a6a1774e..94716a2c7ae 100644 --- a/projects/adrv9001/zcu102/system_top.v +++ b/projects/adrv9001/zcu102/system_top.v @@ -122,7 +122,9 @@ module system_top ( inout sm_fan_tach, input vadj_err, - output platform_status + output platform_status, + + inout tdd_sync ); // internal registers reg [ 2:0] mcs_sync_m = 'd0; @@ -140,6 +142,9 @@ module system_top ( wire fpga_ref_clk; wire fpga_mcs_in; + wire tdd_sync_loc; + wire tdd_sync_i; + wire tdd_sync_cntr; // instantiations @@ -175,7 +180,7 @@ module system_top ( .dio_t ({gpio_t[47:32]}), .dio_i ({gpio_o[47:32]}), .dio_o ({gpio_i[47:32]}), - .dio_p ({sm_fan_tach, // 47 + .dio_p ({sm_fan_tach, // 47 reset_trx, // 46 mode, // 45 gp_int, // 44 @@ -208,6 +213,14 @@ module system_top ( assign spi_en = spi_csn[0]; + assign tdd_sync_loc = gpio_o[56]; + + // tdd_sync_loc - local sync signal from a GPIO or other source + // tdd_sync - external sync + + assign tdd_sync_i = tdd_sync_cntr ? tdd_sync_loc : tdd_sync; + assign tdd_sync = tdd_sync_cntr ? tdd_sync_loc : 1'bz; + system_wrapper i_system_wrapper ( .ref_clk (fpga_ref_clk), .mssi_sync (mssi_sync), @@ -264,6 +277,9 @@ module system_top ( .gpio_tx1_enable_in (gpio_tx1_enable_in), .gpio_tx2_enable_in (gpio_tx2_enable_in), + .tdd_sync (tdd_sync_i), + .tdd_sync_cntr (tdd_sync_cntr), + .gpio_i (gpio_i), .gpio_o (gpio_o), .gpio_t (gpio_t), From 6d397253032468657fa9a3d97331434fc8acaad5 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Thu, 24 Sep 2020 10:50:42 +0100 Subject: [PATCH 19/44] common/up_tdd_cntrl: Fix read data when read is idle --- library/common/up_tdd_cntrl.v | 2 ++ 1 file changed, 2 insertions(+) diff --git a/library/common/up_tdd_cntrl.v b/library/common/up_tdd_cntrl.v index 8715ac36f61..659cc892a5b 100644 --- a/library/common/up_tdd_cntrl.v +++ b/library/common/up_tdd_cntrl.v @@ -338,6 +338,8 @@ module up_tdd_cntrl #( 8'h3b: up_rdata <= { 8'h0, up_tdd_tx_dp_off_2}; default: up_rdata <= 32'h0; endcase + end else begin + up_rdata <= 32'h0; end end end From 72ddcc892d095a3abd95692fc3c003a5d10b92ec Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Thu, 24 Sep 2020 14:21:20 +0100 Subject: [PATCH 20/44] adrv9001/zed: Connect TDD sync to PMOD JA1 --- projects/adrv9001/zed/system_constr.xdc | 4 ++++ projects/adrv9001/zed/system_top.v | 17 ++++++++++++++++- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/projects/adrv9001/zed/system_constr.xdc b/projects/adrv9001/zed/system_constr.xdc index ab95e58ad63..f1b1407d428 100644 --- a/projects/adrv9001/zed/system_constr.xdc +++ b/projects/adrv9001/zed/system_constr.xdc @@ -57,3 +57,7 @@ set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS18} [get_ports gpio_bd[ set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports gpio_bd[29]] ; ## XADC-GIO2 set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18} [get_ports gpio_bd[30]] ; ## XADC-GIO3 set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports gpio_bd[31]] ; ## OTG-RESETN + +set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports tdd_sync] ; ## JA1.JA1 + + diff --git a/projects/adrv9001/zed/system_top.v b/projects/adrv9001/zed/system_top.v index ce119ec2194..0026b733f86 100644 --- a/projects/adrv9001/zed/system_top.v +++ b/projects/adrv9001/zed/system_top.v @@ -155,7 +155,9 @@ module system_top ( inout sm_fan_tach, input vadj_err, - output platform_status + output platform_status, + + inout tdd_sync ); // internal registers @@ -182,6 +184,9 @@ module system_top ( wire rx2_enable_s; wire tx1_enable_s; wire tx2_enable_s; + wire tdd_sync_loc; + wire tdd_sync_i; + wire tdd_sync_cntr; // instantiations @@ -229,6 +234,13 @@ module system_top ( assign gpio_i[55] = vadj_err; assign gpio_i[63:56] = gpio_o[63:56]; + assign tdd_sync_loc = gpio_o[56]; + + // tdd_sync_loc - local sync signal from a GPIO or other source + // tdd_sync - external sync + assign tdd_sync_i = tdd_sync_cntr ? tdd_sync_loc : tdd_sync; + assign tdd_sync = tdd_sync_cntr ? tdd_sync_loc : 1'bz; + ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_scl ( .dio_t ({iic_mux_scl_t_s,iic_mux_scl_t_s}), .dio_i (iic_mux_scl_o_s), @@ -342,6 +354,9 @@ module system_top ( .gpio_tx1_enable_in (gpio_tx1_enable_in), .gpio_tx2_enable_in (gpio_tx2_enable_in), + .tdd_sync (tdd_sync_i), + .tdd_sync_cntr (tdd_sync_cntr), + .spi0_clk_i (1'b0), .spi0_clk_o (spi_clk_s), .spi0_csn_0_o (spi_en_s), From 6b785e40906be3905ca709285a93be5f26c3864e Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Fri, 2 Oct 2020 10:38:06 +0100 Subject: [PATCH 21/44] ad_tdd_control: Fix rx/tx only behavior When tx_only disable rx_enable and vice-versa --- library/axi_adrv9001/axi_adrv9001_core.v | 6 +++--- library/common/ad_tdd_control.v | 16 ++++++++-------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/library/axi_adrv9001/axi_adrv9001_core.v b/library/axi_adrv9001/axi_adrv9001_core.v index 92488d352fd..fe75b25848a 100644 --- a/library/axi_adrv9001/axi_adrv9001_core.v +++ b/library/axi_adrv9001/axi_adrv9001_core.v @@ -577,9 +577,9 @@ module axi_ad9001_core #( .up_rdata (up_rdata_s[7]), .up_rack (up_rack_s[7])); - assign tdd_rx2_rf_en = tx1_r1_mode&rx1_r1_mode ? tdd_rx2_rf_en_loc : tdd_rx1_rf_en; - assign tdd_tx2_rf_en = tx1_r1_mode&rx1_r1_mode ? tdd_tx2_rf_en_loc : tdd_tx1_rf_en; - assign tdd_if2_mode = tx1_r1_mode&rx1_r1_mode ? tdd_if2_mode_loc : tdd_if1_mode; + assign tdd_rx2_rf_en = rx1_r1_mode ? tdd_rx2_rf_en_loc : tdd_rx1_rf_en; + assign tdd_tx2_rf_en = tx1_r1_mode ? tdd_tx2_rf_en_loc : tdd_tx1_rf_en; + assign tdd_if2_mode = tx1_r1_mode||rx1_r1_mode ? tdd_if2_mode_loc : tdd_if1_mode; assign tdd_sync_cntr = tdd_sync_cntr1 | tdd_sync_cntr2; diff --git a/library/common/ad_tdd_control.v b/library/common/ad_tdd_control.v index 7eabbd768bf..8b7fddbfd1f 100644 --- a/library/common/ad_tdd_control.v +++ b/library/common/ad_tdd_control.v @@ -781,8 +781,8 @@ module ad_tdd_control#( tdd_rx_rf_en <= 1'b0; end else if((tdd_cstate == ON) && ((counter_at_tdd_rx_on_1 == 1'b1) || (counter_at_tdd_rx_on_2 == 1'b1))) begin tdd_rx_rf_en <= 1'b1; - end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin - tdd_rx_rf_en <= tdd_rx_only; + end else if((tdd_cstate == ON) && (tdd_tx_only == 1'b1)) begin + tdd_rx_rf_en <= 1'b0; end else begin tdd_rx_rf_en <= tdd_rx_rf_en; end @@ -795,8 +795,8 @@ module ad_tdd_control#( tdd_tx_rf_en <= 1'b0; end else if((tdd_cstate == ON) && ((counter_at_tdd_tx_on_1 == 1'b1) || (counter_at_tdd_tx_on_2 == 1'b1))) begin tdd_tx_rf_en <= 1'b1; - end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin - tdd_tx_rf_en <= tdd_tx_only; + end else if((tdd_cstate == ON) && (tdd_rx_only == 1'b1)) begin + tdd_tx_rf_en <= 1'b0; end else begin tdd_tx_rf_en <= tdd_tx_rf_en; end @@ -809,8 +809,8 @@ module ad_tdd_control#( tdd_tx_dp_en <= 1'b0; end else if((tdd_cstate == ON) && ((counter_at_tdd_tx_dp_on_1 == 1'b1) || (counter_at_tdd_tx_dp_on_2 == 1'b1))) begin tdd_tx_dp_en <= 1'b1; - end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin - tdd_tx_dp_en <= tdd_tx_only; + end else if((tdd_cstate == ON) && (tdd_rx_only == 1'b1)) begin + tdd_tx_dp_en <= 1'b0; end else begin tdd_tx_dp_en <= tdd_tx_dp_en; end @@ -823,8 +823,8 @@ module ad_tdd_control#( tdd_rx_dp_en <= 1'b0; end else if((tdd_cstate == ON) && ((counter_at_tdd_rx_dp_on_1 == 1'b1) || (counter_at_tdd_rx_dp_on_2 == 1'b1))) begin tdd_rx_dp_en <= 1'b1; - end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin - tdd_rx_dp_en <= tdd_rx_only; + end else if((tdd_cstate == ON) && (tdd_tx_only == 1'b1)) begin + tdd_rx_dp_en <= 1'b0; end else begin tdd_rx_dp_en <= tdd_rx_dp_en; end From 2a0aff8b49039c790bf53d59180736a2794a2b8a Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Wed, 14 Oct 2020 11:11:12 +0100 Subject: [PATCH 22/44] ad_tdd_control: Avoid single pulses if tx_only or rx_only --- library/common/ad_tdd_control.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/library/common/ad_tdd_control.v b/library/common/ad_tdd_control.v index 8b7fddbfd1f..aa0958d9d51 100644 --- a/library/common/ad_tdd_control.v +++ b/library/common/ad_tdd_control.v @@ -779,10 +779,10 @@ module ad_tdd_control#( tdd_rx_rf_en <= 1'b0; end else if((tdd_cstate == OFF) || (counter_at_tdd_rx_off_1 == 1'b1) || (counter_at_tdd_rx_off_2 == 1'b1)) begin tdd_rx_rf_en <= 1'b0; - end else if((tdd_cstate == ON) && ((counter_at_tdd_rx_on_1 == 1'b1) || (counter_at_tdd_rx_on_2 == 1'b1))) begin - tdd_rx_rf_en <= 1'b1; end else if((tdd_cstate == ON) && (tdd_tx_only == 1'b1)) begin tdd_rx_rf_en <= 1'b0; + end else if((tdd_cstate == ON) && ((counter_at_tdd_rx_on_1 == 1'b1) || (counter_at_tdd_rx_on_2 == 1'b1))) begin + tdd_rx_rf_en <= 1'b1; end else begin tdd_rx_rf_en <= tdd_rx_rf_en; end @@ -793,10 +793,10 @@ module ad_tdd_control#( tdd_tx_rf_en <= 1'b0; end else if((tdd_cstate == OFF) || (counter_at_tdd_tx_off_1 == 1'b1) || (counter_at_tdd_tx_off_2 == 1'b1)) begin tdd_tx_rf_en <= 1'b0; - end else if((tdd_cstate == ON) && ((counter_at_tdd_tx_on_1 == 1'b1) || (counter_at_tdd_tx_on_2 == 1'b1))) begin - tdd_tx_rf_en <= 1'b1; end else if((tdd_cstate == ON) && (tdd_rx_only == 1'b1)) begin tdd_tx_rf_en <= 1'b0; + end else if((tdd_cstate == ON) && ((counter_at_tdd_tx_on_1 == 1'b1) || (counter_at_tdd_tx_on_2 == 1'b1))) begin + tdd_tx_rf_en <= 1'b1; end else begin tdd_tx_rf_en <= tdd_tx_rf_en; end @@ -807,10 +807,10 @@ module ad_tdd_control#( tdd_tx_dp_en <= 1'b0; end else if((tdd_cstate == OFF) || (counter_at_tdd_tx_dp_off_1 == 1'b1) || (counter_at_tdd_tx_dp_off_2 == 1'b1)) begin tdd_tx_dp_en <= 1'b0; - end else if((tdd_cstate == ON) && ((counter_at_tdd_tx_dp_on_1 == 1'b1) || (counter_at_tdd_tx_dp_on_2 == 1'b1))) begin - tdd_tx_dp_en <= 1'b1; end else if((tdd_cstate == ON) && (tdd_rx_only == 1'b1)) begin tdd_tx_dp_en <= 1'b0; + end else if((tdd_cstate == ON) && ((counter_at_tdd_tx_dp_on_1 == 1'b1) || (counter_at_tdd_tx_dp_on_2 == 1'b1))) begin + tdd_tx_dp_en <= 1'b1; end else begin tdd_tx_dp_en <= tdd_tx_dp_en; end @@ -821,10 +821,10 @@ module ad_tdd_control#( tdd_rx_dp_en <= 1'b0; end else if((tdd_cstate == OFF) || (counter_at_tdd_rx_dp_off_1 == 1'b1) || (counter_at_tdd_rx_dp_off_2 == 1'b1)) begin tdd_rx_dp_en <= 1'b0; - end else if((tdd_cstate == ON) && ((counter_at_tdd_rx_dp_on_1 == 1'b1) || (counter_at_tdd_rx_dp_on_2 == 1'b1))) begin - tdd_rx_dp_en <= 1'b1; end else if((tdd_cstate == ON) && (tdd_tx_only == 1'b1)) begin tdd_rx_dp_en <= 1'b0; + end else if((tdd_cstate == ON) && ((counter_at_tdd_rx_dp_on_1 == 1'b1) || (counter_at_tdd_rx_dp_on_2 == 1'b1))) begin + tdd_rx_dp_en <= 1'b1; end else begin tdd_rx_dp_en <= tdd_rx_dp_en; end From 998756b64095b01c0d36c6021747d55f8e05f802 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Fri, 18 Sep 2020 13:31:11 +0100 Subject: [PATCH 23/44] axi_adrv9001:axi_adrv9001_rx_channel: fix ramp signal checking --- library/axi_adrv9001/axi_adrv9001_rx_channel.v | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/library/axi_adrv9001/axi_adrv9001_rx_channel.v b/library/axi_adrv9001/axi_adrv9001_rx_channel.v index 076ea6848cc..e78ccd8c085 100644 --- a/library/axi_adrv9001/axi_adrv9001_rx_channel.v +++ b/library/axi_adrv9001/axi_adrv9001_rx_channel.v @@ -236,10 +236,12 @@ module axi_adrv9001_rx_channel #( // reference nibble ramp and full ramp generator always @(posedge adc_clk) begin - if (adc_pn_oos_s) begin - full_ramp_counter <= adc_data_in_s + 16'd1; - end else if (adc_valid_in_s) begin - full_ramp_counter <= full_ramp_counter + 16'd1; + if (adc_valid_in_s) begin + if (adc_pn_oos_s) begin + full_ramp_counter <= adc_data_in_s + 16'd1; + end else begin + full_ramp_counter <= full_ramp_counter + 16'd1; + end end end From e7b5a6199d512b0fd1dee394aa54766a2dab92e5 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Mon, 21 Sep 2020 10:43:57 +0100 Subject: [PATCH 24/44] ad_pnmon: Fix zero checking when valid not constant --- library/common/ad_pnmon.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/library/common/ad_pnmon.v b/library/common/ad_pnmon.v index 107c9ae5a75..6c051c2b24a 100644 --- a/library/common/ad_pnmon.v +++ b/library/common/ad_pnmon.v @@ -67,6 +67,7 @@ module ad_pnmon #( reg adc_pn_oos_int = 'd0; reg adc_pn_err_int = 'd0; reg [CNT_W-1:0] adc_pn_oos_count = 'd0; + reg adc_valid_zero_d = 'b0; // internal signals @@ -88,7 +89,7 @@ module ad_pnmon #( // but OOS_THRESHOLD consecutive zeros would assert out of sync. assign adc_valid_zero = ALLOW_ZERO_MASKING & adc_pattern_has_zero & ~adc_pn_oos_int & adc_pn_match_z_s; - assign adc_pn_err_s = ~(adc_pn_oos_int | adc_pn_match_s | adc_valid_zero); + assign adc_pn_err_s = ~(adc_pn_oos_int | adc_pn_match_s | adc_valid_zero_d); // pn oos and counters (16 to clear and set). @@ -100,6 +101,7 @@ module ad_pnmon #( adc_valid_d <= adc_valid_in; adc_pn_match_d <= adc_pn_match_d_s; adc_pn_match_z <= adc_pn_match_z_s; + adc_valid_zero_d <= adc_valid_zero; if (adc_valid_d == 1'b1) begin adc_pn_err_int <= adc_pn_err_s; if ((adc_pn_update_s == 1'b1) && (adc_pn_oos_count >= OOS_THRESHOLD-1)) begin From b27cc4fc93923c494b6e29acae0bf50f3b675f97 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Wed, 2 Dec 2020 06:37:11 +0000 Subject: [PATCH 25/44] axi_adrv9001: Use global clocks for divided down clock --- library/axi_adrv9001/adrv9001_rx.v | 6 +++++- library/axi_adrv9001/adrv9001_tx.v | 7 ++++++- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/library/axi_adrv9001/adrv9001_rx.v b/library/axi_adrv9001/adrv9001_rx.v index 0174ab6b103..a6059c17ed6 100644 --- a/library/axi_adrv9001/adrv9001_rx.v +++ b/library/axi_adrv9001/adrv9001_rx.v @@ -197,8 +197,12 @@ module adrv9001_rx #( .CLR (mssi_sync), .CE (1'b1), .I (clk_in_s), - .O (adc_clk_div)); + .O (adc_clk_div_s)); + BUFG I_bufg ( + .I (adc_clk_div_s), + .O (adc_clk_div) + ); assign ssi_rst = mssi_sync; end else begin diff --git a/library/axi_adrv9001/adrv9001_tx.v b/library/axi_adrv9001/adrv9001_tx.v index a5c131c9eb3..7da9587248d 100644 --- a/library/axi_adrv9001/adrv9001_tx.v +++ b/library/axi_adrv9001/adrv9001_tx.v @@ -186,7 +186,12 @@ module adrv9001_tx #( .CLR (mssi_sync), .CE (1'b1), .I (tx_dclk_in_s), - .O (dac_clk_div)); + .O (dac_clk_div_s)); + + BUFG I_bufg ( + .I (dac_clk_div_s), + .O (dac_clk_div) + ); assign ssi_rst = mssi_sync; From f4f5443c64887b13481633942a60d8943751c086 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Wed, 2 Dec 2020 13:50:03 +0000 Subject: [PATCH 26/44] axi_adrv9001: Add opt-in synthesis parameters --- library/axi_adrv9001/axi_adrv9001.v | 6 +++++ library/axi_adrv9001/axi_adrv9001_core.v | 15 +++++++++--- library/axi_adrv9001/axi_adrv9001_rx.v | 29 ++++++++++++++++++++++ library/axi_adrv9001/axi_adrv9001_tx.v | 31 ++++++++++++++++++++++++ 4 files changed, 77 insertions(+), 4 deletions(-) diff --git a/library/axi_adrv9001/axi_adrv9001.v b/library/axi_adrv9001/axi_adrv9001.v index d4a4d68563c..27a6c12912f 100644 --- a/library/axi_adrv9001/axi_adrv9001.v +++ b/library/axi_adrv9001/axi_adrv9001.v @@ -39,6 +39,9 @@ module axi_adrv9001 #( parameter ID = 0, parameter CMOS_LVDS_N = 0, parameter TDD_DISABLE = 0, + parameter DDS_DISABLE = 0, + parameter INDEPENDENT_1R1T_SUPPORT = 1, + parameter COMMON_2R2T_SUPPORT = 1, parameter IO_DELAY_GROUP = "dev_if_delay_group", parameter FPGA_TECHNOLOGY = 0, parameter FPGA_FAMILY = 0, @@ -376,6 +379,9 @@ module axi_adrv9001 #( .CMOS_LVDS_N (CMOS_LVDS_N), .DRP_WIDTH (DRP_WIDTH), .TDD_DISABLE (TDD_DISABLE), + .DDS_DISABLE (DDS_DISABLE), + .INDEPENDENT_1R1T_SUPPORT (INDEPENDENT_1R1T_SUPPORT), + .COMMON_2R2T_SUPPORT (COMMON_2R2T_SUPPORT), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_FAMILY (FPGA_FAMILY), .SPEED_GRADE (SPEED_GRADE), diff --git a/library/axi_adrv9001/axi_adrv9001_core.v b/library/axi_adrv9001/axi_adrv9001_core.v index fe75b25848a..3bdf48fe688 100644 --- a/library/axi_adrv9001/axi_adrv9001_core.v +++ b/library/axi_adrv9001/axi_adrv9001_core.v @@ -41,6 +41,9 @@ module axi_ad9001_core #( parameter NUM_LANES = 3, parameter DRP_WIDTH = 5, parameter TDD_DISABLE = 0, + parameter DDS_DISABLE = 0, + parameter INDEPENDENT_1R1T_SUPPORT = 1, + parameter COMMON_2R2T_SUPPORT = 1, parameter FPGA_TECHNOLOGY = 0, parameter FPGA_FAMILY = 0, parameter SPEED_GRADE = 0, @@ -262,10 +265,11 @@ module axi_ad9001_core #( axi_adrv9001_rx #( .ID (ID), + .ENABLED (1), .CMOS_LVDS_N (CMOS_LVDS_N), .COMMON_BASE_ADDR(6'h00), .CHANNEL_BASE_ADDR(6'h01), - .MODE_R1 (0), + .MODE_R1 (COMMON_2R2T_SUPPORT==0), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_FAMILY (FPGA_FAMILY), .SPEED_GRADE (SPEED_GRADE), @@ -321,6 +325,7 @@ module axi_ad9001_core #( axi_adrv9001_rx #( .ID (ID), + .ENABLED (INDEPENDENT_1R1T_SUPPORT), .CMOS_LVDS_N (CMOS_LVDS_N), .COMMON_BASE_ADDR(6'h04), .CHANNEL_BASE_ADDR(6'h05), @@ -374,15 +379,16 @@ module axi_ad9001_core #( axi_adrv9001_tx #( .ID (ID), + .ENABLED (1), .CMOS_LVDS_N (CMOS_LVDS_N), .COMMON_BASE_ADDR ('h08), .CHANNEL_BASE_ADDR ('h09), - .MODE_R1 (0), + .MODE_R1 (COMMON_2R2T_SUPPORT==0), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_FAMILY (FPGA_FAMILY), .SPEED_GRADE (SPEED_GRADE), .DEV_PACKAGE (DEV_PACKAGE), - .DDS_DISABLE (0), + .DDS_DISABLE (DDS_DISABLE), .IQCORRECTION_DISABLE (1), .DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), @@ -425,6 +431,7 @@ module axi_ad9001_core #( axi_adrv9001_tx #( .ID (ID), + .ENABLED (INDEPENDENT_1R1T_SUPPORT), .CMOS_LVDS_N (CMOS_LVDS_N), .COMMON_BASE_ADDR ('h10), .CHANNEL_BASE_ADDR ('h11), @@ -433,7 +440,7 @@ module axi_ad9001_core #( .FPGA_FAMILY (FPGA_FAMILY), .SPEED_GRADE (SPEED_GRADE), .DEV_PACKAGE (DEV_PACKAGE), - .DDS_DISABLE (0), + .DDS_DISABLE (DDS_DISABLE), .IQCORRECTION_DISABLE (1), .DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), diff --git a/library/axi_adrv9001/axi_adrv9001_rx.v b/library/axi_adrv9001/axi_adrv9001_rx.v index 548d5e11779..e17c41c1a18 100644 --- a/library/axi_adrv9001/axi_adrv9001_rx.v +++ b/library/axi_adrv9001/axi_adrv9001_rx.v @@ -37,6 +37,7 @@ module axi_adrv9001_rx #( parameter ID = 0, + parameter ENABLED = 1, parameter CMOS_LVDS_N = 0, parameter COMMON_BASE_ADDR = 'h00, parameter CHANNEL_BASE_ADDR = 'h01, @@ -101,6 +102,31 @@ module axi_adrv9001_rx #( output reg up_rack ); +generate +if (ENABLED == 0) begin : core_disabled + + assign adc_rst = 1'b0; + assign adc_single_lane = 1'b0; + assign adc_sdr_ddr_n = 1'b0; + assign adc_r1_mode = 1'b0; + assign adc_valid = 1'b0; + assign adc_enable_i0 = 1'b0; + assign adc_data_i0 = 16'b0; + assign adc_enable_q0 = 1'b0; + assign adc_data_q0 = 16'b0; + assign adc_enable_i1 = 1'b0; + assign adc_data_i1 = 16'b0; + assign adc_enable_q1 = 1'b0; + assign adc_data_q1 = 16'b0; + + always @(*) begin + up_wack = 1'b0; + up_rdata = 32'b0; + up_rack = 1'b0; + end + +end else begin : core_enabled + // configuration settings localparam CONFIG = (CMOS_LVDS_N * 128) + @@ -366,6 +392,9 @@ module axi_adrv9001_rx #( assign adc_single_lane = adc_num_lanes[0]; +end +endgenerate + endmodule // *************************************************************************** diff --git a/library/axi_adrv9001/axi_adrv9001_tx.v b/library/axi_adrv9001/axi_adrv9001_tx.v index 989b1016bd1..e1676b81e04 100644 --- a/library/axi_adrv9001/axi_adrv9001_tx.v +++ b/library/axi_adrv9001/axi_adrv9001_tx.v @@ -37,6 +37,7 @@ module axi_adrv9001_tx #( parameter ID = 0, + parameter ENABLED = 1, parameter CMOS_LVDS_N = 0, parameter COMMON_BASE_ADDR = 'h10, parameter CHANNEL_BASE_ADDR = 'h11, @@ -100,6 +101,33 @@ module axi_adrv9001_tx #( output reg [ 31:0] up_rdata, output reg up_rack ); +generate +if (ENABLED == 0) begin : core_disabled + + assign dac_rst = 1'b0; + assign dac_data_valid_A = 1'b0; + assign dac_data_i_A = 16'b0; + assign dac_data_q_A = 16'b0; + assign dac_data_valid_B = 1'b0; + assign dac_data_i_B = 16'b0; + assign dac_data_q_B = 16'b0; + assign dac_single_lane = 1'b0; + assign dac_sdr_ddr_n = 1'b0; + assign dac_r1_mode = 1'b0; + assign dac_sync_out = 1'b0; + assign dac_valid = 1'b0; + assign dac_enable_i0 = 1'b0; + assign dac_enable_q0 = 1'b0; + assign dac_enable_i1 = 1'b0; + assign dac_enable_q1 = 1'b0; + + always @(*) begin + up_wack = 1'b0; + up_rdata = 32'b0; + up_rack = 1'b0; + end + +end else begin : core_enabled // configuration settings @@ -377,6 +405,9 @@ module axi_adrv9001_tx #( assign dac_single_lane = dac_num_lanes[0]; +end +endgenerate + endmodule // *************************************************************************** From df2d527108d289a190c999986d33468039b72739 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Mon, 24 Aug 2020 15:25:52 +0100 Subject: [PATCH 27/44] adrv9001/common: Run DMAs @ 100MHz --- projects/adrv9001/common/adrv9001_bd.tcl | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/projects/adrv9001/common/adrv9001_bd.tcl b/projects/adrv9001/common/adrv9001_bd.tcl index ef0e4149db3..0812c16a75e 100644 --- a/projects/adrv9001/common/adrv9001_bd.tcl +++ b/projects/adrv9001/common/adrv9001_bd.tcl @@ -269,16 +269,16 @@ ad_cpu_interconnect 0x44A60000 axi_adrv9001_tx2_dma # memory inteconnect -ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1 -ad_mem_hp1_interconnect $sys_dma_clk axi_adrv9001_rx1_dma/m_dest_axi -ad_mem_hp1_interconnect $sys_dma_clk axi_adrv9001_rx2_dma/m_dest_axi -ad_mem_hp1_interconnect $sys_dma_clk axi_adrv9001_tx1_dma/m_src_axi -ad_mem_hp1_interconnect $sys_dma_clk axi_adrv9001_tx2_dma/m_src_axi - -ad_connect $sys_dma_resetn axi_adrv9001_rx1_dma/m_dest_axi_aresetn -ad_connect $sys_dma_resetn axi_adrv9001_rx2_dma/m_dest_axi_aresetn -ad_connect $sys_dma_resetn axi_adrv9001_tx1_dma/m_src_axi_aresetn -ad_connect $sys_dma_resetn axi_adrv9001_tx2_dma/m_src_axi_aresetn +ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_rx1_dma/m_dest_axi +ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_rx2_dma/m_dest_axi +ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_tx1_dma/m_src_axi +ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_tx2_dma/m_src_axi + +ad_connect $sys_cpu_resetn axi_adrv9001_rx1_dma/m_dest_axi_aresetn +ad_connect $sys_cpu_resetn axi_adrv9001_rx2_dma/m_dest_axi_aresetn +ad_connect $sys_cpu_resetn axi_adrv9001_tx1_dma/m_src_axi_aresetn +ad_connect $sys_cpu_resetn axi_adrv9001_tx2_dma/m_src_axi_aresetn # interrupts ad_cpu_interrupt ps-13 mb-12 axi_adrv9001_rx1_dma/irq From b24bbcb72675e3748c0e36b051d90b6bdd881c32 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Mon, 24 Aug 2020 15:26:55 +0100 Subject: [PATCH 28/44] adrv9001/zcu102: Run postRoutePhysOpt to close Rx1 to Rx2 path timing --- projects/adrv9001/zcu102/system_bd.tcl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/projects/adrv9001/zcu102/system_bd.tcl b/projects/adrv9001/zcu102/system_bd.tcl index f573b5d1e43..0d34f3183a9 100644 --- a/projects/adrv9001/zcu102/system_bd.tcl +++ b/projects/adrv9001/zcu102/system_bd.tcl @@ -11,3 +11,5 @@ ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 set sys_cstring "CMOS_LVDS_N=${ad_project_params(CMOS_LVDS_N)}" sysid_gen_sys_init_file $sys_cstring +set_property strategy Flow_RunPostRoutePhysOpt [get_runs impl_1] + From c549cfb4b9ee9182ea6ce24d1940991b8e38c28f Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Mon, 24 Aug 2020 11:33:59 +0100 Subject: [PATCH 29/44] library/common/up_tdd_cntrl: Make address generic --- library/common/up_tdd_cntrl.v | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/library/common/up_tdd_cntrl.v b/library/common/up_tdd_cntrl.v index 659cc892a5b..d9bf09ae547 100644 --- a/library/common/up_tdd_cntrl.v +++ b/library/common/up_tdd_cntrl.v @@ -36,7 +36,9 @@ module up_tdd_cntrl #( - parameter ID = 0) ( + parameter ID = 0, + parameter BASE_ADDRESS = 6'h20 +) ( input clk, input rst, @@ -145,8 +147,8 @@ module up_tdd_cntrl #( // decode block select - assign up_wreq_s = (up_waddr[13:8] == 6'h20) ? up_wreq : 1'b0; - assign up_rreq_s = (up_raddr[13:8] == 6'h20) ? up_rreq : 1'b0; + assign up_wreq_s = (up_waddr[13:8] == BASE_ADDRESS[5:0]) ? up_wreq : 1'b0; + assign up_rreq_s = (up_raddr[13:8] == BASE_ADDRESS[5:0]) ? up_rreq : 1'b0; // processor write interface From 0d02e1ea541af5a0991e45ccf9beacada6a76522 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Tue, 5 Jan 2021 07:19:01 +0000 Subject: [PATCH 30/44] axi_adrv9001:rx:phy: do not generate valid while in reset --- library/axi_adrv9001/adrv9001_rx.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/axi_adrv9001/adrv9001_rx.v b/library/axi_adrv9001/adrv9001_rx.v index a6059c17ed6..9ea192a374d 100644 --- a/library/axi_adrv9001/adrv9001_rx.v +++ b/library/axi_adrv9001/adrv9001_rx.v @@ -269,6 +269,6 @@ module adrv9001_rx #( endgenerate assign adc_clk = adc_clk_in_fast; - assign adc_valid = 1'b1; + assign adc_valid = ~adc_rst; endmodule From 93ea52a46ed3aa54c69dca47d85103b9aa7f7e14 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Tue, 5 Jan 2021 16:20:40 +0000 Subject: [PATCH 31/44] axi_adrv9001:rx: Add reset to link layer Fix random valid signals after resets on the Rx interface. --- library/axi_adrv9001/adrv9001_aligner4.v | 9 +++++++-- library/axi_adrv9001/adrv9001_aligner8.v | 9 +++++++-- library/axi_adrv9001/adrv9001_pack.v | 5 ++++- library/axi_adrv9001/adrv9001_rx_link.v | 18 ++++++++++++++++++ library/axi_adrv9001/axi_adrv9001_if.v | 2 ++ 5 files changed, 38 insertions(+), 5 deletions(-) diff --git a/library/axi_adrv9001/adrv9001_aligner4.v b/library/axi_adrv9001/adrv9001_aligner4.v index 33b4cc15882..515fb33ae41 100644 --- a/library/axi_adrv9001/adrv9001_aligner4.v +++ b/library/axi_adrv9001/adrv9001_aligner4.v @@ -37,6 +37,7 @@ module adrv9001_aligner4 ( input clk, + input rst, input [3:0] idata, input ivalid, input [3:0] strobe, @@ -48,7 +49,9 @@ module adrv9001_aligner4 ( reg ivalid_d = 'b0; always @(posedge clk) begin - if (ivalid) begin + if (rst) begin + idata_d <= 'h0; + end else if (ivalid) begin idata_d <= idata; end ivalid_d <= ivalid; @@ -56,7 +59,9 @@ module adrv9001_aligner4 ( reg [1:0] phase = 'h0; always @(posedge clk) begin - if (ivalid) begin + if (rst) begin + phase <= 0; + end else if (ivalid) begin if ((strobe != 'b1111) && (strobe != 'b0000)) begin casex (strobe) 'b1xxx : phase <= 0; diff --git a/library/axi_adrv9001/adrv9001_aligner8.v b/library/axi_adrv9001/adrv9001_aligner8.v index 43a90c889ef..26b21926f94 100644 --- a/library/axi_adrv9001/adrv9001_aligner8.v +++ b/library/axi_adrv9001/adrv9001_aligner8.v @@ -37,6 +37,7 @@ module adrv9001_aligner8 ( input clk, + input rst, input [7:0] idata, input ivalid, input [7:0] strobe, @@ -48,7 +49,9 @@ module adrv9001_aligner8 ( reg ivalid_d = 'b0; always @(posedge clk) begin - if (ivalid) begin + if (rst) begin + idata_d <= 'h0; + end else if (ivalid) begin idata_d <= idata; end ivalid_d <= ivalid; @@ -56,7 +59,9 @@ module adrv9001_aligner8 ( reg [2:0] phase = 'h0; always @(posedge clk) begin - if (ivalid) begin + if (rst) begin + phase <= 0; + end if (ivalid) begin if ((strobe != 'b1111_1111) && (strobe != 'b0000_0000)) begin casex (strobe) 'b1xxx_xxxx : phase <= 0; diff --git a/library/axi_adrv9001/adrv9001_pack.v b/library/axi_adrv9001/adrv9001_pack.v index f038f906d22..410178fbb26 100644 --- a/library/axi_adrv9001/adrv9001_pack.v +++ b/library/axi_adrv9001/adrv9001_pack.v @@ -53,6 +53,7 @@ module adrv9001_pack #( parameter WIDTH = 8 )( input clk, // Input clock + input rst, input sof, // Start of frame indicator marking the MS Beat input [WIDTH-1:0] idata, // Input data beat input ivalid, // Input data qualifier @@ -73,7 +74,9 @@ module adrv9001_pack #( // Use sof_d[2] for frame size of 4 beats // Use sof_d[4,6] for frame size of 8 beats always @(posedge clk) begin - if (ivalid) begin + if (rst) begin + sof_d <= 7'b0; + end else if (ivalid) begin sof_d <= {sof_d[5:0],sof}; end if (ivalid &(sof_d[0] | sof_d[2] | sof_d[4] | sof_d[6])) begin diff --git a/library/axi_adrv9001/adrv9001_rx_link.v b/library/axi_adrv9001/adrv9001_rx_link.v index 15616c60bc9..c79f217926f 100644 --- a/library/axi_adrv9001/adrv9001_rx_link.v +++ b/library/axi_adrv9001/adrv9001_rx_link.v @@ -39,6 +39,7 @@ module adrv9001_rx_link #( parameter CMOS_LVDS_N = 0 ) ( + input adc_rst, input adc_clk_div, input [7:0] adc_data_0, input [7:0] adc_data_1, @@ -100,6 +101,7 @@ module adrv9001_rx_link #( adrv9001_aligner4 i_rx_aligner4_0 ( .clk (adc_clk_div), + .rst (adc_rst), .idata (sdr_data_0), .ivalid (adc_valid), .strobe (sdr_data_strobe), @@ -108,6 +110,7 @@ module adrv9001_rx_link #( adrv9001_aligner4 i_rx_aligner4_1 ( .clk (adc_clk_div), + .rst (adc_rst), .idata (sdr_data_1), .ivalid (adc_valid), .strobe (sdr_data_strobe), @@ -116,6 +119,7 @@ module adrv9001_rx_link #( adrv9001_aligner4 i_rx_aligner4_2 ( .clk (adc_clk_div), + .rst (adc_rst), .idata (sdr_data_2), .ivalid (adc_valid), .strobe (sdr_data_strobe), @@ -124,6 +128,7 @@ module adrv9001_rx_link #( adrv9001_aligner4 i_rx_aligner4_3 ( .clk (adc_clk_div), + .rst (adc_rst), .idata (sdr_data_3), .ivalid (adc_valid), .strobe (sdr_data_strobe), @@ -132,6 +137,7 @@ module adrv9001_rx_link #( adrv9001_aligner4 i_rx_aligner4_strobe ( .clk (adc_clk_div), + .rst (adc_rst), .idata (sdr_data_strobe), .ivalid (adc_valid), .strobe (sdr_data_strobe), @@ -143,6 +149,7 @@ module adrv9001_rx_link #( .WIDTH(4) ) i_rx_pack_4_to_8_0 ( .clk (adc_clk_div), + .rst (adc_rst), .idata (sdr_data_0_aligned), .ivalid (aligner4_ovalid), .sof (sdr_data_strobe_aligned[3]), @@ -154,6 +161,7 @@ module adrv9001_rx_link #( .WIDTH(4) ) i_rx_pack_4_to_8_1 ( .clk (adc_clk_div), + .rst (adc_rst), .idata (sdr_data_1_aligned), .ivalid (aligner4_ovalid), .sof (sdr_data_strobe_aligned[3]), @@ -176,6 +184,7 @@ module adrv9001_rx_link #( .WIDTH(4) ) i_rx_pack_4_to_8_3 ( .clk (adc_clk_div), + .rst (adc_rst), .idata (sdr_data_3_aligned), .ivalid (aligner4_ovalid), .sof (sdr_data_strobe_aligned[3]), @@ -187,6 +196,7 @@ module adrv9001_rx_link #( .WIDTH(4) ) i_rx_pack_4_to_8_strobe ( .clk (adc_clk_div), + .rst (adc_rst), .idata (sdr_data_strobe_aligned), .ivalid (aligner4_ovalid), .sof (sdr_data_strobe_aligned[3]), @@ -229,6 +239,7 @@ module adrv9001_rx_link #( adrv9001_aligner8 i_rx_aligner8_0( .clk (adc_clk_div), + .rst (adc_rst), .idata (data_0), .ivalid (data_valid), .strobe (data_strobe), @@ -238,6 +249,7 @@ module adrv9001_rx_link #( adrv9001_aligner8 i_rx_aligner8_1( .clk (adc_clk_div), + .rst (adc_rst), .ivalid (data_valid), .idata (data_1), .strobe (data_strobe), @@ -248,6 +260,7 @@ module adrv9001_rx_link #( generate if (CMOS_LVDS_N) begin : cmos_aligner8 adrv9001_aligner8 i_rx_aligner8_2( .clk (adc_clk_div), + .rst (adc_rst), .idata (data_2), .ivalid (data_valid), .strobe (data_strobe), @@ -255,6 +268,7 @@ module adrv9001_rx_link #( ); adrv9001_aligner8 i_rx_aligner8_3( .clk (adc_clk_div), + .rst (adc_rst), .idata (data_3), .ivalid (data_valid), .strobe (data_strobe), @@ -265,6 +279,7 @@ module adrv9001_rx_link #( adrv9001_aligner8 i_rx_strobe_aligner( .clk (adc_clk_div), + .rst (adc_rst), .idata (data_strobe), .ivalid (data_valid), .strobe (data_strobe), @@ -275,6 +290,7 @@ module adrv9001_rx_link #( .WIDTH (8) ) i_rx_pack_8_to_16_0 ( .clk (adc_clk_div), + .rst (adc_rst), .ivalid (rx_data8_0_aligned_valid), .idata (rx_data8_0_aligned), .sof (rx_data8_strobe_aligned[7]), @@ -287,6 +303,7 @@ module adrv9001_rx_link #( .WIDTH (8) ) i_rx_pack_8_to_16_1 ( .clk (adc_clk_div), + .rst (adc_rst), .ivalid (rx_data8_1_aligned_valid), .idata (rx_data8_1_aligned), .sof (rx_data8_strobe_aligned[7]), @@ -298,6 +315,7 @@ module adrv9001_rx_link #( .WIDTH (16) ) i_rx_pack_16_to_32_0 ( .clk (adc_clk_div), + .rst (adc_rst), .ivalid (rx_data16_0_packed_valid), .idata (rx_data16_0_packed), .sof (rx_data16_0_packed_osof), diff --git a/library/axi_adrv9001/axi_adrv9001_if.v b/library/axi_adrv9001/axi_adrv9001_if.v index ca67a6a54fa..83d51d113c4 100644 --- a/library/axi_adrv9001/axi_adrv9001_if.v +++ b/library/axi_adrv9001/axi_adrv9001_if.v @@ -232,6 +232,7 @@ module axi_adrv9001_if #( adrv9001_rx_link #( .CMOS_LVDS_N (CMOS_LVDS_N) ) i_rx_1_link ( + .adc_rst (rx1_rst), .adc_clk_div (adc_1_clk_div), .adc_data_0 (adc_1_data_0), .adc_data_1 (adc_1_data_1), @@ -292,6 +293,7 @@ module axi_adrv9001_if #( adrv9001_rx_link #( .CMOS_LVDS_N (CMOS_LVDS_N) ) i_rx_2_link ( + .adc_rst (rx2_rst), .adc_clk_div (adc_2_clk_div), .adc_data_0 (adc_2_data_0), .adc_data_1 (adc_2_data_1), From 4ef156c70134ff51467551b1ba718845f734f222 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Tue, 9 Feb 2021 08:34:18 +0000 Subject: [PATCH 32/44] axi_adrv9001: Add status bit for Tx clocking If Tx source synchronous clock is not routed through clock capable pins the interface and driving logic must run on the Rx interface clock. This introduces a dependency, Rx interface must be bring up before the Tx. In this mode a Tx only operation is not possible. This is done through a synthesis parameter. Expose this parameter to the software so it can query if the limitations exists in the implementation. --- library/axi_adrv9001/axi_adrv9001.v | 1 + library/axi_adrv9001/axi_adrv9001_core.v | 3 +++ library/axi_adrv9001/axi_adrv9001_tx.v | 4 +++- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/library/axi_adrv9001/axi_adrv9001.v b/library/axi_adrv9001/axi_adrv9001.v index 27a6c12912f..9060ac2f241 100644 --- a/library/axi_adrv9001/axi_adrv9001.v +++ b/library/axi_adrv9001/axi_adrv9001.v @@ -377,6 +377,7 @@ module axi_adrv9001 #( .ID (ID), .NUM_LANES (NUM_LANES), .CMOS_LVDS_N (CMOS_LVDS_N), + .USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX), .DRP_WIDTH (DRP_WIDTH), .TDD_DISABLE (TDD_DISABLE), .DDS_DISABLE (DDS_DISABLE), diff --git a/library/axi_adrv9001/axi_adrv9001_core.v b/library/axi_adrv9001/axi_adrv9001_core.v index 3bdf48fe688..8d8e50ed3a0 100644 --- a/library/axi_adrv9001/axi_adrv9001_core.v +++ b/library/axi_adrv9001/axi_adrv9001_core.v @@ -38,6 +38,7 @@ module axi_ad9001_core #( parameter ID = 0, parameter CMOS_LVDS_N = 0, + parameter USE_RX_CLK_FOR_TX = 0, parameter NUM_LANES = 3, parameter DRP_WIDTH = 5, parameter TDD_DISABLE = 0, @@ -381,6 +382,7 @@ module axi_ad9001_core #( .ID (ID), .ENABLED (1), .CMOS_LVDS_N (CMOS_LVDS_N), + .USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX), .COMMON_BASE_ADDR ('h08), .CHANNEL_BASE_ADDR ('h09), .MODE_R1 (COMMON_2R2T_SUPPORT==0), @@ -433,6 +435,7 @@ module axi_ad9001_core #( .ID (ID), .ENABLED (INDEPENDENT_1R1T_SUPPORT), .CMOS_LVDS_N (CMOS_LVDS_N), + .USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX), .COMMON_BASE_ADDR ('h10), .CHANNEL_BASE_ADDR ('h11), .MODE_R1 (1), diff --git a/library/axi_adrv9001/axi_adrv9001_tx.v b/library/axi_adrv9001/axi_adrv9001_tx.v index e1676b81e04..132847b63dc 100644 --- a/library/axi_adrv9001/axi_adrv9001_tx.v +++ b/library/axi_adrv9001/axi_adrv9001_tx.v @@ -39,6 +39,7 @@ module axi_adrv9001_tx #( parameter ID = 0, parameter ENABLED = 1, parameter CMOS_LVDS_N = 0, + parameter USE_RX_CLK_FOR_TX = 0, parameter COMMON_BASE_ADDR = 'h10, parameter CHANNEL_BASE_ADDR = 'h11, parameter MODE_R1 = 1, @@ -131,7 +132,8 @@ end else begin : core_enabled // configuration settings - localparam CONFIG = (CMOS_LVDS_N * 128) + + localparam CONFIG = (USE_RX_CLK_FOR_TX * 1024) + + (CMOS_LVDS_N * 128) + (MODE_R1 * 16) + (DDS_DISABLE * 64) + (IQCORRECTION_DISABLE * 1); From a76bd13a36760ca5d81d6f72e791d90eafbe8511 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Tue, 5 Jan 2021 07:17:00 +0000 Subject: [PATCH 33/44] axi_adrv9001: Let gate signals have initial value, useful for simulation --- library/axi_adrv9001/axi_adrv9001_tdd.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/library/axi_adrv9001/axi_adrv9001_tdd.v b/library/axi_adrv9001/axi_adrv9001_tdd.v index fe5f5d90507..a91d01f9663 100644 --- a/library/axi_adrv9001/axi_adrv9001_tdd.v +++ b/library/axi_adrv9001/axi_adrv9001_tdd.v @@ -64,8 +64,8 @@ module axi_adrv9001_tdd #( // tx/rx data flow control - output reg tdd_tx_valid, - output reg tdd_rx_valid, + output reg tdd_tx_valid = 1'b1, + output reg tdd_rx_valid = 1'b1, // bus interface From 400be0456176ebff87a74abe4251bf1c2d63a806 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Tue, 5 Jan 2021 07:18:16 +0000 Subject: [PATCH 34/44] axi_adrv9001: rx: calculate ramp value based on received value --- library/axi_adrv9001/axi_adrv9001_rx_channel.v | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/library/axi_adrv9001/axi_adrv9001_rx_channel.v b/library/axi_adrv9001/axi_adrv9001_rx_channel.v index e78ccd8c085..dfc34dea3ee 100644 --- a/library/axi_adrv9001/axi_adrv9001_rx_channel.v +++ b/library/axi_adrv9001/axi_adrv9001_rx_channel.v @@ -235,13 +235,10 @@ module axi_adrv9001_rx_channel #( ); // reference nibble ramp and full ramp generator + // next value is always the currently received value incremented always @(posedge adc_clk) begin if (adc_valid_in_s) begin - if (adc_pn_oos_s) begin - full_ramp_counter <= adc_data_in_s + 16'd1; - end else begin - full_ramp_counter <= full_ramp_counter + 16'd1; - end + full_ramp_counter <= adc_data_in_s + 16'd1; end end From 3f22cd3a08db6e1af54eaa9517e58f46661ca440 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Fri, 12 Feb 2021 13:11:53 +0000 Subject: [PATCH 35/44] axi_adrv9001: Fix channel 3 for Tx1 in DMA mode --- library/axi_adrv9001/axi_adrv9001_tx.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/axi_adrv9001/axi_adrv9001_tx.v b/library/axi_adrv9001/axi_adrv9001_tx.v index 132847b63dc..af32821e299 100644 --- a/library/axi_adrv9001/axi_adrv9001_tx.v +++ b/library/axi_adrv9001/axi_adrv9001_tx.v @@ -329,7 +329,7 @@ end else begin : core_enabled .dac_clk (dac_clk), .dac_rst (dac_rst), .dac_data_in_req (), - .dac_data_in (dac_data_q0), + .dac_data_in (dac_data_q1), .dac_data_out_req (dac_data_valid_B), .dac_data_out (dac_data_q_B[15:0]), .dac_data_iq_in (dac_data_iq_i1_s), From 7c86b9f84f75d6eaad0ef29a31e74b6f6f37c447 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Mon, 15 Feb 2021 09:16:58 +0000 Subject: [PATCH 36/44] fmcomms2/zed: Disable unused TDD to save space and timing --- projects/fmcomms2/zed/system_bd.tcl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/projects/fmcomms2/zed/system_bd.tcl b/projects/fmcomms2/zed/system_bd.tcl index 9574d9b431c..a86cb934444 100644 --- a/projects/fmcomms2/zed/system_bd.tcl +++ b/projects/fmcomms2/zed/system_bd.tcl @@ -11,3 +11,5 @@ sysid_gen_sys_init_file ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 23 +ad_ip_parameter axi_ad9361 CONFIG.TDD_DISABLE 1 + From f45d5d949c5e7516251dfc7a2026978813562da7 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Tue, 16 Feb 2021 12:50:09 +0000 Subject: [PATCH 37/44] adrv9001/zcu102/cmos: Loosen up clock skew constraints to match LVDS settings Set the same inter clock skew characteristics as used in LVDS mode. The physical lanes/routes are common on both modes. --- projects/adrv9001/zcu102/cmos_constr.xdc | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/projects/adrv9001/zcu102/cmos_constr.xdc b/projects/adrv9001/zcu102/cmos_constr.xdc index 317e04286ea..84825bb7458 100644 --- a/projects/adrv9001/zcu102/cmos_constr.xdc +++ b/projects/adrv9001/zcu102/cmos_constr.xdc @@ -47,8 +47,10 @@ create_clock -name rx2_dclk_out -period 12.5 [get_ports rx2_dclk_in_p] create_clock -name tx1_dclk_out -period 12.5 [get_ports tx1_dclk_in_p] create_clock -name tx2_dclk_out -period 12.5 [get_ports tx2_dclk_in_p] -set_clock_latency -source -early 2 [get_clocks rx1_dclk_out] -set_clock_latency -source -early 2 [get_clocks rx2_dclk_out] +set_clock_latency -source -early -0.25 [get_clocks rx1_dclk_out] +set_clock_latency -source -early -0.25 [get_clocks rx2_dclk_out] + +set_clock_latency -source -late 0.25 [get_clocks rx1_dclk_out] +set_clock_latency -source -late 0.25 [get_clocks rx2_dclk_out] + -set_clock_latency -source -late 5 [get_clocks rx1_dclk_out] -set_clock_latency -source -late 5 [get_clocks rx2_dclk_out] From 697a1427d6a97317505935691e3b6c2f423dd598 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Wed, 17 Feb 2021 10:00:43 +0000 Subject: [PATCH 38/44] axi_ad9361: Update constraints in case TDD is disabled --- library/axi_ad9361/axi_ad9361_constr.xdc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/axi_ad9361/axi_ad9361_constr.xdc b/library/axi_ad9361/axi_ad9361_constr.xdc index 5173be8bf08..334f0481db9 100644 --- a/library/axi_ad9361/axi_ad9361_constr.xdc +++ b/library/axi_ad9361/axi_ad9361_constr.xdc @@ -6,5 +6,5 @@ set_property ASYNC_REG TRUE \ set_false_path -from [get_cells -hier -filter {name =~ *up_enable_int_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *enable_up_m1_reg && IS_SEQUENTIAL}] set_false_path -from [get_cells -hier -filter {name =~ *up_txnrx_int_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *txnrx_up_m1_reg && IS_SEQUENTIAL}] -set_false_path -to [get_cells -hier -filter {name =~ *tdd_sync_d1_reg && IS_SEQUENTIAL}] +set_false_path -quiet -to [get_cells -quiet -hier -filter {name =~ *tdd_sync_d1_reg && IS_SEQUENTIAL}] From 44b80bd335a736a831a4da287e66c522060a11e3 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Wed, 17 Feb 2021 10:02:39 +0000 Subject: [PATCH 39/44] axi_adrv9001: Double sync control lines between interface 1 and 2 --- library/axi_adrv9001/axi_adrv9001_constr.sdc | 7 ++++ library/axi_adrv9001/axi_adrv9001_constr.xdc | 10 ++++++ library/axi_adrv9001/axi_adrv9001_core.v | 34 +++++++++++++++----- library/axi_adrv9001/axi_adrv9001_hw.tcl | 2 ++ 4 files changed, 45 insertions(+), 8 deletions(-) diff --git a/library/axi_adrv9001/axi_adrv9001_constr.sdc b/library/axi_adrv9001/axi_adrv9001_constr.sdc index 77095d9690b..9fe867a687c 100644 --- a/library/axi_adrv9001/axi_adrv9001_constr.sdc +++ b/library/axi_adrv9001/axi_adrv9001_constr.sdc @@ -1,6 +1,13 @@ +set script_dir [file dirname [info script]] + +source "$script_dir/util_cdc_constr.tcl" set_false_path -from [get_registers *i_dev_if|up_enable_int*] -to [get_registers *i_dev_if|enable_up_m1*] set_false_path -from [get_registers *i_dev_if|up_txnrx_int*] -to [get_registers *i_dev_if|txnrx_up_m1*] set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_xfer_toggle*] -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_state_m1*] set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_toggle*] -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_xfer_toggle_m1*] set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_data*] -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_data_cntrl*] + +util_cdc_sync_bits_constr {*|sync_bits:i_rx1_ctrl_sync} +util_cdc_sync_bits_constr {*|sync_bits:i_tx1_ctrl_sync} + diff --git a/library/axi_adrv9001/axi_adrv9001_constr.xdc b/library/axi_adrv9001/axi_adrv9001_constr.xdc index 1eddedaa6c4..8350c805c3e 100644 --- a/library/axi_adrv9001/axi_adrv9001_constr.xdc +++ b/library/axi_adrv9001/axi_adrv9001_constr.xdc @@ -3,3 +3,13 @@ set_false_path -quiet -from [get_cells -quiet -hier *out_toggle_d1_reg* -filter set_false_path -through [get_pins -hier *i_idelay/CNTVALUEOUT] set_false_path -through [get_pins -hier *i_idelay/CNTVALUEIN] + +# sync bits i_rx1_ctrl_sync +set_false_path \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_rx1_ctrl_sync* && IS_SEQUENTIAL}] + +# sync bits i_tx1_ctrl_sync +set_false_path \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_tx1_ctrl_sync* && IS_SEQUENTIAL}] diff --git a/library/axi_adrv9001/axi_adrv9001_core.v b/library/axi_adrv9001/axi_adrv9001_core.v index 8d8e50ed3a0..34a967f148c 100644 --- a/library/axi_adrv9001/axi_adrv9001_core.v +++ b/library/axi_adrv9001/axi_adrv9001_core.v @@ -206,13 +206,31 @@ module axi_ad9001_core #( // rx1_r1_mode should be 0 only when rx1_clk and rx2_clk have the same frequency // tx1_r1_mode should be 0 only when tx1_clk and tx2_clk have the same frequency - assign rx2_rst = rx1_r1_mode ? rx2_rst_loc : rx1_rst; - assign rx2_single_lane = rx1_r1_mode ? rx2_single_lane_loc : rx1_single_lane; - assign rx2_sdr_ddr_n = rx1_r1_mode ? rx2_sdr_ddr_n_loc : rx1_sdr_ddr_n; - - assign tx2_rst = tx1_r1_mode ? tx2_rst_loc : tx1_rst; - assign tx2_single_lane = tx1_r1_mode ? tx2_single_lane_loc : tx1_single_lane; - assign tx2_sdr_ddr_n = tx1_r1_mode ? tx2_sdr_ddr_n_loc : tx1_sdr_ddr_n; + sync_bits #( + .NUM_OF_BITS (3), + .ASYNC_CLK (1)) + i_rx1_ctrl_sync ( + .in_bits ({rx1_sdr_ddr_n,rx1_single_lane,rx1_rst}), + .out_clk (rx2_clk), + .out_resetn (1'b1), + .out_bits ({rx1_sdr_ddr_n_s,rx1_single_lane_s,rx1_rst_s})); + + sync_bits #( + .NUM_OF_BITS (3), + .ASYNC_CLK (1)) + i_tx1_ctrl_sync ( + .in_bits ({tx1_sdr_ddr_n,tx1_single_lane,tx1_rst}), + .out_clk (tx2_clk), + .out_resetn (1'b1), + .out_bits ({tx1_sdr_ddr_n_s,tx1_single_lane_s,tx1_rst_s})); + + assign rx2_rst = rx1_r1_mode ? rx2_rst_loc : rx1_rst_s; + assign rx2_single_lane = rx1_r1_mode ? rx2_single_lane_loc : rx1_single_lane_s; + assign rx2_sdr_ddr_n = rx1_r1_mode ? rx2_sdr_ddr_n_loc : rx1_sdr_ddr_n_s; + + assign tx2_rst = tx1_r1_mode ? tx2_rst_loc : tx1_rst_s; + assign tx2_single_lane = tx1_r1_mode ? tx2_single_lane_loc : tx1_single_lane_s; + assign tx2_sdr_ddr_n = tx1_r1_mode ? tx2_sdr_ddr_n_loc : tx1_sdr_ddr_n_s; assign tx1_data_valid = tx1_data_valid_A_d; assign tx1_data_i = tx1_data_i_A_d; @@ -565,7 +583,7 @@ module axi_ad9001_core #( .BASE_ADDRESS (6'h13) ) i_tdd_2 ( .clk (rx2_clk), - .rst (rx2_rst), + .rst (rx2_rst_loc), .tdd_rx_vco_en (), .tdd_tx_vco_en (), .tdd_rx_rf_en (tdd_rx2_rf_en_loc), diff --git a/library/axi_adrv9001/axi_adrv9001_hw.tcl b/library/axi_adrv9001/axi_adrv9001_hw.tcl index 66b7f80d157..4b663812bd5 100644 --- a/library/axi_adrv9001/axi_adrv9001_hw.tcl +++ b/library/axi_adrv9001/axi_adrv9001_hw.tcl @@ -35,6 +35,8 @@ ad_ip_files axi_adrv9001 [list\ "$ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc" \ "$ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc" \ "$ad_hdl_dir/library/intel/common/up_rst_constr.sdc" \ + "$ad_hdl_dir/library/util_cdc/sync_bits.v" \ + "$ad_hdl_dir/library/util_cdc/util_cdc_constr.tcl" \ "intel/adrv9001_rx.v" \ "intel/adrv9001_tx.v" \ "adrv9001_pack.v" \ From 061d024d596ef84c6a819854bf2472e6b43a2d5d Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Mon, 21 Sep 2020 09:56:27 +0100 Subject: [PATCH 40/44] axi_adrv9001: Quartus 19.3 updates --- library/axi_adrv9001/axi_adrv9001_hw.tcl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/library/axi_adrv9001/axi_adrv9001_hw.tcl b/library/axi_adrv9001/axi_adrv9001_hw.tcl index 4b663812bd5..2cfce09e351 100644 --- a/library/axi_adrv9001/axi_adrv9001_hw.tcl +++ b/library/axi_adrv9001/axi_adrv9001_hw.tcl @@ -182,19 +182,19 @@ proc axi_adrv9001_elab {} { set m_fpga_technology [get_parameter_value "FPGA_TECHNOLOGY"] set m_cmos_lvds_n [get_parameter_value "CMOS_LVDS_N"] - add_hdl_instance adrv9001_gpio_in altera_gpio + add_hdl_instance adrv9001_gpio_in altera_gpio 19.3 set_instance_parameter_value adrv9001_gpio_in {DEVICE_FAMILY} {Arria 10} set_instance_parameter_value adrv9001_gpio_in {PIN_TYPE_GUI} {Input} set_instance_parameter_value adrv9001_gpio_in {SIZE} {1} set_instance_parameter_value adrv9001_gpio_in {gui_io_reg_mode} {DDIO} - add_hdl_instance adrv9001_gpio_out altera_gpio + add_hdl_instance adrv9001_gpio_out altera_gpio 19.3 set_instance_parameter_value adrv9001_gpio_out {DEVICE_FAMILY} {Arria 10} set_instance_parameter_value adrv9001_gpio_out {PIN_TYPE_GUI} {Output} set_instance_parameter_value adrv9001_gpio_out {SIZE} {1} set_instance_parameter_value adrv9001_gpio_out {gui_io_reg_mode} {DDIO} - add_hdl_instance periphery_clk_buf altclkctrl + add_hdl_instance periphery_clk_buf altclkctrl 19.1 set_instance_parameter_value periphery_clk_buf {DEVICE_FAMILY} {Arria 10} set_instance_parameter_value periphery_clk_buf {CLOCK_TYPE} {Periphery Clock} From 10b2863bbe1746224adf1ed1d6182b797b16d577 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Fri, 19 Mar 2021 07:55:33 +0000 Subject: [PATCH 41/44] common/up_dac_common: Expose r1_mode in up clock domain to prevent deadlock If R1 mode is first syncronized to the dac clock domain will prevent its usage if the dac clock is missing. In such case the synchronization will not propagate. --- library/common/up_dac_common.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/common/up_dac_common.v b/library/common/up_dac_common.v index b9e84f9eeac..c1e73f286b0 100644 --- a/library/common/up_dac_common.v +++ b/library/common/up_dac_common.v @@ -77,6 +77,7 @@ module up_dac_common #( input [31:0] up_pps_rcounter, input up_pps_status, output reg up_pps_irq_mask, + output reg up_dac_r1_mode = 'd0, // drp interface @@ -127,7 +128,6 @@ module up_dac_common #( reg up_dac_sdr_ddr_n = 'd0; reg up_dac_par_type = 'd0; reg up_dac_par_enb = 'd0; - reg up_dac_r1_mode = 'd0; reg up_dac_datafmt = 'd0; reg [15:0] up_dac_datarate = 'd0; reg up_dac_frame = 'd0; From 12668554256ddf369e229267b48e3b413751630b Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Fri, 19 Mar 2021 08:00:14 +0000 Subject: [PATCH 42/44] axi_adrv9001: Allow running Rx2/Tx2 channels in R1 mode without Rx1/Tx1 This commit removes the deadlock created while trying to use the Rx2/Tx2 channels without the Rx1/Tx1 channels enabled first. --- library/axi_adrv9001/axi_adrv9001_core.v | 18 ++++++++++-------- library/axi_adrv9001/axi_adrv9001_rx.v | 7 +++---- library/axi_adrv9001/axi_adrv9001_tx.v | 7 ++++--- 3 files changed, 17 insertions(+), 15 deletions(-) diff --git a/library/axi_adrv9001/axi_adrv9001_core.v b/library/axi_adrv9001/axi_adrv9001_core.v index 34a967f148c..673b92ded25 100644 --- a/library/axi_adrv9001/axi_adrv9001_core.v +++ b/library/axi_adrv9001/axi_adrv9001_core.v @@ -183,10 +183,12 @@ module axi_ad9001_core #( wire tx2_data_valid_A; wire [15:0] tx2_data_i_A; wire [15:0] tx2_data_q_A; + wire up_rx1_r1_mode; wire rx1_r1_mode; wire rx2_rst_loc; wire rx2_single_lane_loc; wire rx2_sdr_ddr_n_loc; + wire up_tx1_r1_mode; wire tx1_r1_mode; wire tx2_rst_loc; wire tx2_single_lane_loc; @@ -207,22 +209,22 @@ module axi_ad9001_core #( // tx1_r1_mode should be 0 only when tx1_clk and tx2_clk have the same frequency sync_bits #( - .NUM_OF_BITS (3), + .NUM_OF_BITS (4), .ASYNC_CLK (1)) i_rx1_ctrl_sync ( - .in_bits ({rx1_sdr_ddr_n,rx1_single_lane,rx1_rst}), + .in_bits ({up_rx1_r1_mode,rx1_sdr_ddr_n,rx1_single_lane,rx1_rst}), .out_clk (rx2_clk), .out_resetn (1'b1), - .out_bits ({rx1_sdr_ddr_n_s,rx1_single_lane_s,rx1_rst_s})); + .out_bits ({rx1_r1_mode,rx1_sdr_ddr_n_s,rx1_single_lane_s,rx1_rst_s})); sync_bits #( - .NUM_OF_BITS (3), + .NUM_OF_BITS (4), .ASYNC_CLK (1)) i_tx1_ctrl_sync ( - .in_bits ({tx1_sdr_ddr_n,tx1_single_lane,tx1_rst}), + .in_bits ({up_tx1_r1_mode,tx1_sdr_ddr_n,tx1_single_lane,tx1_rst}), .out_clk (tx2_clk), .out_resetn (1'b1), - .out_bits ({tx1_sdr_ddr_n_s,tx1_single_lane_s,tx1_rst_s})); + .out_bits ({tx1_r1_mode,tx1_sdr_ddr_n_s,tx1_single_lane_s,tx1_rst_s})); assign rx2_rst = rx1_r1_mode ? rx2_rst_loc : rx1_rst_s; assign rx2_single_lane = rx1_r1_mode ? rx2_single_lane_loc : rx1_single_lane_s; @@ -309,7 +311,7 @@ module axi_ad9001_core #( .adc_single_lane (rx1_single_lane), .adc_sdr_ddr_n (rx1_sdr_ddr_n), - .adc_r1_mode (rx1_r1_mode), + .up_adc_r1_mode (up_rx1_r1_mode), .dac_data_valid_A (tx1_data_valid_A), .dac_data_i_A (tx1_data_i_A), @@ -424,7 +426,7 @@ module axi_ad9001_core #( .dac_data_q_B (tx1_data_q_B), .dac_single_lane (tx1_single_lane), .dac_sdr_ddr_n (tx1_sdr_ddr_n), - .dac_r1_mode (tx1_r1_mode), + .up_dac_r1_mode (up_tx1_r1_mode), .tdd_tx_valid (tdd_tx1_valid), .dac_sync_in (1'b0), .dac_sync_out (), diff --git a/library/axi_adrv9001/axi_adrv9001_rx.v b/library/axi_adrv9001/axi_adrv9001_rx.v index e17c41c1a18..fcf4be49208 100644 --- a/library/axi_adrv9001/axi_adrv9001_rx.v +++ b/library/axi_adrv9001/axi_adrv9001_rx.v @@ -63,7 +63,7 @@ module axi_adrv9001_rx #( output adc_single_lane, output adc_sdr_ddr_n, - output adc_r1_mode, + output up_adc_r1_mode, // dac loopback interface input dac_data_valid_A, @@ -108,7 +108,7 @@ if (ENABLED == 0) begin : core_disabled assign adc_rst = 1'b0; assign adc_single_lane = 1'b0; assign adc_sdr_ddr_n = 1'b0; - assign adc_r1_mode = 1'b0; + assign up_adc_r1_mode = 1'b0; assign adc_valid = 1'b0; assign adc_enable_i0 = 1'b0; assign adc_data_i0 = 16'b0; @@ -154,7 +154,6 @@ end else begin : core_enabled wire [ 4:0] up_wack_s; wire [ 4:0] up_rack_s; wire [ 31:0] up_rdata_s[0:4]; - wire up_adc_r1_mode; wire adc_valid_out_i0; wire adc_valid_out_i1; @@ -348,7 +347,7 @@ end else begin : core_enabled .mmcm_rst (), .adc_clk (adc_clk), .adc_rst (adc_rst), - .adc_r1_mode (adc_r1_mode), + .adc_r1_mode (), .adc_ddr_edgesel (), .adc_pin_mode (), .adc_status (1'b1), diff --git a/library/axi_adrv9001/axi_adrv9001_tx.v b/library/axi_adrv9001/axi_adrv9001_tx.v index af32821e299..86cbc87fe98 100644 --- a/library/axi_adrv9001/axi_adrv9001_tx.v +++ b/library/axi_adrv9001/axi_adrv9001_tx.v @@ -67,7 +67,7 @@ module axi_adrv9001_tx #( output dac_single_lane, output dac_sdr_ddr_n, - output dac_r1_mode, + output up_dac_r1_mode, input tdd_tx_valid, @@ -114,7 +114,7 @@ if (ENABLED == 0) begin : core_disabled assign dac_data_q_B = 16'b0; assign dac_single_lane = 1'b0; assign dac_sdr_ddr_n = 1'b0; - assign dac_r1_mode = 1'b0; + assign up_dac_r1_mode = 1'b0; assign dac_sync_out = 1'b0; assign dac_valid = 1'b0; assign dac_enable_i0 = 1'b0; @@ -373,7 +373,8 @@ end else begin : core_enabled .dac_clksel (), .dac_par_type (), .dac_par_enb (), - .dac_r1_mode (dac_r1_mode), + .dac_r1_mode (), + .up_dac_r1_mode (up_dac_r1_mode), .dac_datafmt (dac_dds_format_s), .dac_datarate (dac_datarate_s), .dac_status (1'b1), From 43c6ae1ca9faf268f30c7ef489f1428fc30a8b23 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Tue, 11 May 2021 11:55:11 +0100 Subject: [PATCH 43/44] adrv9001/zcu102: Enable independent TX mode in CMOS For CMOS case, lane rates are so low that reference clock of the source synchronous interface can be routed on non-clock routes. The delays on the clock line are adjusted by the digital interface tuning controlled through software. Lock down clock buffers on Rx and Tx interfaces, this avoids suboptimal placement which causes large skew between clocks at the serdes pins. --- projects/adrv9001/zcu102/cmos_constr.xdc | 14 ++++++++++++++ projects/adrv9001/zcu102/system_bd.tcl | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/projects/adrv9001/zcu102/cmos_constr.xdc b/projects/adrv9001/zcu102/cmos_constr.xdc index 84825bb7458..ede4d0140bb 100644 --- a/projects/adrv9001/zcu102/cmos_constr.xdc +++ b/projects/adrv9001/zcu102/cmos_constr.xdc @@ -53,4 +53,18 @@ set_clock_latency -source -early -0.25 [get_clocks rx2_dclk_out] set_clock_latency -source -late 0.25 [get_clocks rx1_dclk_out] set_clock_latency -source -late 0.25 [get_clocks rx2_dclk_out] +create_pblock SSI_REGION +add_cells_to_pblock [get_pblocks SSI_REGION] [get_cells -quiet [list \ + i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_clk_buf_fast \ + i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_div_clk_buf \ + i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_buf_fast \ + i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf \ + i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_1_phy/i_dac_clk_in_gbuf \ + i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_1_phy/i_dac_div_clk_rbuf \ + i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_2_phy/i_dac_clk_in_gbuf \ + i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_2_phy/i_dac_div_clk_rbuf \ + ]] +resize_pblock SSI_REGION -add CLOCKREGION_X3Y2:CLOCKREGION_X3Y3 +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_1_phy/i_dac_clk_in_ibuf/O] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_2_phy/i_dac_clk_in_ibuf/O] diff --git a/projects/adrv9001/zcu102/system_bd.tcl b/projects/adrv9001/zcu102/system_bd.tcl index 0d34f3183a9..5b675c3b86f 100644 --- a/projects/adrv9001/zcu102/system_bd.tcl +++ b/projects/adrv9001/zcu102/system_bd.tcl @@ -2,7 +2,7 @@ source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl source ../common/adrv9001_bd.tcl -ad_ip_parameter axi_adrv9001 CONFIG.USE_RX_CLK_FOR_TX 1 +ad_ip_parameter axi_adrv9001 CONFIG.USE_RX_CLK_FOR_TX [expr $ad_project_params(CMOS_LVDS_N) == 0] #system ID ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 From 43cdc6263baf3edb166a3def6fab15bc81c4c729 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Tue, 3 Aug 2021 20:57:50 +0100 Subject: [PATCH 44/44] pluto: Fix dunf connection --- projects/pluto/system_bd.tcl | 1 + 1 file changed, 1 insertion(+) diff --git a/projects/pluto/system_bd.tcl b/projects/pluto/system_bd.tcl index 8a9634b9a30..fa47a8406ae 100644 --- a/projects/pluto/system_bd.tcl +++ b/projects/pluto/system_bd.tcl @@ -297,6 +297,7 @@ ad_ip_instance util_vector_logic logic_or [list \ ad_connect logic_or/Op1 tx_fir_interpolator/valid_out_0 ad_connect logic_or/Op2 axi_ad9361/dac_valid_i1 ad_connect logic_or/Res tx_upack/fifo_rd_en +ad_connect tx_upack/fifo_rd_underflow axi_ad9361/dac_dunf ad_connect axi_ad9361/up_dac_gpio_out interp_slice/Din ad_connect tx_fir_interpolator/active interp_slice/Dout