diff --git a/projects/scripts/write_bitstream_pre.tcl b/projects/scripts/write_bitstream_pre.tcl new file mode 100644 index 00000000000..b4c1a1affdd --- /dev/null +++ b/projects/scripts/write_bitstream_pre.tcl @@ -0,0 +1,3 @@ +# This is a placeholder script for write_bitstream_pre hook +# It doesn't need to do anything for our purposes +puts "Running write_bitstream_pre.tcl" diff --git a/projects/signalsdrpi/Makefile b/projects/signalsdrpi/Makefile new file mode 100644 index 00000000000..7c8b421485c --- /dev/null +++ b/projects/signalsdrpi/Makefile @@ -0,0 +1,21 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := signalsdrpi + +M_DEPS += ../common/xilinx/adi_fir_filter_constr.xdc +M_DEPS += ../common/xilinx/adi_fir_filter_bd.tcl +M_DEPS += ../../library/common/ad_iobuf.v +M_DEPS += ../../library/util_cdc/sync_bits.v +M_DEPS += ../../library/common/util_pulse_gen.v +M_DEPS += ../../library/common/ad_bus_mux.v +M_DEPS += ../../library/axi_ad9361/axi_ad9361_delay.tcl + +LIB_DEPS += axi_ad9361 +LIB_DEPS += axi_dmac +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 + +include ../scripts/project-xilinx.mk diff --git a/projects/signalsdrpi/system_bd.tcl b/projects/signalsdrpi/system_bd.tcl new file mode 100644 index 00000000000..42a1106413d --- /dev/null +++ b/projects/signalsdrpi/system_bd.tcl @@ -0,0 +1,357 @@ +# create board design + + +source $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_bd.tcl + +# default ports + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr +create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io + +create_bd_port -dir O spi0_csn_2_o +create_bd_port -dir O spi0_csn_1_o +create_bd_port -dir O spi0_csn_0_o +create_bd_port -dir I spi0_csn_i +create_bd_port -dir I spi0_clk_i +create_bd_port -dir O spi0_clk_o +create_bd_port -dir I spi0_sdo_i +create_bd_port -dir O spi0_sdo_o +create_bd_port -dir I spi0_sdi_i + +create_bd_port -dir I -from 24 -to 0 gpio_i +create_bd_port -dir O -from 24 -to 0 gpio_o +create_bd_port -dir O -from 24 -to 0 gpio_t + +create_bd_port -dir O spi_csn_o +create_bd_port -dir I spi_csn_i +create_bd_port -dir I spi_clk_i +create_bd_port -dir O spi_clk_o +create_bd_port -dir I spi_sdo_i +create_bd_port -dir O spi_sdo_o +create_bd_port -dir I spi_sdi_i + +# instance: sys_ps7 + +ad_ip_instance processing_system7 sys_ps7 + +# ps7 settings + +ad_ip_parameter sys_ps7 CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} +ad_ip_parameter sys_ps7 CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} +ad_ip_parameter sys_ps7 CONFIG.PCW_PACKAGE_NAME clg400 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_MIO_GPIO_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_ENET0_IO "MIO 16 .. 27" +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_IO "MIO 52 .. 53" +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET_RESET_SELECT "Separate reset pins" +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_RESET_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_RESET_IO "MIO 46" +ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP1 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP2 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK1_PORT 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_EN_RST1_PORT 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ 100.0 +ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 200.0 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO 25 +ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_PERIPHERAL_ENABLE 0 +ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_PERIPHERAL_ENABLE 0 +ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ 50 +ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} +ad_ip_parameter sys_ps7 CONFIG.PCW_I2C1_PERIPHERAL_ENABLE 0 +ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_SPI0_IO EMIO +ad_ip_parameter sys_ps7 CONFIG.PCW_TTC0_PERIPHERAL_ENABLE 0 +ad_ip_parameter sys_ps7 CONFIG.PCW_USE_FABRIC_INTERRUPT 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_MIO_GPIO_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_MIO_GPIO_IO MIO +ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_IO {MIO 47} +ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_INTR 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_MODE REVERSE +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_0_PULLUP {enabled} +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_9_PULLUP {enabled} +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_10_PULLUP {enabled} +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_11_PULLUP {enabled} +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_48_PULLUP {enabled} +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_49_PULLUP {disabled} +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_53_PULLUP {enabled} + +# DDR MT41K256M16 HA-15E (32M, 16bit, 8banks) + +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF 0 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 0.110 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 0.095 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 0.249 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 0.249 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 0.202 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 0.217 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 0.216 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 0.217 + +ad_ip_instance xlconcat sys_concat_intc +ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 16 + +ad_ip_instance proc_sys_reset sys_rstgen +ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1 + +# system reset/clock definitions + +# add external spi + +ad_ip_instance axi_quad_spi axi_spi +ad_ip_parameter axi_spi CONFIG.C_USE_STARTUP 0 +ad_ip_parameter axi_spi CONFIG.C_NUM_SS_BITS 1 +ad_ip_parameter axi_spi CONFIG.C_SCK_RATIO 8 + +ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0 +ad_connect sys_200m_clk sys_ps7/FCLK_CLK1 +ad_connect sys_cpu_reset sys_rstgen/peripheral_reset +ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn +ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk +ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N + +# interface connections + +ad_connect ddr sys_ps7/DDR +ad_connect gpio_i sys_ps7/GPIO_I +ad_connect gpio_o sys_ps7/GPIO_O +ad_connect gpio_t sys_ps7/GPIO_T +ad_connect fixed_io sys_ps7/FIXED_IO + +# ps7 spi connections + +ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O +ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O +ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O +ad_connect spi0_csn_i sys_ps7/SPI0_SS_I +ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I +ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O +ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I +ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O +ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I + +# axi spi connections + +ad_connect sys_cpu_clk axi_spi/ext_spi_clk +ad_connect spi_csn_i axi_spi/ss_i +ad_connect spi_csn_o axi_spi/ss_o +ad_connect spi_clk_i axi_spi/sck_i +ad_connect spi_clk_o axi_spi/sck_o +ad_connect spi_sdo_i axi_spi/io0_i +ad_connect spi_sdo_o axi_spi/io0_o +ad_connect spi_sdi_i axi_spi/io1_i + +# interrupts + +ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P +ad_connect sys_concat_intc/In15 GND +ad_connect sys_concat_intc/In14 GND +ad_connect sys_concat_intc/In13 GND +ad_connect sys_concat_intc/In12 GND +ad_connect sys_concat_intc/In11 GND +ad_connect sys_concat_intc/In10 GND +ad_connect sys_concat_intc/In9 GND +ad_connect sys_concat_intc/In8 GND +ad_connect sys_concat_intc/In7 GND +ad_connect sys_concat_intc/In6 GND +ad_connect sys_concat_intc/In5 GND +ad_connect sys_concat_intc/In4 GND +ad_connect sys_concat_intc/In3 GND +ad_connect sys_concat_intc/In2 GND +ad_connect sys_concat_intc/In1 GND +ad_connect sys_concat_intc/In0 GND + +# iic + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main + +ad_ip_instance axi_iic axi_iic_main + +ad_connect iic_main axi_iic_main/iic +ad_cpu_interconnect 0x41600000 axi_iic_main +ad_cpu_interrupt ps-15 mb-15 axi_iic_main/iic2intc_irpt + +# ad9361 + +create_bd_port -dir I rx_clk_in +create_bd_port -dir I rx_frame_in +create_bd_port -dir I -from 11 -to 0 rx_data_in + +create_bd_port -dir O tx_clk_out +create_bd_port -dir O tx_frame_out +create_bd_port -dir O -from 11 -to 0 tx_data_out + +create_bd_port -dir O enable +create_bd_port -dir O txnrx +create_bd_port -dir I up_enable +create_bd_port -dir I up_txnrx + +# ad9361 core(s) + +ad_ip_instance axi_ad9361 axi_ad9361 +ad_ip_parameter axi_ad9361 CONFIG.ID 0 +ad_ip_parameter axi_ad9361 CONFIG.CMOS_OR_LVDS_N 1 +ad_ip_parameter axi_ad9361 CONFIG.MODE_1R1T 0 +ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 21 + +ad_ip_instance axi_dmac axi_ad9361_dac_dma +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_SRC 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_DEST 1 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.CYCLIC 1 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_DEST 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 64 + +ad_add_interpolation_filter "tx_fir_interpolator" 8 2 1 {61.44} {7.68} \ + "$ad_hdl_dir/library/util_fir_int/coefile_int.coe" +ad_ip_instance xlslice interp_slice +ad_ip_instance util_upack2 tx_upack + +ad_ip_instance axi_dmac axi_ad9361_adc_dma +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_TYPE_SRC 2 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_DEST 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_SRC 64 + +ad_add_decimation_filter "rx_fir_decimator" 8 2 1 {61.44} {61.44} \ + "$ad_hdl_dir/library/util_fir_int/coefile_int.coe" +ad_ip_instance xlslice decim_slice +ad_ip_instance util_cpack2 cpack + +# connections + +ad_connect rx_clk_in axi_ad9361/rx_clk_in +ad_connect rx_frame_in axi_ad9361/rx_frame_in +ad_connect rx_data_in axi_ad9361/rx_data_in +ad_connect tx_clk_out axi_ad9361/tx_clk_out +ad_connect tx_frame_out axi_ad9361/tx_frame_out +ad_connect tx_data_out axi_ad9361/tx_data_out +ad_connect enable axi_ad9361/enable +ad_connect txnrx axi_ad9361/txnrx +ad_connect up_enable axi_ad9361/up_enable +ad_connect up_txnrx axi_ad9361/up_txnrx + +ad_connect axi_ad9361/tdd_sync GND +ad_connect sys_200m_clk axi_ad9361/delay_clk +ad_connect axi_ad9361/l_clk axi_ad9361/clk + +ad_connect axi_ad9361/l_clk rx_fir_decimator/aclk + +ad_connect axi_ad9361/adc_valid_i0 rx_fir_decimator/valid_in_0 +ad_connect axi_ad9361/adc_enable_i0 rx_fir_decimator/enable_in_0 +ad_connect axi_ad9361/adc_data_i0 rx_fir_decimator/data_in_0 +ad_connect axi_ad9361/adc_valid_q0 rx_fir_decimator/valid_in_1 +ad_connect axi_ad9361/adc_enable_q0 rx_fir_decimator/enable_in_1 +ad_connect axi_ad9361/adc_data_q0 rx_fir_decimator/data_in_1 + +ad_connect axi_ad9361/l_clk cpack/clk +ad_connect axi_ad9361/rst cpack/reset + +ad_connect axi_ad9361/adc_enable_i1 cpack/enable_2 +ad_connect axi_ad9361/adc_data_i1 cpack/fifo_wr_data_2 +ad_connect axi_ad9361/adc_enable_q1 cpack/enable_3 +ad_connect axi_ad9361/adc_data_q1 cpack/fifo_wr_data_3 + +ad_connect cpack/enable_0 rx_fir_decimator/enable_out_0 +ad_connect cpack/enable_1 rx_fir_decimator/enable_out_1 +ad_connect cpack/fifo_wr_data_0 rx_fir_decimator/data_out_0 +ad_connect cpack/fifo_wr_data_1 rx_fir_decimator/data_out_1 +ad_connect rx_fir_decimator/valid_out_0 cpack/fifo_wr_en + +ad_connect axi_ad9361_adc_dma/fifo_wr cpack/packed_fifo_wr +ad_connect axi_ad9361/up_adc_gpio_out decim_slice/Din +ad_connect rx_fir_decimator/active decim_slice/Dout + +ad_connect axi_ad9361/l_clk tx_fir_interpolator/aclk + +ad_connect axi_ad9361/dac_enable_i0 tx_fir_interpolator/dac_enable_0 +ad_connect axi_ad9361/dac_valid_i0 tx_fir_interpolator/dac_valid_0 +ad_connect axi_ad9361/dac_data_i0 tx_fir_interpolator/data_out_0 +ad_connect axi_ad9361/dac_enable_q0 tx_fir_interpolator/dac_enable_1 +ad_connect axi_ad9361/dac_valid_q0 tx_fir_interpolator/dac_valid_1 +ad_connect axi_ad9361/dac_data_q0 tx_fir_interpolator/data_out_1 + +ad_connect axi_ad9361/l_clk tx_upack/clk +ad_connect axi_ad9361/rst tx_upack/reset + +ad_connect tx_upack/fifo_rd_data_0 tx_fir_interpolator/data_in_0 +ad_connect tx_upack/enable_0 tx_fir_interpolator/enable_out_0 +ad_connect tx_upack/fifo_rd_data_1 tx_fir_interpolator/data_in_1 +ad_connect tx_upack/enable_1 tx_fir_interpolator/enable_out_1 + +ad_connect axi_ad9361/dac_enable_i1 tx_upack/enable_2 +ad_connect axi_ad9361/dac_data_i1 tx_upack/fifo_rd_data_2 +ad_connect axi_ad9361/dac_enable_q1 tx_upack/enable_3 +ad_connect axi_ad9361/dac_data_q1 tx_upack/fifo_rd_data_3 + +ad_connect tx_upack/s_axis axi_ad9361_dac_dma/m_axis + +ad_ip_instance util_vector_logic logic_or [list \ + C_OPERATION {or} \ + C_SIZE 1] + +ad_connect logic_or/Op1 tx_fir_interpolator/valid_out_0 +ad_connect logic_or/Op2 axi_ad9361/dac_valid_i1 +ad_connect logic_or/Res tx_upack/fifo_rd_en + +ad_connect axi_ad9361/up_dac_gpio_out interp_slice/Din +ad_connect tx_fir_interpolator/active interp_slice/Dout + +ad_connect axi_ad9361/l_clk axi_ad9361_adc_dma/fifo_wr_clk +ad_connect axi_ad9361/l_clk axi_ad9361_dac_dma/m_axis_aclk +ad_connect cpack/fifo_wr_overflow axi_ad9361/adc_dovf + +# interconnects + +ad_cpu_interconnect 0x79020000 axi_ad9361 +ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma +ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma +ad_cpu_interconnect 0x7C430000 axi_spi + +ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP1 {1} +ad_connect sys_cpu_clk sys_ps7/S_AXI_HP1_ACLK +ad_connect axi_ad9361_adc_dma/m_dest_axi sys_ps7/S_AXI_HP1 + +create_bd_addr_seg -range 0x40000000 -offset 0x00000000 \ + [get_bd_addr_spaces axi_ad9361_adc_dma/m_dest_axi] \ + [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] \ + SEG_sys_ps7_HP1_DDR_LOWOCM + +ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP2 {1} +ad_connect sys_cpu_clk sys_ps7/S_AXI_HP2_ACLK +ad_connect axi_ad9361_dac_dma/m_src_axi sys_ps7/S_AXI_HP2 + +create_bd_addr_seg -range 0x40000000 -offset 0x00000000 \ + [get_bd_addr_spaces axi_ad9361_dac_dma/m_src_axi] \ + [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] \ + SEG_sys_ps7_HP2_DDR_LOWOCM + +ad_connect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi_aclk +ad_connect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi_aclk +ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn +ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn + +# interrupts + +ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq +ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq +ad_cpu_interrupt ps-11 mb-11 axi_spi/ip2intc_irpt + + diff --git a/projects/signalsdrpi/system_constr.xdc b/projects/signalsdrpi/system_constr.xdc new file mode 100644 index 00000000000..59fb6a95bca --- /dev/null +++ b/projects/signalsdrpi/system_constr.xdc @@ -0,0 +1,194 @@ +set_property PACKAGE_PIN p16 [get_ports gpio_en_agc] +# +set_property PACKAGE_PIN n17 [get_ports gpio_resetb] +# + +set_property PACKAGE_PIN t10 [get_ports {gpio_ctl[0]}] +# +set_property PACKAGE_PIN j14 [get_ports {gpio_ctl[1]}] +# +set_property PACKAGE_PIN n15 [get_ports {gpio_ctl[2]}] +# + + +set_property PACKAGE_PIN n16 [get_ports {gpio_ctl[3]}] +# + +set_property PACKAGE_PIN t11 [get_ports {gpio_status[0]}] +# +set_property PACKAGE_PIN t14 [get_ports {gpio_status[1]}] +# +set_property PACKAGE_PIN t15 [get_ports {gpio_status[2]}] +# +set_property PACKAGE_PIN t17 [get_ports {gpio_status[3]}] +# +set_property PACKAGE_PIN t19 [get_ports {gpio_status[4]}] +# +set_property PACKAGE_PIN t20 [get_ports {gpio_status[5]}] + # +set_property PACKAGE_PIN u13 [get_ports {gpio_status[6]}] +# +set_property PACKAGE_PIN v13 [get_ports {gpio_status[7]}] +# + +set_property PACKAGE_PIN n20 [get_ports rx_clk_in] +#rx_clk_in_p +set_property PACKAGE_PIN u18 [get_ports rx_frame_in] +#rx_frame_in_p + +set_property PACKAGE_PIN y19 [get_ports {rx_data_in[0]}] +#rx_data_in_n[0] +set_property PACKAGE_PIN y18 [get_ports {rx_data_in[1]}] +#rx_data_in_p[0] + +set_property PACKAGE_PIN w20 [get_ports {rx_data_in[2]}] +#rx_data_in_n[1] +set_property PACKAGE_PIN v20 [get_ports {rx_data_in[3]}] + #rx_data_in_p[1] + +set_property PACKAGE_PIN w19 [get_ports {rx_data_in[4]}] +#rx_data_in_n[2] +set_property PACKAGE_PIN w18 [get_ports {rx_data_in[5]}] +#rx_data_in_p[2] + +set_property PACKAGE_PIN r17 [get_ports {rx_data_in[6]}] +#rx_data_in_n[3] +set_property PACKAGE_PIN r16 [get_ports {rx_data_in[7]}] +#rx_data_in_p[3] + +set_property PACKAGE_PIN v18 [get_ports {rx_data_in[8]}] +#rx_data_in_n[4] +set_property PACKAGE_PIN v17 [get_ports {rx_data_in[9]}] +#rx_data_in_p[4] + +set_property PACKAGE_PIN w16 [get_ports {rx_data_in[10]}] +#rx_data_in_n[5] +set_property PACKAGE_PIN v16 [get_ports {rx_data_in[11]}] +#rx_data_in_p[5] + +set_property PACKAGE_PIN y17 [get_ports {tx_data_out[0]}] +#tx_data_out_n[0] +set_property PACKAGE_PIN y16 [get_ports {tx_data_out[1]}] +#tx_data_out_p[0] + +set_property PACKAGE_PIN u15 [get_ports {tx_data_out[2]}] +#tx_data_out_n[1] +set_property PACKAGE_PIN u14 [get_ports {tx_data_out[3]}] +#tx_data_out_p[1] + +set_property PACKAGE_PIN w15 [get_ports {tx_data_out[4]}] +#tx_data_out_n[2] +set_property PACKAGE_PIN v15 [get_ports {tx_data_out[5]}] +#tx_data_out_p[2] + +set_property PACKAGE_PIN y14 [get_ports {tx_data_out[6]}] +#tx_data_out_n[3] +set_property PACKAGE_PIN w14 [get_ports {tx_data_out[7]}] +#tx_data_out_p[3] + +set_property PACKAGE_PIN w13 [get_ports {tx_data_out[8]}] +#tx_data_out_n[4] +set_property PACKAGE_PIN v12 [get_ports {tx_data_out[9]}] +#tx_data_out_p[4] + +set_property PACKAGE_PIN u12 [get_ports {tx_data_out[10]}] +#tx_data_out_n[5] +set_property PACKAGE_PIN t12 [get_ports {tx_data_out[11]}] +#tx_data_out_p[5] + +set_property PACKAGE_PIN n18 [get_ports tx_clk_out] +#tx_clk_out_p +set_property PACKAGE_PIN t16 [get_ports tx_frame_out] +#tx_frame_out_p + + + +set_property PACKAGE_PIN p14 [get_ports txnrx] +set_property PACKAGE_PIN r18 [get_ports enable] +set_property PACKAGE_PIN m14 [get_ports iic_scl] +set_property PACKAGE_PIN m15 [get_ports iic_sda] +set_property PACKAGE_PIN p18 [get_ports spi_csn] +set_property PACKAGE_PIN r14 [get_ports spi_clk] +set_property PACKAGE_PIN p15 [get_ports spi_mosi] +set_property PACKAGE_PIN r19 [get_ports spi_miso] + + + + + +set_property IOSTANDARD LVCMOS18 [get_ports gpio_en_agc] +set_property IOSTANDARD LVCMOS18 [get_ports gpio_resetb] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_ctl[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_ctl[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_ctl[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_ctl[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_status[7]}] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_status[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_status[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_status[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_status[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_status[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_status[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_status[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports iic_scl] +set_property IOSTANDARD LVCMOS18 [get_ports iic_sda] + +set_property IOSTANDARD LVCMOS18 [get_ports spi_clk] +set_property IOSTANDARD LVCMOS18 [get_ports spi_csn] +set_property IOSTANDARD LVCMOS18 [get_ports spi_miso] +set_property IOSTANDARD LVCMOS18 [get_ports spi_mosi] +set_property IOSTANDARD LVCMOS18 [get_ports clk_out] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[11]}] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[10]}] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[9]}] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[8]}] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[7]}] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[11]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[10]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[9]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[8]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[7]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports enable] +set_property IOSTANDARD LVCMOS18 [get_ports rx_clk_in] +set_property IOSTANDARD LVCMOS18 [get_ports rx_frame_in] +set_property IOSTANDARD LVCMOS18 [get_ports tx_clk_out] +set_property IOSTANDARD LVCMOS18 [get_ports tx_frame_out] +set_property IOSTANDARD LVCMOS18 [get_ports txnrx] + +create_clock -name rx_clk -period 16.27 [get_ports rx_clk_in] +create_clock -name clk_fpga_0 -period 10 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]"] +create_clock -name clk_fpga_1 -period 5 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]"] + +create_clock -name spi0_clk -period 40 [get_pins -hier */EMIOSPI0SCLKO] + +set_input_jitter clk_fpga_0 0.3 +set_input_jitter clk_fpga_1 0.15 + + +set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS18} [get_ports tx1_en] +set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS18} [get_ports tx2_en] +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18} [get_ports sel_clk_src] + +set_property -dict {PACKAGE_PIN a20 IOSTANDARD LVCMOS18} [get_ports rx1_led ] +set_property -dict {PACKAGE_PIN b19 IOSTANDARD LVCMOS18} [get_ports rx2_led ] + + + + + + + diff --git a/projects/signalsdrpi/system_project.tcl b/projects/signalsdrpi/system_project.tcl new file mode 100644 index 00000000000..0b0c68777f2 --- /dev/null +++ b/projects/signalsdrpi/system_project.tcl @@ -0,0 +1,17 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z020clg400-1" +adi_project signalsdrpi + +adi_project_files signalsdrpi [list \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_iobuf.v"] + +set_property is_enabled false [get_files *system_sys_ps7_0.xdc] +adi_project_run signalsdrpi +source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl + diff --git a/projects/signalsdrpi/system_top.v b/projects/signalsdrpi/system_top.v new file mode 100644 index 00000000000..64078c818c0 --- /dev/null +++ b/projects/signalsdrpi/system_top.v @@ -0,0 +1,185 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 1:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 1:0] ddr_dqs_n, + inout [ 1:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [31:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout iic_scl, + inout iic_sda, + + input rx_clk_in, + input rx_frame_in, + input [11:0] rx_data_in, + output tx_clk_out, + output tx_frame_out, + output [11:0] tx_data_out, + + output enable, + output txnrx, + input clk_out, + + inout gpio_resetb, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, + + output spi_csn , + output spi_clk , + output spi_mosi , + input spi_miso , + output tx1_en , tx2_en , sel_clk_src, + output rx1_led,rx2_led + ); + + +assign {tx1_en,tx2_en,sel_clk_src} = 3'b101 ; +assign rx1_led = 1'b1 ; +assign rx2_led = 1'b0 ; + + wire pl_spi_clk_o ; + wire pl_spi_mosi ; + wire pl_spi_miso ; + + // internal signals + + wire [24:0] gpio_i; + wire [24:0] gpio_o; + wire [24:0] gpio_t; + + // instantiations + + ad_iobuf #(.DATA_WIDTH(14)) i_iobuf ( + .dio_t (gpio_t[13:0]), + .dio_i (gpio_o[13:0]), + .dio_o (gpio_i[13:0]), + .dio_p ({ gpio_resetb, // 13:13 + gpio_en_agc, // 12:12 + gpio_ctl, // 11: 8 + gpio_status})); // 7: 0 + + assign gpio_i[24:14] = gpio_o[24:14]; + + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .rx_clk_in (rx_clk_in), + .rx_data_in (rx_data_in), + .rx_frame_in (rx_frame_in), + + // .ltc2630_mosi_0(ltc2630_mosi_0), + // .ltc2630_ncs_0(ltc2630_ncs_0), + // .ltc2630_sclk_0(ltc2630_sclk_0), + + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + + .spi_clk_i(1'b0), + .spi_clk_o(pl_spi_clk_o), + .spi_csn_i(1'b1), + .spi_csn_o(), + .spi_sdi_i(pl_spi_miso), + .spi_sdo_i(1'b0), + .spi_sdo_o(pl_spi_mosi), + + .tx_clk_out (tx_clk_out), + .tx_data_out (tx_data_out), + .tx_frame_out (tx_frame_out), + .txnrx (txnrx), + .up_enable (gpio_o[15]), + .up_txnrx (gpio_o[16])); + +endmodule + +// *************************************************************************** +// *************************************************************************** + + diff --git a/projects/signalsdrpro/Makefile b/projects/signalsdrpro/Makefile new file mode 100644 index 00000000000..7c8b421485c --- /dev/null +++ b/projects/signalsdrpro/Makefile @@ -0,0 +1,21 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := signalsdrpi + +M_DEPS += ../common/xilinx/adi_fir_filter_constr.xdc +M_DEPS += ../common/xilinx/adi_fir_filter_bd.tcl +M_DEPS += ../../library/common/ad_iobuf.v +M_DEPS += ../../library/util_cdc/sync_bits.v +M_DEPS += ../../library/common/util_pulse_gen.v +M_DEPS += ../../library/common/ad_bus_mux.v +M_DEPS += ../../library/axi_ad9361/axi_ad9361_delay.tcl + +LIB_DEPS += axi_ad9361 +LIB_DEPS += axi_dmac +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 + +include ../scripts/project-xilinx.mk diff --git a/projects/signalsdrpro/system_bd.tcl b/projects/signalsdrpro/system_bd.tcl new file mode 100644 index 00000000000..42a1106413d --- /dev/null +++ b/projects/signalsdrpro/system_bd.tcl @@ -0,0 +1,357 @@ +# create board design + + +source $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_bd.tcl + +# default ports + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr +create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io + +create_bd_port -dir O spi0_csn_2_o +create_bd_port -dir O spi0_csn_1_o +create_bd_port -dir O spi0_csn_0_o +create_bd_port -dir I spi0_csn_i +create_bd_port -dir I spi0_clk_i +create_bd_port -dir O spi0_clk_o +create_bd_port -dir I spi0_sdo_i +create_bd_port -dir O spi0_sdo_o +create_bd_port -dir I spi0_sdi_i + +create_bd_port -dir I -from 24 -to 0 gpio_i +create_bd_port -dir O -from 24 -to 0 gpio_o +create_bd_port -dir O -from 24 -to 0 gpio_t + +create_bd_port -dir O spi_csn_o +create_bd_port -dir I spi_csn_i +create_bd_port -dir I spi_clk_i +create_bd_port -dir O spi_clk_o +create_bd_port -dir I spi_sdo_i +create_bd_port -dir O spi_sdo_o +create_bd_port -dir I spi_sdi_i + +# instance: sys_ps7 + +ad_ip_instance processing_system7 sys_ps7 + +# ps7 settings + +ad_ip_parameter sys_ps7 CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} +ad_ip_parameter sys_ps7 CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} +ad_ip_parameter sys_ps7 CONFIG.PCW_PACKAGE_NAME clg400 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_MIO_GPIO_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_ENET0_IO "MIO 16 .. 27" +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_IO "MIO 52 .. 53" +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET_RESET_SELECT "Separate reset pins" +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_RESET_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_RESET_IO "MIO 46" +ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP1 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP2 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK1_PORT 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_EN_RST1_PORT 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ 100.0 +ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 200.0 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO 25 +ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_PERIPHERAL_ENABLE 0 +ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_PERIPHERAL_ENABLE 0 +ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ 50 +ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} +ad_ip_parameter sys_ps7 CONFIG.PCW_I2C1_PERIPHERAL_ENABLE 0 +ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_SPI0_IO EMIO +ad_ip_parameter sys_ps7 CONFIG.PCW_TTC0_PERIPHERAL_ENABLE 0 +ad_ip_parameter sys_ps7 CONFIG.PCW_USE_FABRIC_INTERRUPT 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_MIO_GPIO_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_MIO_GPIO_IO MIO +ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_IO {MIO 47} +ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_INTR 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_MODE REVERSE +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_0_PULLUP {enabled} +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_9_PULLUP {enabled} +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_10_PULLUP {enabled} +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_11_PULLUP {enabled} +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_48_PULLUP {enabled} +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_49_PULLUP {disabled} +ad_ip_parameter sys_ps7 CONFIG.PCW_MIO_53_PULLUP {enabled} + +# DDR MT41K256M16 HA-15E (32M, 16bit, 8banks) + +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF 0 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 0.110 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 0.095 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 0.249 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 0.249 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 0.202 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 0.217 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 0.216 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 0.217 + +ad_ip_instance xlconcat sys_concat_intc +ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 16 + +ad_ip_instance proc_sys_reset sys_rstgen +ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1 + +# system reset/clock definitions + +# add external spi + +ad_ip_instance axi_quad_spi axi_spi +ad_ip_parameter axi_spi CONFIG.C_USE_STARTUP 0 +ad_ip_parameter axi_spi CONFIG.C_NUM_SS_BITS 1 +ad_ip_parameter axi_spi CONFIG.C_SCK_RATIO 8 + +ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0 +ad_connect sys_200m_clk sys_ps7/FCLK_CLK1 +ad_connect sys_cpu_reset sys_rstgen/peripheral_reset +ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn +ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk +ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N + +# interface connections + +ad_connect ddr sys_ps7/DDR +ad_connect gpio_i sys_ps7/GPIO_I +ad_connect gpio_o sys_ps7/GPIO_O +ad_connect gpio_t sys_ps7/GPIO_T +ad_connect fixed_io sys_ps7/FIXED_IO + +# ps7 spi connections + +ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O +ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O +ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O +ad_connect spi0_csn_i sys_ps7/SPI0_SS_I +ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I +ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O +ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I +ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O +ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I + +# axi spi connections + +ad_connect sys_cpu_clk axi_spi/ext_spi_clk +ad_connect spi_csn_i axi_spi/ss_i +ad_connect spi_csn_o axi_spi/ss_o +ad_connect spi_clk_i axi_spi/sck_i +ad_connect spi_clk_o axi_spi/sck_o +ad_connect spi_sdo_i axi_spi/io0_i +ad_connect spi_sdo_o axi_spi/io0_o +ad_connect spi_sdi_i axi_spi/io1_i + +# interrupts + +ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P +ad_connect sys_concat_intc/In15 GND +ad_connect sys_concat_intc/In14 GND +ad_connect sys_concat_intc/In13 GND +ad_connect sys_concat_intc/In12 GND +ad_connect sys_concat_intc/In11 GND +ad_connect sys_concat_intc/In10 GND +ad_connect sys_concat_intc/In9 GND +ad_connect sys_concat_intc/In8 GND +ad_connect sys_concat_intc/In7 GND +ad_connect sys_concat_intc/In6 GND +ad_connect sys_concat_intc/In5 GND +ad_connect sys_concat_intc/In4 GND +ad_connect sys_concat_intc/In3 GND +ad_connect sys_concat_intc/In2 GND +ad_connect sys_concat_intc/In1 GND +ad_connect sys_concat_intc/In0 GND + +# iic + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main + +ad_ip_instance axi_iic axi_iic_main + +ad_connect iic_main axi_iic_main/iic +ad_cpu_interconnect 0x41600000 axi_iic_main +ad_cpu_interrupt ps-15 mb-15 axi_iic_main/iic2intc_irpt + +# ad9361 + +create_bd_port -dir I rx_clk_in +create_bd_port -dir I rx_frame_in +create_bd_port -dir I -from 11 -to 0 rx_data_in + +create_bd_port -dir O tx_clk_out +create_bd_port -dir O tx_frame_out +create_bd_port -dir O -from 11 -to 0 tx_data_out + +create_bd_port -dir O enable +create_bd_port -dir O txnrx +create_bd_port -dir I up_enable +create_bd_port -dir I up_txnrx + +# ad9361 core(s) + +ad_ip_instance axi_ad9361 axi_ad9361 +ad_ip_parameter axi_ad9361 CONFIG.ID 0 +ad_ip_parameter axi_ad9361 CONFIG.CMOS_OR_LVDS_N 1 +ad_ip_parameter axi_ad9361 CONFIG.MODE_1R1T 0 +ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 21 + +ad_ip_instance axi_dmac axi_ad9361_dac_dma +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_SRC 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_DEST 1 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.CYCLIC 1 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_DEST 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 64 + +ad_add_interpolation_filter "tx_fir_interpolator" 8 2 1 {61.44} {7.68} \ + "$ad_hdl_dir/library/util_fir_int/coefile_int.coe" +ad_ip_instance xlslice interp_slice +ad_ip_instance util_upack2 tx_upack + +ad_ip_instance axi_dmac axi_ad9361_adc_dma +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_TYPE_SRC 2 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_DEST 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_SRC 64 + +ad_add_decimation_filter "rx_fir_decimator" 8 2 1 {61.44} {61.44} \ + "$ad_hdl_dir/library/util_fir_int/coefile_int.coe" +ad_ip_instance xlslice decim_slice +ad_ip_instance util_cpack2 cpack + +# connections + +ad_connect rx_clk_in axi_ad9361/rx_clk_in +ad_connect rx_frame_in axi_ad9361/rx_frame_in +ad_connect rx_data_in axi_ad9361/rx_data_in +ad_connect tx_clk_out axi_ad9361/tx_clk_out +ad_connect tx_frame_out axi_ad9361/tx_frame_out +ad_connect tx_data_out axi_ad9361/tx_data_out +ad_connect enable axi_ad9361/enable +ad_connect txnrx axi_ad9361/txnrx +ad_connect up_enable axi_ad9361/up_enable +ad_connect up_txnrx axi_ad9361/up_txnrx + +ad_connect axi_ad9361/tdd_sync GND +ad_connect sys_200m_clk axi_ad9361/delay_clk +ad_connect axi_ad9361/l_clk axi_ad9361/clk + +ad_connect axi_ad9361/l_clk rx_fir_decimator/aclk + +ad_connect axi_ad9361/adc_valid_i0 rx_fir_decimator/valid_in_0 +ad_connect axi_ad9361/adc_enable_i0 rx_fir_decimator/enable_in_0 +ad_connect axi_ad9361/adc_data_i0 rx_fir_decimator/data_in_0 +ad_connect axi_ad9361/adc_valid_q0 rx_fir_decimator/valid_in_1 +ad_connect axi_ad9361/adc_enable_q0 rx_fir_decimator/enable_in_1 +ad_connect axi_ad9361/adc_data_q0 rx_fir_decimator/data_in_1 + +ad_connect axi_ad9361/l_clk cpack/clk +ad_connect axi_ad9361/rst cpack/reset + +ad_connect axi_ad9361/adc_enable_i1 cpack/enable_2 +ad_connect axi_ad9361/adc_data_i1 cpack/fifo_wr_data_2 +ad_connect axi_ad9361/adc_enable_q1 cpack/enable_3 +ad_connect axi_ad9361/adc_data_q1 cpack/fifo_wr_data_3 + +ad_connect cpack/enable_0 rx_fir_decimator/enable_out_0 +ad_connect cpack/enable_1 rx_fir_decimator/enable_out_1 +ad_connect cpack/fifo_wr_data_0 rx_fir_decimator/data_out_0 +ad_connect cpack/fifo_wr_data_1 rx_fir_decimator/data_out_1 +ad_connect rx_fir_decimator/valid_out_0 cpack/fifo_wr_en + +ad_connect axi_ad9361_adc_dma/fifo_wr cpack/packed_fifo_wr +ad_connect axi_ad9361/up_adc_gpio_out decim_slice/Din +ad_connect rx_fir_decimator/active decim_slice/Dout + +ad_connect axi_ad9361/l_clk tx_fir_interpolator/aclk + +ad_connect axi_ad9361/dac_enable_i0 tx_fir_interpolator/dac_enable_0 +ad_connect axi_ad9361/dac_valid_i0 tx_fir_interpolator/dac_valid_0 +ad_connect axi_ad9361/dac_data_i0 tx_fir_interpolator/data_out_0 +ad_connect axi_ad9361/dac_enable_q0 tx_fir_interpolator/dac_enable_1 +ad_connect axi_ad9361/dac_valid_q0 tx_fir_interpolator/dac_valid_1 +ad_connect axi_ad9361/dac_data_q0 tx_fir_interpolator/data_out_1 + +ad_connect axi_ad9361/l_clk tx_upack/clk +ad_connect axi_ad9361/rst tx_upack/reset + +ad_connect tx_upack/fifo_rd_data_0 tx_fir_interpolator/data_in_0 +ad_connect tx_upack/enable_0 tx_fir_interpolator/enable_out_0 +ad_connect tx_upack/fifo_rd_data_1 tx_fir_interpolator/data_in_1 +ad_connect tx_upack/enable_1 tx_fir_interpolator/enable_out_1 + +ad_connect axi_ad9361/dac_enable_i1 tx_upack/enable_2 +ad_connect axi_ad9361/dac_data_i1 tx_upack/fifo_rd_data_2 +ad_connect axi_ad9361/dac_enable_q1 tx_upack/enable_3 +ad_connect axi_ad9361/dac_data_q1 tx_upack/fifo_rd_data_3 + +ad_connect tx_upack/s_axis axi_ad9361_dac_dma/m_axis + +ad_ip_instance util_vector_logic logic_or [list \ + C_OPERATION {or} \ + C_SIZE 1] + +ad_connect logic_or/Op1 tx_fir_interpolator/valid_out_0 +ad_connect logic_or/Op2 axi_ad9361/dac_valid_i1 +ad_connect logic_or/Res tx_upack/fifo_rd_en + +ad_connect axi_ad9361/up_dac_gpio_out interp_slice/Din +ad_connect tx_fir_interpolator/active interp_slice/Dout + +ad_connect axi_ad9361/l_clk axi_ad9361_adc_dma/fifo_wr_clk +ad_connect axi_ad9361/l_clk axi_ad9361_dac_dma/m_axis_aclk +ad_connect cpack/fifo_wr_overflow axi_ad9361/adc_dovf + +# interconnects + +ad_cpu_interconnect 0x79020000 axi_ad9361 +ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma +ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma +ad_cpu_interconnect 0x7C430000 axi_spi + +ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP1 {1} +ad_connect sys_cpu_clk sys_ps7/S_AXI_HP1_ACLK +ad_connect axi_ad9361_adc_dma/m_dest_axi sys_ps7/S_AXI_HP1 + +create_bd_addr_seg -range 0x40000000 -offset 0x00000000 \ + [get_bd_addr_spaces axi_ad9361_adc_dma/m_dest_axi] \ + [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] \ + SEG_sys_ps7_HP1_DDR_LOWOCM + +ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP2 {1} +ad_connect sys_cpu_clk sys_ps7/S_AXI_HP2_ACLK +ad_connect axi_ad9361_dac_dma/m_src_axi sys_ps7/S_AXI_HP2 + +create_bd_addr_seg -range 0x40000000 -offset 0x00000000 \ + [get_bd_addr_spaces axi_ad9361_dac_dma/m_src_axi] \ + [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] \ + SEG_sys_ps7_HP2_DDR_LOWOCM + +ad_connect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi_aclk +ad_connect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi_aclk +ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn +ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn + +# interrupts + +ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq +ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq +ad_cpu_interrupt ps-11 mb-11 axi_spi/ip2intc_irpt + + diff --git a/projects/signalsdrpro/system_constr.xdc b/projects/signalsdrpro/system_constr.xdc new file mode 100644 index 00000000000..59fb6a95bca --- /dev/null +++ b/projects/signalsdrpro/system_constr.xdc @@ -0,0 +1,194 @@ +set_property PACKAGE_PIN p16 [get_ports gpio_en_agc] +# +set_property PACKAGE_PIN n17 [get_ports gpio_resetb] +# + +set_property PACKAGE_PIN t10 [get_ports {gpio_ctl[0]}] +# +set_property PACKAGE_PIN j14 [get_ports {gpio_ctl[1]}] +# +set_property PACKAGE_PIN n15 [get_ports {gpio_ctl[2]}] +# + + +set_property PACKAGE_PIN n16 [get_ports {gpio_ctl[3]}] +# + +set_property PACKAGE_PIN t11 [get_ports {gpio_status[0]}] +# +set_property PACKAGE_PIN t14 [get_ports {gpio_status[1]}] +# +set_property PACKAGE_PIN t15 [get_ports {gpio_status[2]}] +# +set_property PACKAGE_PIN t17 [get_ports {gpio_status[3]}] +# +set_property PACKAGE_PIN t19 [get_ports {gpio_status[4]}] +# +set_property PACKAGE_PIN t20 [get_ports {gpio_status[5]}] + # +set_property PACKAGE_PIN u13 [get_ports {gpio_status[6]}] +# +set_property PACKAGE_PIN v13 [get_ports {gpio_status[7]}] +# + +set_property PACKAGE_PIN n20 [get_ports rx_clk_in] +#rx_clk_in_p +set_property PACKAGE_PIN u18 [get_ports rx_frame_in] +#rx_frame_in_p + +set_property PACKAGE_PIN y19 [get_ports {rx_data_in[0]}] +#rx_data_in_n[0] +set_property PACKAGE_PIN y18 [get_ports {rx_data_in[1]}] +#rx_data_in_p[0] + +set_property PACKAGE_PIN w20 [get_ports {rx_data_in[2]}] +#rx_data_in_n[1] +set_property PACKAGE_PIN v20 [get_ports {rx_data_in[3]}] + #rx_data_in_p[1] + +set_property PACKAGE_PIN w19 [get_ports {rx_data_in[4]}] +#rx_data_in_n[2] +set_property PACKAGE_PIN w18 [get_ports {rx_data_in[5]}] +#rx_data_in_p[2] + +set_property PACKAGE_PIN r17 [get_ports {rx_data_in[6]}] +#rx_data_in_n[3] +set_property PACKAGE_PIN r16 [get_ports {rx_data_in[7]}] +#rx_data_in_p[3] + +set_property PACKAGE_PIN v18 [get_ports {rx_data_in[8]}] +#rx_data_in_n[4] +set_property PACKAGE_PIN v17 [get_ports {rx_data_in[9]}] +#rx_data_in_p[4] + +set_property PACKAGE_PIN w16 [get_ports {rx_data_in[10]}] +#rx_data_in_n[5] +set_property PACKAGE_PIN v16 [get_ports {rx_data_in[11]}] +#rx_data_in_p[5] + +set_property PACKAGE_PIN y17 [get_ports {tx_data_out[0]}] +#tx_data_out_n[0] +set_property PACKAGE_PIN y16 [get_ports {tx_data_out[1]}] +#tx_data_out_p[0] + +set_property PACKAGE_PIN u15 [get_ports {tx_data_out[2]}] +#tx_data_out_n[1] +set_property PACKAGE_PIN u14 [get_ports {tx_data_out[3]}] +#tx_data_out_p[1] + +set_property PACKAGE_PIN w15 [get_ports {tx_data_out[4]}] +#tx_data_out_n[2] +set_property PACKAGE_PIN v15 [get_ports {tx_data_out[5]}] +#tx_data_out_p[2] + +set_property PACKAGE_PIN y14 [get_ports {tx_data_out[6]}] +#tx_data_out_n[3] +set_property PACKAGE_PIN w14 [get_ports {tx_data_out[7]}] +#tx_data_out_p[3] + +set_property PACKAGE_PIN w13 [get_ports {tx_data_out[8]}] +#tx_data_out_n[4] +set_property PACKAGE_PIN v12 [get_ports {tx_data_out[9]}] +#tx_data_out_p[4] + +set_property PACKAGE_PIN u12 [get_ports {tx_data_out[10]}] +#tx_data_out_n[5] +set_property PACKAGE_PIN t12 [get_ports {tx_data_out[11]}] +#tx_data_out_p[5] + +set_property PACKAGE_PIN n18 [get_ports tx_clk_out] +#tx_clk_out_p +set_property PACKAGE_PIN t16 [get_ports tx_frame_out] +#tx_frame_out_p + + + +set_property PACKAGE_PIN p14 [get_ports txnrx] +set_property PACKAGE_PIN r18 [get_ports enable] +set_property PACKAGE_PIN m14 [get_ports iic_scl] +set_property PACKAGE_PIN m15 [get_ports iic_sda] +set_property PACKAGE_PIN p18 [get_ports spi_csn] +set_property PACKAGE_PIN r14 [get_ports spi_clk] +set_property PACKAGE_PIN p15 [get_ports spi_mosi] +set_property PACKAGE_PIN r19 [get_ports spi_miso] + + + + + +set_property IOSTANDARD LVCMOS18 [get_ports gpio_en_agc] +set_property IOSTANDARD LVCMOS18 [get_ports gpio_resetb] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_ctl[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_ctl[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_ctl[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_ctl[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_status[7]}] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_status[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_status[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_status[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_status[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_status[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_status[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {gpio_status[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports iic_scl] +set_property IOSTANDARD LVCMOS18 [get_ports iic_sda] + +set_property IOSTANDARD LVCMOS18 [get_ports spi_clk] +set_property IOSTANDARD LVCMOS18 [get_ports spi_csn] +set_property IOSTANDARD LVCMOS18 [get_ports spi_miso] +set_property IOSTANDARD LVCMOS18 [get_ports spi_mosi] +set_property IOSTANDARD LVCMOS18 [get_ports clk_out] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[11]}] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[10]}] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[9]}] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[8]}] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[7]}] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {rx_data_in[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[11]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[10]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[9]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[8]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[7]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {tx_data_out[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports enable] +set_property IOSTANDARD LVCMOS18 [get_ports rx_clk_in] +set_property IOSTANDARD LVCMOS18 [get_ports rx_frame_in] +set_property IOSTANDARD LVCMOS18 [get_ports tx_clk_out] +set_property IOSTANDARD LVCMOS18 [get_ports tx_frame_out] +set_property IOSTANDARD LVCMOS18 [get_ports txnrx] + +create_clock -name rx_clk -period 16.27 [get_ports rx_clk_in] +create_clock -name clk_fpga_0 -period 10 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]"] +create_clock -name clk_fpga_1 -period 5 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]"] + +create_clock -name spi0_clk -period 40 [get_pins -hier */EMIOSPI0SCLKO] + +set_input_jitter clk_fpga_0 0.3 +set_input_jitter clk_fpga_1 0.15 + + +set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS18} [get_ports tx1_en] +set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS18} [get_ports tx2_en] +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18} [get_ports sel_clk_src] + +set_property -dict {PACKAGE_PIN a20 IOSTANDARD LVCMOS18} [get_ports rx1_led ] +set_property -dict {PACKAGE_PIN b19 IOSTANDARD LVCMOS18} [get_ports rx2_led ] + + + + + + + diff --git a/projects/signalsdrpro/system_project.tcl b/projects/signalsdrpro/system_project.tcl new file mode 100644 index 00000000000..0b0c68777f2 --- /dev/null +++ b/projects/signalsdrpro/system_project.tcl @@ -0,0 +1,17 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z020clg400-1" +adi_project signalsdrpi + +adi_project_files signalsdrpi [list \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_iobuf.v"] + +set_property is_enabled false [get_files *system_sys_ps7_0.xdc] +adi_project_run signalsdrpi +source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl + diff --git a/projects/signalsdrpro/system_top.v b/projects/signalsdrpro/system_top.v new file mode 100644 index 00000000000..64078c818c0 --- /dev/null +++ b/projects/signalsdrpro/system_top.v @@ -0,0 +1,185 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 1:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 1:0] ddr_dqs_n, + inout [ 1:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [31:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout iic_scl, + inout iic_sda, + + input rx_clk_in, + input rx_frame_in, + input [11:0] rx_data_in, + output tx_clk_out, + output tx_frame_out, + output [11:0] tx_data_out, + + output enable, + output txnrx, + input clk_out, + + inout gpio_resetb, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, + + output spi_csn , + output spi_clk , + output spi_mosi , + input spi_miso , + output tx1_en , tx2_en , sel_clk_src, + output rx1_led,rx2_led + ); + + +assign {tx1_en,tx2_en,sel_clk_src} = 3'b101 ; +assign rx1_led = 1'b1 ; +assign rx2_led = 1'b0 ; + + wire pl_spi_clk_o ; + wire pl_spi_mosi ; + wire pl_spi_miso ; + + // internal signals + + wire [24:0] gpio_i; + wire [24:0] gpio_o; + wire [24:0] gpio_t; + + // instantiations + + ad_iobuf #(.DATA_WIDTH(14)) i_iobuf ( + .dio_t (gpio_t[13:0]), + .dio_i (gpio_o[13:0]), + .dio_o (gpio_i[13:0]), + .dio_p ({ gpio_resetb, // 13:13 + gpio_en_agc, // 12:12 + gpio_ctl, // 11: 8 + gpio_status})); // 7: 0 + + assign gpio_i[24:14] = gpio_o[24:14]; + + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .rx_clk_in (rx_clk_in), + .rx_data_in (rx_data_in), + .rx_frame_in (rx_frame_in), + + // .ltc2630_mosi_0(ltc2630_mosi_0), + // .ltc2630_ncs_0(ltc2630_ncs_0), + // .ltc2630_sclk_0(ltc2630_sclk_0), + + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + + .spi_clk_i(1'b0), + .spi_clk_o(pl_spi_clk_o), + .spi_csn_i(1'b1), + .spi_csn_o(), + .spi_sdi_i(pl_spi_miso), + .spi_sdo_i(1'b0), + .spi_sdo_o(pl_spi_mosi), + + .tx_clk_out (tx_clk_out), + .tx_data_out (tx_data_out), + .tx_frame_out (tx_frame_out), + .txnrx (txnrx), + .up_enable (gpio_o[15]), + .up_txnrx (gpio_o[16])); + +endmodule + +// *************************************************************************** +// *************************************************************************** + +