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acsawdeyacsawdey
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Fix operand order to subf for p10 fusion.
This certainly causes a bootstrap miscompare, and might also be responsible for PR/100820. The operands to subf were reversed in the logical-add/sub fusion patterns, and I screwed up my bootstrap test which is how it ended up getting committed. gcc/ChangeLog * config/rs6000/genfusion.pl (gen_logical_addsubf): Fix input order to subf instruction. * config/rs6000/fusion.md: Regenerate.
1 parent 0614bbb commit 52e1306

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+43
-41
lines changed

2 files changed

+43
-41
lines changed

‎gcc/config/rs6000/fusion.md‎

Lines changed: 32 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -1733,10 +1733,10 @@
17331733
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
17341734
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
17351735
"@
1736-
and %3,%1,%0\;subf %3,%3,%2
1737-
and %3,%1,%0\;subf %3,%3,%2
1738-
and %3,%1,%0\;subf %3,%3,%2
1739-
and %4,%1,%0\;subf %3,%4,%2"
1736+
and %3,%1,%0\;subf %3,%2,%3
1737+
and %3,%1,%0\;subf %3,%2,%3
1738+
and %3,%1,%0\;subf %3,%2,%3
1739+
and %4,%1,%0\;subf %3,%2,%4"
17401740
[(set_attr "type" "fused_arith_logical")
17411741
(set_attr "cost" "6")
17421742
(set_attr "length" "8")])
@@ -1751,10 +1751,10 @@
17511751
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
17521752
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
17531753
"@
1754-
nand %3,%1,%0\;subf %3,%3,%2
1755-
nand %3,%1,%0\;subf %3,%3,%2
1756-
nand %3,%1,%0\;subf %3,%3,%2
1757-
nand %4,%1,%0\;subf %3,%4,%2"
1754+
nand %3,%1,%0\;subf %3,%2,%3
1755+
nand %3,%1,%0\;subf %3,%2,%3
1756+
nand %3,%1,%0\;subf %3,%2,%3
1757+
nand %4,%1,%0\;subf %3,%2,%4"
17581758
[(set_attr "type" "fused_arith_logical")
17591759
(set_attr "cost" "6")
17601760
(set_attr "length" "8")])
@@ -1769,10 +1769,10 @@
17691769
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
17701770
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
17711771
"@
1772-
nor %3,%1,%0\;subf %3,%3,%2
1773-
nor %3,%1,%0\;subf %3,%3,%2
1774-
nor %3,%1,%0\;subf %3,%3,%2
1775-
nor %4,%1,%0\;subf %3,%4,%2"
1772+
nor %3,%1,%0\;subf %3,%2,%3
1773+
nor %3,%1,%0\;subf %3,%2,%3
1774+
nor %3,%1,%0\;subf %3,%2,%3
1775+
nor %4,%1,%0\;subf %3,%2,%4"
17761776
[(set_attr "type" "fused_arith_logical")
17771777
(set_attr "cost" "6")
17781778
(set_attr "length" "8")])
@@ -1787,10 +1787,10 @@
17871787
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
17881788
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
17891789
"@
1790-
or %3,%1,%0\;subf %3,%3,%2
1791-
or %3,%1,%0\;subf %3,%3,%2
1792-
or %3,%1,%0\;subf %3,%3,%2
1793-
or %4,%1,%0\;subf %3,%4,%2"
1790+
or %3,%1,%0\;subf %3,%2,%3
1791+
or %3,%1,%0\;subf %3,%2,%3
1792+
or %3,%1,%0\;subf %3,%2,%3
1793+
or %4,%1,%0\;subf %3,%2,%4"
17941794
[(set_attr "type" "fused_arith_logical")
17951795
(set_attr "cost" "6")
17961796
(set_attr "length" "8")])
@@ -1805,10 +1805,10 @@
18051805
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
18061806
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
18071807
"@
1808-
and %3,%1,%0\;subf %3,%2,%3
1809-
and %3,%1,%0\;subf %3,%2,%3
1810-
and %3,%1,%0\;subf %3,%2,%3
1811-
and %4,%1,%0\;subf %3,%2,%4"
1808+
and %3,%1,%0\;subf %3,%3,%2
1809+
and %3,%1,%0\;subf %3,%3,%2
1810+
and %3,%1,%0\;subf %3,%3,%2
1811+
and %4,%1,%0\;subf %3,%4,%2"
18121812
[(set_attr "type" "fused_arith_logical")
18131813
(set_attr "cost" "6")
18141814
(set_attr "length" "8")])
@@ -1823,10 +1823,10 @@
18231823
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
18241824
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
18251825
"@
1826-
nand %3,%1,%0\;subf %3,%2,%3
1827-
nand %3,%1,%0\;subf %3,%2,%3
1828-
nand %3,%1,%0\;subf %3,%2,%3
1829-
nand %4,%1,%0\;subf %3,%2,%4"
1826+
nand %3,%1,%0\;subf %3,%3,%2
1827+
nand %3,%1,%0\;subf %3,%3,%2
1828+
nand %3,%1,%0\;subf %3,%3,%2
1829+
nand %4,%1,%0\;subf %3,%4,%2"
18301830
[(set_attr "type" "fused_arith_logical")
18311831
(set_attr "cost" "6")
18321832
(set_attr "length" "8")])
@@ -1841,10 +1841,10 @@
18411841
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
18421842
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
18431843
"@
1844-
nor %3,%1,%0\;subf %3,%2,%3
1845-
nor %3,%1,%0\;subf %3,%2,%3
1846-
nor %3,%1,%0\;subf %3,%2,%3
1847-
nor %4,%1,%0\;subf %3,%2,%4"
1844+
nor %3,%1,%0\;subf %3,%3,%2
1845+
nor %3,%1,%0\;subf %3,%3,%2
1846+
nor %3,%1,%0\;subf %3,%3,%2
1847+
nor %4,%1,%0\;subf %3,%4,%2"
18481848
[(set_attr "type" "fused_arith_logical")
18491849
(set_attr "cost" "6")
18501850
(set_attr "length" "8")])
@@ -1859,10 +1859,10 @@
18591859
(clobber (match_scratch:GPR 4 "=X,X,X,&r"))]
18601860
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LOGADD)"
18611861
"@
1862-
or %3,%1,%0\;subf %3,%2,%3
1863-
or %3,%1,%0\;subf %3,%2,%3
1864-
or %3,%1,%0\;subf %3,%2,%3
1865-
or %4,%1,%0\;subf %3,%2,%4"
1862+
or %3,%1,%0\;subf %3,%3,%2
1863+
or %3,%1,%0\;subf %3,%3,%2
1864+
or %3,%1,%0\;subf %3,%3,%2
1865+
or %4,%1,%0\;subf %3,%4,%2"
18661866
[(set_attr "type" "fused_arith_logical")
18671867
(set_attr "cost" "6")
18681868
(set_attr "length" "8")])

‎gcc/config/rs6000/genfusion.pl‎

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -166,7 +166,7 @@ sub gen_logical_addsubf
166166
$outer_op, $outer_comp, $outer_inv, $outer_rtl, $inner, @inner_ops,
167167
$inner_comp, $inner_inv, $inner_rtl, $inner_op, $both_commute, $c4,
168168
$bc, $inner_arg0, $inner_arg1, $inner_exp, $outer_arg2, $outer_exp,
169-
$target_flag, $ftype, $insn, $is_rsubf, $outer_32, $outer_42,
169+
$target_flag, $ftype, $insn, $is_subf, $is_rsubf, $outer_32, $outer_42,
170170
$outer_name, $fuse_type);
171171
KIND: foreach $kind ('scalar','vector') {
172172
@outer_ops = @logicals;
@@ -188,11 +188,10 @@ sub gen_logical_addsubf
188188
$c4 = "${constraint},${constraint},${constraint},${constraint}";
189189
OUTER: foreach $outer ( @outer_ops ) {
190190
$outer_name = "${vchr}${outer}";
191-
if ( $outer eq "rsubf" ) {
192-
$is_rsubf = 1;
191+
$is_subf = ( $outer eq "subf" );
192+
$is_rsubf = ( $outer eq "rsubf" );
193+
if ( $is_rsubf ) {
193194
$outer = "subf";
194-
} else {
195-
$is_rsubf = 0;
196195
}
197196
$outer_op = "${vchr}${outer}";
198197
$outer_comp = $complement{$outer};
@@ -241,16 +240,19 @@ sub gen_logical_addsubf
241240
if ( ($outer_comp & 2) == 2 ) {
242241
$inner_exp = "(not:${mode} $inner_exp)";
243242
}
243+
if ( $is_subf ) {
244+
$outer_32 = "%2,%3";
245+
$outer_42 = "%2,%4";
246+
} else {
247+
$outer_32 = "%3,%2";
248+
$outer_42 = "%4,%2";
249+
}
244250
if ( $is_rsubf == 1 ) {
245251
$outer_exp = "(${outer_rtl}:${mode} ${outer_arg2}
246252
${inner_exp})";
247-
$outer_32 = "%2,%3";
248-
$outer_42 = "%2,%4";
249253
} else {
250254
$outer_exp = "(${outer_rtl}:${mode} ${inner_exp}
251255
${outer_arg2})";
252-
$outer_32 = "%3,%2";
253-
$outer_42 = "%4,%2";
254256
}
255257
if ( $outer_inv == 1 ) {
256258
$outer_exp = "(not:${mode} $outer_exp)";

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