22
33** Goal: Finish the interrupts implementation and CPU timer**
44
5- Remap the PIC
6- -------------
7-
85When the CPU boots, the PIC maps IRQs 0-7 to INT 0x8-0xF
96and IRQs 8-15 to INT 0x70-0x77. This conflicts with the ISRs
107we programmed last lesson. Since we programmed ISRs 0-31,
@@ -14,7 +11,8 @@ The PICs are communicated with via I/O ports (see lesson 15).
1411The Master PIC has command 0x20 and data 0x21, while the slave has
1512command 0xA0 and data 0xA1.
1613
17- The code for remapping the PICs is obfuscated, so check
14+ The code for remapping the PICs is weird and includes
15+ some masks, so check
1816[ this article] ( http://www.osdev.org/wiki/PIC ) if you're curious.
1917Otherwise, just look at ` cpu/isr.c ` , new code after we set the IDT
2018gates for the ISRs. After that, we add the IDT gates for IRQs.
@@ -30,5 +28,10 @@ We then create this `irq_common_stub` which is very similar to the ISR one.
3028It is located at the top of ` interrupt.asm ` , and it also defines
3129a new ` [extern irq_handler] `
3230
33- Now back to C code.
34- - Write the ` irq_handler ` in C:
31+ Now back to C code, to write the ` irq_handler() ` in ` isr.c ` . It sends some
32+ EOIs to the PICs and calls the appropriate handler, which is stored in an array
33+ named ` interrupt_handlers ` and defined at the top of the file. The new structs
34+ are defined in ` isr.h ` . We will also use a simple function to register
35+ the interrupt handlers.
36+
37+ That was a lot of work, but now we can define our first IRQ handler!
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