By Jose Tejada (@topapate)
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Project source code hosted at http://www.github.com/jotego/jtcores License: GPL3, you are obligued to publish your code if you use mine
Yes, you always wanted to have an arcade board at home. First you couldn't get it because your parents somehow did not understand you. Then you grow up and your wife doesn't understand you either. Don't worry, JT cores are here to the rescue.
I hope you will have as much fun with this project as I had while working on it!
This FPGA core is compatible with the following arcade PCBs:
- The Simpsons
- Parodius da!
- Vendetta (Crime Fighters 2)
This game does not use DIP switches but a small EEPROM to save the configuration. Access to the configuration by pressing F2 on your keyboard or pressing button 1 and coin in the Analogue Pocket. Follow the game menu to alter the configuration from that point on.
Derived from Caius original files.
053994 at 11C:
/i7 = /AS & /INIT & /A15 & /A14 & /A13 & A12 & A11 & A10 & /W0C1 & W0C0 +
/AS & /INIT & /A15 & /A14 & /A13 & A12 & A11 & A10 & W0C1 +
/AS & /A15 & /A14 & /A13 & A12 & A11 & A10 & /W0C0 +
/AS & INIT & /A15 & /A14 & A13 & /W0C1 +
/AS & INIT & /A15 & /A14 & /A13 & /W0C0 +
/AS & INIT & /A15 & /A14 & /A13 & A12
# 1C00~1FFFF and if /INIT 7C00~7FFF
/i6 = /AS & /INIT & /A15 & A14 & A13 & A12 & A11 & A10 +
/AS & /A15 & /A14 & /A13 & A12 & A11 & A10 =>
=>/AS & ( A[15:10]==7 || (A[15:10]=='h1F && /INIT))
/WORKCS = /AS & INIT & /A15 & A14 & /A13
/OBJCS = /AS & INIT & /A15 & /A14 & A13 & W0C1
/COLOCS = /AS & INIT & /A15 & /A14 & /A13 & /A12 & W0C0
/PROGCS = /AS & INIT & A14 & A13 & BK4 +
/AS & A15
/BNKCS = /AS & INIT & /A15 & A14 & A13 & /BK4
053995 at 11D:
/EEPROM = /AS & //i6 & //i7 & A9 & A8 & A7 & /A6 & /A5 & /A4
/JOYSTK = /AS & //i6 & //i7 & A9 & A8 & A7 & /A6 & /A5 & A4
/OBJREG = /AS & //i6 & //i7 & A9 & A8 & A7 & /A6 & A5 & /A4 # A[9:4]==111010
/PCUCS = /AS & //i6 & //i7 & A9 & A8 & A7 & /A6 & A5 & A4
/IOCS = /AS & //i6 & //i7 & A9 & A8 & A7 & A6 & /A5 & /A4
/VRAMCS = /AS & //i6 & /A9 +
/AS & //i6 & /A8 +
/AS & //i6 & /A7 +
/AS & //i6 & A6 & A5 +
/AS & //i6 & A6 & A4
/AS & //i6 & /i7 +
/AS & /i6 & //i7 +
Based on 051960 (previous generation of sprite hardware) and MAME documentation
256 sprites, 8x 16-bit data per sprite Sprite table = 25682=4096 = (0x1000) DMA transfer takes 297.5us, and occurs 1 line after VS finishes The PCB may detect end of the DMA transfer and set an interrupt on it
The chip can operate in either 8-bit or 16-bit mode, so it can connect to an 8-bit CPU (and RAM) or a 16-bit system Is the 8-bit mode set by an MMR? DMA A0 line max speed is 3MHz (166ns low, 166ns high) in 8-bit mode, not all 8 positions have low & high bytes read if all were read, DMA should last for 682.67us but it is 596.9us so 14 out of 16 bytes are read for each object MSB is read first, so the order is 1,0,3,2,5,4,7,6,9,8,B,A,D,C Note that F,E are missing. Could they be enabled with some MMR?
In X-Men (16-bit mode) DMA lasts for 298.7us, half the time than in 8-bit mode (595us, accounting for some inaccuracy in the measurement)
This implementation has a first phase that clears out the internal buffer and then sprites are copied by their priority code into memory, so they naturally fall in order. The original one likely has the same clear phase but executed right after the vs edge and lasting for a whole line. The DMA timing has been matched with the original, despite of the different buffer-clear logic
Special thanks to Museo Arcade Vintage for lending their Simpsons PCB to us during development.
Thanks to August 2023 Patreon supporters
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