diff --git a/src/coreclr/vm/amd64/JitHelpers_Fast.asm b/src/coreclr/vm/amd64/JitHelpers_Fast.asm
index 5c654ab72a0438..dd5b891a441341 100644
--- a/src/coreclr/vm/amd64/JitHelpers_Fast.asm
+++ b/src/coreclr/vm/amd64/JitHelpers_Fast.asm
@@ -279,7 +279,7 @@ ifdef WRITE_BARRIER_CHECK
         ; Check that our adjusted destination is somewhere in the shadow gc
         add     r10, [g_GCShadow]
         cmp     r10, [g_GCShadowEnd]
-        ja      NoShadow
+        jnb     NoShadow
 
         ; Write ref into real GC
         mov     [rdi], rcx
diff --git a/src/coreclr/vm/amd64/JitHelpers_Slow.asm b/src/coreclr/vm/amd64/JitHelpers_Slow.asm
index 50fe4c64b66f9f..b864801bfd60c8 100644
--- a/src/coreclr/vm/amd64/JitHelpers_Slow.asm
+++ b/src/coreclr/vm/amd64/JitHelpers_Slow.asm
@@ -81,7 +81,7 @@ ifdef WRITE_BARRIER_CHECK
         ; Check that our adjusted destination is somewhere in the shadow gc
         add     r10, [g_GCShadow]
         cmp     r10, [g_GCShadowEnd]
-        ja      NoShadow
+        jnb     NoShadow
 
         ; Write ref into real GC; see comment below about possibility of AV
         mov     [rcx], rdx
diff --git a/src/coreclr/vm/amd64/jithelpers_fast.S b/src/coreclr/vm/amd64/jithelpers_fast.S
index 9b582103509c2a..32890b471b26c1 100644
--- a/src/coreclr/vm/amd64/jithelpers_fast.S
+++ b/src/coreclr/vm/amd64/jithelpers_fast.S
@@ -300,7 +300,7 @@ LEAF_ENTRY JIT_ByRefWriteBarrier, _TEXT
         add     r10, [rax]
         PREPARE_EXTERNAL_VAR g_GCShadowEnd, rax
         cmp     r10, [rax]
-        ja      NoShadow_ByRefWriteBarrier
+        jnb     NoShadow_ByRefWriteBarrier
 
         // Write ref into real GC
         mov     [rdi], rcx
diff --git a/src/coreclr/vm/amd64/jithelpers_slow.S b/src/coreclr/vm/amd64/jithelpers_slow.S
index 1757a7d1c5adeb..c0c80324710c64 100644
--- a/src/coreclr/vm/amd64/jithelpers_slow.S
+++ b/src/coreclr/vm/amd64/jithelpers_slow.S
@@ -28,7 +28,7 @@ LEAF_ENTRY JIT_WriteBarrier_Debug, _TEXT
         add     r10, [rax]
         PREPARE_EXTERNAL_VAR g_GCShadowEnd, r11
         cmp     r10, [r11]
-        ja      NoShadow
+        jnb     NoShadow
 
         // Write ref into real GC// see comment below about possibility of AV
         mov     [rdi], rsi
diff --git a/src/coreclr/vm/arm64/asmhelpers.S b/src/coreclr/vm/arm64/asmhelpers.S
index d2a4c94fe1fab1..574d30068f0994 100644
--- a/src/coreclr/vm/arm64/asmhelpers.S
+++ b/src/coreclr/vm/arm64/asmhelpers.S
@@ -420,7 +420,7 @@ LOCAL_LABEL(CheckCardTable):
     // branch to exit is taken.
     ccmp x15, x12, #0x2, hs
 
-    bhi  LOCAL_LABEL(Exit)
+    bhs  LOCAL_LABEL(Exit)
 
 LOCAL_LABEL(SkipEphemeralCheck):
     // Check if we need to update the card table
diff --git a/src/coreclr/vm/arm64/asmhelpers.asm b/src/coreclr/vm/arm64/asmhelpers.asm
index 6b2042d41f9e33..8718a90d813ba4 100644
--- a/src/coreclr/vm/arm64/asmhelpers.asm
+++ b/src/coreclr/vm/arm64/asmhelpers.asm
@@ -473,15 +473,19 @@ ShadowUpdateDisabled
 CheckCardTable
         ; Branch to Exit if the reference is not in the Gen0 heap
         ;
-        adr      x12,  wbs_ephemeral_low
-        ldp      x12,  x16, [x12]
+        ldr      x12,  wbs_ephemeral_low
         cbz      x12,  SkipEphemeralCheck
-
         cmp      x15,  x12
-        blo      Exit
 
-        cmp      x15,  x16
-        bhi      Exit
+        ldr      x12,  wbs_ephemeral_high
+
+        ; Compare against the upper bound if the previous comparison indicated
+        ; that the destination address is greater than or equal to the lower
+        ; bound. Otherwise, set the C flag (specified by the 0x2) so that the
+        ; branch to exit is taken.
+        ccmp     x15,  x12, #0x2, hs
+
+        bhs      Exit
 
 SkipEphemeralCheck
         ; Check if we need to update the card table
diff --git a/src/coreclr/vm/i386/jithelp.S b/src/coreclr/vm/i386/jithelp.S
index e1733810a1a76e..d61dfb3dd2fa00 100644
--- a/src/coreclr/vm/i386/jithelp.S
+++ b/src/coreclr/vm/i386/jithelp.S
@@ -109,7 +109,7 @@ PATCH_LABEL JIT_DebugWriteBarrier\rg
     mov     [edx], edx
     cmp     ecx, [edx]
     pop     edx
-    ja      LOCAL_LABEL(WriteBarrier_NoShadow_\rg)
+    jae     LOCAL_LABEL(WriteBarrier_NoShadow_\rg)
 
     // TODO: In Orcas timeframe if we move to P4+ only on X86 we should enable
     // mfence barriers on either side of these two writes to make sure that
@@ -281,7 +281,7 @@ LEAF_ENTRY JIT_ByRefWriteBarrier, _TEXT
     mov     eax, [eax]
     cmp     edx, [eax]
     pop     eax
-    ja      LOCAL_LABEL(ByRefWriteBarrier_NoShadow)
+    jae     LOCAL_LABEL(ByRefWriteBarrier_NoShadow)
 
     // TODO: In Orcas timeframe if we move to P4+ only on X86 we should enable
     // mfence barriers on either side of these two writes to make sure that
diff --git a/src/coreclr/vm/i386/jithelp.asm b/src/coreclr/vm/i386/jithelp.asm
index 8c02d35a382339..054e6ee236e381 100644
--- a/src/coreclr/vm/i386/jithelp.asm
+++ b/src/coreclr/vm/i386/jithelp.asm
@@ -193,7 +193,7 @@ ifdef WRITE_BARRIER_CHECK
         jb      WriteBarrier_NoShadow_&rg
         add     ecx, [g_GCShadow]
         cmp     ecx, [g_GCShadowEnd]
-        ja      WriteBarrier_NoShadow_&rg
+        jae     WriteBarrier_NoShadow_&rg
 
         ; TODO: In Orcas timeframe if we move to P4+ only on X86 we should enable
         ; mfence barriers on either side of these two writes to make sure that
@@ -330,7 +330,7 @@ ifdef WRITE_BARRIER_CHECK
         jb      ByRefWriteBarrier_NoShadow
         add     edx, [g_GCShadow]
         cmp     edx, [g_GCShadowEnd]
-        ja      ByRefWriteBarrier_NoShadow
+        jae     ByRefWriteBarrier_NoShadow
 
         ; TODO: In Orcas timeframe if we move to P4+ only on X86 we should enable
         ; mfence barriers on either side of these two writes to make sure that