From 38d89a60a704e1a351613a7441fd26f3eb9e3199 Mon Sep 17 00:00:00 2001 From: Kirill Mikhailov Date: Mon, 29 Jul 2024 16:31:54 +0200 Subject: [PATCH 1/8] WIP state --- esp-hal/src/rtc_cntl/sleep/esp32c3.rs | 69 +++++++++---------- esp-hal/src/rtc_cntl/sleep/esp32s3.rs | 70 +++++++++---------- esp-hal/src/soc/esp32c6/radio_clocks.rs | 6 +- esp-hal/src/soc/esp32h2/radio_clocks.rs | 6 +- esp-storage/src/esp32.rs | 90 +++++++++++-------------- esp-wifi/src/wifi/os_adapter_esp32.rs | 25 +++---- examples/src/bin/wifi_dhcp.rs | 4 +- 7 files changed, 126 insertions(+), 144 deletions(-) diff --git a/esp-hal/src/rtc_cntl/sleep/esp32c3.rs b/esp-hal/src/rtc_cntl/sleep/esp32c3.rs index f8fdcf3fac1..783dd8ffe72 100644 --- a/esp-hal/src/rtc_cntl/sleep/esp32c3.rs +++ b/esp-hal/src/rtc_cntl/sleep/esp32c3.rs @@ -387,42 +387,16 @@ impl Default for RtcSleepConfig { } } -const DR_REG_NRX_BASE: u32 = 0x6001CC00; -const DR_REG_FE_BASE: u32 = 0x60006000; -const DR_REG_FE2_BASE: u32 = 0x60005000; - -const NRXPD_CTRL: u32 = DR_REG_NRX_BASE + 0x00d4; -const FE_GEN_CTRL: u32 = DR_REG_FE_BASE + 0x0090; -const FE2_TX_INTERP_CTRL: u32 = DR_REG_FE2_BASE + 0x00f0; - const SYSCON_SRAM_POWER_UP: u8 = 0x0000000F; const SYSCON_ROM_POWER_UP: u8 = 0x00000003; -const NRX_RX_ROT_FORCE_PU: u32 = 1 << 5; -const NRX_VIT_FORCE_PU: u32 = 1 << 3; -const NRX_DEMAP_FORCE_PU: u32 = 1 << 1; - -const FE_IQ_EST_FORCE_PU: u32 = 1 << 5; -const FE2_TX_INF_FORCE_PU: u32 = 1 << 10; - -fn modify_register(reg: u32, mask: u32, value: u32) { - let reg = reg as *mut u32; - - unsafe { reg.write_volatile((reg.read_volatile() & !mask) | value) }; -} - -fn register_modify_bits(reg: u32, bits: u32, set: bool) { - if set { - modify_register(reg, bits, bits); - } else { - modify_register(reg, bits, 0); - } -} - fn rtc_sleep_pu(val: bool) { let rtc_cntl = unsafe { &*esp32c3::RTC_CNTL::ptr() }; let syscon = unsafe { &*esp32c3::APB_CTRL::ptr() }; let bb = unsafe { &*esp32c3::BB::ptr() }; + let nrx = unsafe { &*esp32s3::NRX::ptr() }; + let fe = unsafe { &*esp32s3::FE::ptr() }; + let fe2 = unsafe { &*esp32s3::FE2::ptr() }; rtc_cntl .dig_pwc() @@ -440,15 +414,38 @@ fn rtc_sleep_pu(val: bool) { bb.bbpd_ctrl() .modify(|_r, w| w.fft_force_pu().bit(val).dc_est_force_pu().bit(val)); - register_modify_bits( - NRXPD_CTRL, - NRX_RX_ROT_FORCE_PU | NRX_VIT_FORCE_PU | NRX_DEMAP_FORCE_PU, - val, - ); - register_modify_bits(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, val); + if val { + nrx.nrxpd_ctrl().modify(|_, w| { + w.rx_rot_force_pu() + .set_bit() + .vit_force_pu() + .set_bit() + .demap_force_pu() + .set_bit() + }); + } else { + nrx.nrxpd_ctrl().modify(|_, w| { + w.rx_rot_force_pu() + .clear_bit() + .vit_force_pu() + .clear_bit() + .demap_force_pu() + .clear_bit() + }); + } - register_modify_bits(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, val); + if val { + fe.gen_ctrl().modify(|_, w| w.iq_est_force_pu().set_bit()); + } else { + fe.gen_ctrl().modify(|_, w| w.iq_est_force_pu().clear_bit()); + } + + if val { + fe2.tx_interp_ctrl().modify(|_, w| w.tx_inf_force_pu().set_bit()); + } else { + fe2.tx_interp_ctrl().modify(|_, w| w.tx_inf_force_pu().clear_bit()); + } syscon.mem_power_up().modify(|_r, w| unsafe { w.sram_power_up() diff --git a/esp-hal/src/rtc_cntl/sleep/esp32s3.rs b/esp-hal/src/rtc_cntl/sleep/esp32s3.rs index 34011d6cf93..89737903fdf 100644 --- a/esp-hal/src/rtc_cntl/sleep/esp32s3.rs +++ b/esp-hal/src/rtc_cntl/sleep/esp32s3.rs @@ -328,42 +328,16 @@ impl Default for RtcSleepConfig { } } -const DR_REG_NRX_BASE: u32 = 0x6001CC00; -const DR_REG_FE_BASE: u32 = 0x60006000; -const DR_REG_FE2_BASE: u32 = 0x60005000; - -const NRXPD_CTRL: u32 = DR_REG_NRX_BASE + 0x00d4; -const FE_GEN_CTRL: u32 = DR_REG_FE_BASE + 0x0090; -const FE2_TX_INTERP_CTRL: u32 = DR_REG_FE2_BASE + 0x00f0; - const SYSCON_SRAM_POWER_UP: u16 = 0x7FF; const SYSCON_ROM_POWER_UP: u8 = 0x7; -const NRX_RX_ROT_FORCE_PU: u32 = 1 << 5; -const NRX_VIT_FORCE_PU: u32 = 1 << 3; -const NRX_DEMAP_FORCE_PU: u32 = 1 << 1; - -const FE_IQ_EST_FORCE_PU: u32 = 1 << 5; -const FE2_TX_INF_FORCE_PU: u32 = 1 << 10; - -fn modify_register(reg: u32, mask: u32, value: u32) { - let reg = reg as *mut u32; - - unsafe { reg.write_volatile((reg.read_volatile() & !mask) | value) }; -} - -fn register_modify_bits(reg: u32, bits: u32, set: bool) { - if set { - modify_register(reg, bits, bits); - } else { - modify_register(reg, bits, 0); - } -} - fn rtc_sleep_pu(val: bool) { let rtc_cntl = unsafe { &*esp32s3::RTC_CNTL::ptr() }; let syscon = unsafe { &*esp32s3::APB_CTRL::ptr() }; let bb = unsafe { &*esp32s3::BB::ptr() }; + let nrx = unsafe { &*esp32s3::NRX::ptr() }; + let fe = unsafe { &*esp32s3::FE::ptr() }; + let fe2 = unsafe { &*esp32s3::FE2::ptr() }; rtc_cntl .dig_pwc() @@ -385,15 +359,37 @@ fn rtc_sleep_pu(val: bool) { bb.bbpd_ctrl() .modify(|_r, w| w.fft_force_pu().bit(val).dc_est_force_pu().bit(val)); - register_modify_bits( - NRXPD_CTRL, - NRX_RX_ROT_FORCE_PU | NRX_VIT_FORCE_PU | NRX_DEMAP_FORCE_PU, - val, - ); - - register_modify_bits(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, val); + if val { + nrx.nrxpd_ctrl().modify(|_, w| { + w.rx_rot_force_pu() + .set_bit() + .vit_force_pu() + .set_bit() + .demap_force_pu() + .set_bit() + }); + } else { + nrx.nrxpd_ctrl().modify(|_, w| { + w.rx_rot_force_pu() + .clear_bit() + .vit_force_pu() + .clear_bit() + .demap_force_pu() + .clear_bit() + }); + } + + if val { + fe.gen_ctrl().modify(|_, w| w.iq_est_force_pu().set_bit()); + } else { + fe.gen_ctrl().modify(|_, w| w.iq_est_force_pu().clear_bit()); + } - register_modify_bits(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, val); + if val { + fe2.tx_interp_ctrl().modify(|_, w| w.tx_inf_force_pu().set_bit()); + } else { + fe2.tx_interp_ctrl().modify(|_, w| w.tx_inf_force_pu().clear_bit()); + } syscon.mem_power_up().modify(|_r, w| unsafe { w.sram_power_up() diff --git a/esp-hal/src/soc/esp32c6/radio_clocks.rs b/esp-hal/src/soc/esp32c6/radio_clocks.rs index 2ce532a7842..83075869ea0 100644 --- a/esp-hal/src/soc/esp32c6/radio_clocks.rs +++ b/esp-hal/src/soc/esp32c6/radio_clocks.rs @@ -342,11 +342,9 @@ fn init_clocks() { pmu.hp_active_icg_modem() .modify(|_, w| w.hp_active_dig_icg_modem_code().bits(2)); pmu.imm_modem_icg() - .as_ptr() - .write_volatile(pmu.imm_modem_icg().as_ptr().read_volatile() | 1 << 31); + .modify(|_, w| w.update_dig_icg_modem_en().set_bit()); pmu.imm_sleep_sysclk() - .as_ptr() - .write_volatile(pmu.imm_sleep_sysclk().as_ptr().read_volatile() | 1 << 28); + .modify(|_, w| w.update_dig_icg_switch().set_bit()); let modem_syscon = &*esp32c6::MODEM_SYSCON::PTR; modem_syscon.clk_conf_power_st().modify(|_, w| { diff --git a/esp-hal/src/soc/esp32h2/radio_clocks.rs b/esp-hal/src/soc/esp32h2/radio_clocks.rs index d9067deab70..350d9e8fc93 100644 --- a/esp-hal/src/soc/esp32h2/radio_clocks.rs +++ b/esp-hal/src/soc/esp32h2/radio_clocks.rs @@ -131,11 +131,9 @@ fn init_clocks() { pmu.hp_active_icg_modem() .modify(|_, w| w.hp_active_dig_icg_modem_code().bits(2)); pmu.imm_modem_icg() - .as_ptr() - .write_volatile(pmu.imm_modem_icg().as_ptr().read_volatile() | 1 << 31); + .modify(|_, w| w.update_dig_icg_modem_en().set_bit()); pmu.imm_sleep_sysclk() - .as_ptr() - .write_volatile(pmu.imm_sleep_sysclk().as_ptr().read_volatile() | 1 << 28); + .modify(|_, w| w.update_dig_icg_switch().set_bit()); (*esp32h2::MODEM_LPCON::PTR).clk_conf().modify(|_, w| { w.clk_i2c_mst_en() diff --git a/esp-storage/src/esp32.rs b/esp-storage/src/esp32.rs index 352a983ab6b..3954dace614 100644 --- a/esp-storage/src/esp32.rs +++ b/esp-storage/src/esp32.rs @@ -146,10 +146,12 @@ pub(crate) fn esp_rom_spiflash_erase_sector(sector_number: u32) -> i32 { #[link_section = ".rwtext"] fn spi_write_enable() { spiflash_wait_for_ready(); - - write_register(SPI_RD_STATUS_REG, 0); - write_register(SPI_CMD_REG, SPI_FLASH_WREN); - while read_register(SPI_CMD_REG) != 0 {} + unsafe { + let spi = &*crate::peripherals::SPI1::PTR; + spi.rd_status().modify(|_, w| w.bits(0)); + spi.cmd().modify(|_, w| w.flash_wren().set_bit()); + while spi.cmd().read().bits() != 0 {} + } } #[inline(never)] @@ -167,35 +169,34 @@ pub(crate) fn esp_rom_spiflash_write(dest_addr: u32, data: *const u32, len: u32) } spiflash_wait_for_ready(); - - write_register(SPI_USER_REG, read_register(SPI_USER_REG) & !SPI_USR_DUMMY); - let addrbits = ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN; - let mut regval = read_register(SPI_USER1_REG); - regval &= !SPI_USR_ADDR_BITLEN_M; - regval |= addrbits << SPI_USR_ADDR_BITLEN_S; - write_register(SPI_USER1_REG, regval); - - for block in (0..len).step_by(32) { - spiflash_wait_for_ready(); - spi_write_enable(); - - let block_len = if len - block < 32 { len - block } else { 32 }; - write_register( - SPI_ADDR_REG, - ((dest_addr + block) & 0xffffff) | block_len << 24, - ); - - let data_ptr = unsafe { data.offset((block / 4) as isize) }; - for i in 0..block_len / 4 { - write_register(SPI_W0_REG + (4 * i), unsafe { - data_ptr.offset(i as isize).read_volatile() - }); + unsafe { + let spi = &*crate::peripherals::SPI1::PTR; + + spi.user().modify(|_, w| w.usr_dummy().clear_bit()); + + spi.user1().modify(|_, w| { + w.usr_addr_bitlen() + .bits(ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN) + }); + + for block in (0..len).step_by(32) { + spiflash_wait_for_ready(); + spi_write_enable(); + let block_len = if len - block < 32 { len - block } else { 32 }; + spi.addr() + .modify(|_, w| w.bits(((dest_addr + block) & 0xffffff) | block_len << 24)); + + let data_ptr = data.offset((block / 4) as isize); + for i in 0..block_len / 4 { + spi.w(i) + .modify(|_, w| w.bits(data_ptr.offset(i as isize).read_volatile())); + } + + spi.rd_status().modify(|_, w| w.bits(0)); + spi.cmd().modify(|_, w| w.flash_pp().set_bit()); + while spi.cmd().read().bits() != 0 {} } - write_register(SPI_RD_STATUS_REG, 0); - write_register(SPI_CMD_REG, 1 << 25); // FLASH PP - while read_register(SPI_CMD_REG) != 0 { /* wait */ } - wait_for_ready(); } @@ -213,26 +214,14 @@ pub(crate) fn esp_rom_spiflash_write(dest_addr: u32, data: *const u32, len: u32) #[inline(always)] #[link_section = ".rwtext"] -pub fn read_register(address: u32) -> u32 { - unsafe { (address as *const u32).read_volatile() } -} - -#[inline(always)] -#[link_section = ".rwtext"] -pub fn write_register(address: u32, value: u32) { +fn wait_for_ready() { unsafe { - (address as *mut u32).write_volatile(value); + while (&*crate::peripherals::SPI1::PTR).ext2().read().st().bits() != 0 {} + // ESP32_OR_LATER ... we don't support anything earlier + while (&*crate::peripherals::SPI0::PTR).ext2().read().st().bits() != 0 {} } } -#[inline(always)] -#[link_section = ".rwtext"] -fn wait_for_ready() { - while (read_register(SPI_EXT2_REG) & SPI_ST) != 0 {} - // ESP32_OR_LATER ... we don't support anything earlier - while (read_register(SPI0_EXT2_REG) & SPI_ST) != 0 {} -} - #[inline(always)] #[link_section = ".rwtext"] fn spiflash_wait_for_ready() { @@ -272,8 +261,11 @@ pub(crate) fn esp_rom_spiflash_unlock() -> i32 { // Clear all bits except QE, if it is set status &= STATUS_QIE_BIT; - - write_register(SPI_CTRL_REG, read_register(SPI_CTRL_REG) | SPI_WRSR_2B); + unsafe { + (&*crate::peripherals::SPI1::PTR) + .ctrl() + .modify(|_, w| w.wrsr_2b().set_bit()); + } spiflash_wait_for_ready(); if spi_write_status(flashchip, status) != 0 { diff --git a/esp-wifi/src/wifi/os_adapter_esp32.rs b/esp-wifi/src/wifi/os_adapter_esp32.rs index 6ef40ee33d1..f91e0b515a8 100644 --- a/esp-wifi/src/wifi/os_adapter_esp32.rs +++ b/esp-wifi/src/wifi/os_adapter_esp32.rs @@ -4,12 +4,7 @@ use crate::hal::{interrupt, peripherals}; -const DR_REG_DPORT_BASE: u32 = 0x3ff00000; -const DPORT_WIFI_CLK_EN_REG: u32 = DR_REG_DPORT_BASE + 0x0CC; -const DPORT_WIFI_CLK_WIFI_EN: u32 = 0x00000406; -const DPORT_WIFI_CLK_WIFI_EN_V: u32 = 0x406; -const DPORT_WIFI_CLK_WIFI_EN_S: u32 = 0; -const DPORT_WIFI_CLK_WIFI_EN_M: u32 = (DPORT_WIFI_CLK_WIFI_EN_V) << (DPORT_WIFI_CLK_WIFI_EN_S); +const DPORT_WIFI_CLK_WIFI_EN_M: u32 = 0x406; pub(crate) fn chip_ints_on(mask: u32) { unsafe { crate::hal::xtensa_lx::interrupt::enable_mask(mask) }; @@ -56,15 +51,21 @@ pub(crate) unsafe extern "C" fn set_intr( } pub(crate) unsafe extern "C" fn wifi_clock_enable() { - let ptr = DPORT_WIFI_CLK_EN_REG as *mut u32; - let old = ptr.read_volatile(); - ptr.write_volatile(old | DPORT_WIFI_CLK_WIFI_EN_M); + let dport = &*crate::hal::peripherals::SYSTEM::ptr(); + dport.wifi_clk_en().modify(|r, w| { + let old = r.bits(); + let new_bits = old | DPORT_WIFI_CLK_WIFI_EN_M; + w.bits(new_bits) + }); } pub(crate) unsafe extern "C" fn wifi_clock_disable() { - let ptr = DPORT_WIFI_CLK_EN_REG as *mut u32; - let old = ptr.read_volatile(); - ptr.write_volatile(old & !DPORT_WIFI_CLK_WIFI_EN_M); + let dport = &*crate::hal::peripherals::SYSTEM::ptr(); + dport.wifi_clk_en().modify(|r, w| { + let old = r.bits(); + let new_bits = old & !DPORT_WIFI_CLK_WIFI_EN_M; + w.bits(new_bits) + }); } /// ************************************************************************** diff --git a/examples/src/bin/wifi_dhcp.rs b/examples/src/bin/wifi_dhcp.rs index 72183c5ece8..89f842da27d 100644 --- a/examples/src/bin/wifi_dhcp.rs +++ b/examples/src/bin/wifi_dhcp.rs @@ -41,8 +41,8 @@ use smoltcp::{ wire::{IpAddress, Ipv4Address}, }; -const SSID: &str = env!("SSID"); -const PASSWORD: &str = env!("PASSWORD"); +const SSID: &str = "EspressifSystems"; +const PASSWORD: &str = "Espressif32"; #[entry] fn main() -> ! { From ba62ba0fff5974084ac329b28e29ec51714f0c8a Mon Sep 17 00:00:00 2001 From: Kirill Mikhailov Date: Wed, 31 Jul 2024 16:49:56 +0200 Subject: [PATCH 2/8] More fixes --- esp-hal/src/interrupt/riscv.rs | 90 ++++++++++--------------- esp-hal/src/rtc_cntl/sleep/esp32c3.rs | 13 ++-- esp-hal/src/rtc_cntl/sleep/esp32s3.rs | 8 ++- esp-hal/src/soc/esp32c6/radio_clocks.rs | 4 +- 4 files changed, 51 insertions(+), 64 deletions(-) diff --git a/esp-hal/src/interrupt/riscv.rs b/esp-hal/src/interrupt/riscv.rs index 6b9f8da7722..d9b9213ed53 100644 --- a/esp-hal/src/interrupt/riscv.rs +++ b/esp-hal/src/interrupt/riscv.rs @@ -572,12 +572,7 @@ mod classic { /// priority of interrupts 1 - 15. pub unsafe fn set_priority(_core: Cpu, which: CpuInterrupt, priority: Priority) { let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR; - let cpu_interrupt_number = which as isize; - let intr_prio_base = intr.cpu_int_pri(0).as_ptr(); - - intr_prio_base - .offset(cpu_interrupt_number) - .write_volatile(priority as u32); + intr.cpu_int_pri(which as usize).read().map().bits(priority as u32); } /// Clear a CPU interrupt @@ -601,12 +596,7 @@ mod classic { #[inline] pub(super) unsafe extern "C" fn get_priority(cpu_interrupt: CpuInterrupt) -> Priority { let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR; - let intr_prio_base = intr.cpu_int_pri(0).as_ptr(); - - let prio = intr_prio_base - .offset(cpu_interrupt as isize) - .read_volatile(); - core::mem::transmute::(prio as u8) + core::mem::transmute::(intr.cpu_int_pri(cpu_interrupt as usize).read().map().bits()) } #[no_mangle] #[link_section = ".trap"] @@ -659,22 +649,19 @@ mod plic { 1, 2, 0, 0, 3, 4, 0, 0, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ]; - const DR_REG_PLIC_MX_BASE: u32 = 0x20001000; - const PLIC_MXINT_ENABLE_REG: u32 = DR_REG_PLIC_MX_BASE; - const PLIC_MXINT_TYPE_REG: u32 = DR_REG_PLIC_MX_BASE + 0x4; - const PLIC_MXINT_CLEAR_REG: u32 = DR_REG_PLIC_MX_BASE + 0x8; - const PLIC_MXINT0_PRI_REG: u32 = DR_REG_PLIC_MX_BASE + 0x10; - const PLIC_MXINT_THRESH_REG: u32 = DR_REG_PLIC_MX_BASE + 0x90; /// Enable a CPU interrupt /// /// # Safety /// /// Make sure there is an interrupt handler registered. pub unsafe fn enable_cpu_interrupt(which: CpuInterrupt) { - let cpu_interrupt_number = which as isize; - let mxint_enable = PLIC_MXINT_ENABLE_REG as *mut u32; unsafe { - mxint_enable.write_volatile(mxint_enable.read_volatile() | 1 << cpu_interrupt_number); + let plic = &*crate::peripherals::PLIC_MX::PTR; + plic.mxint_enable().modify(|r, w| { + let old = r.cpu_mxint_enable().bits(); + let new = old | 1 << (which as isize); + w.cpu_mxint_enable().bits(new) + }); } } @@ -684,17 +671,17 @@ mod plic { /// bits. pub fn set_kind(_core: Cpu, which: CpuInterrupt, kind: InterruptKind) { unsafe { - let intr = PLIC_MXINT_TYPE_REG as *mut u32; - let cpu_interrupt_number = which as isize; - + let plic = &*crate::peripherals::PLIC_MX::PTR; let interrupt_type = match kind { InterruptKind::Level => 0, InterruptKind::Edge => 1, }; - intr.write_volatile( - intr.read_volatile() & !(1 << cpu_interrupt_number) - | (interrupt_type << cpu_interrupt_number), - ); + + plic.mxint_type().modify(|r, w| { + let old = r.cpu_mxint_type().bits(); + let new = old & !(1 << (which as isize)) | (interrupt_type << (which as isize)); + w.cpu_mxint_type().bits(new) + }); } } @@ -705,21 +692,23 @@ mod plic { /// Great care must be taken when using this function; avoid changing the /// priority of interrupts 1 - 15. pub unsafe fn set_priority(_core: Cpu, which: CpuInterrupt, priority: Priority) { - let plic_mxint_pri_ptr = PLIC_MXINT0_PRI_REG as *mut u32; - - let cpu_interrupt_number = which as isize; - plic_mxint_pri_ptr - .offset(cpu_interrupt_number) - .write_volatile(priority as u32); + unsafe { + let plic = &*crate::peripherals::PLIC_MX::PTR; + plic.mxint_pri(which as usize) + .modify(|_, w| w.cpu_mxint_pri().bits(priority as u8)); + } } /// Clear a CPU interrupt #[inline] pub fn clear(_core: Cpu, which: CpuInterrupt) { unsafe { - let cpu_interrupt_number = which as isize; - let intr = PLIC_MXINT_CLEAR_REG as *mut u32; - intr.write_volatile(1 << cpu_interrupt_number); + let plic = &*crate::peripherals::PLIC_MX::PTR; + plic.mxint_clear().modify(|r, w| { + let old = r.cpu_mxint_clear().bits(); + let new = old | (1 << (which as isize)); + w.cpu_mxint_clear().bits(new) + }); } } @@ -735,40 +724,35 @@ mod plic { /// Get interrupt priority - called by assembly code #[inline] pub(super) unsafe extern "C" fn get_priority(cpu_interrupt: CpuInterrupt) -> Priority { - let plic_mxint_pri_ptr = PLIC_MXINT0_PRI_REG as *mut u32; - - let cpu_interrupt_number = cpu_interrupt as isize; - let prio = plic_mxint_pri_ptr - .offset(cpu_interrupt_number) - .read_volatile(); + let plic = &*crate::peripherals::PLIC_MX::PTR; + let prio = plic.mxint_pri(cpu_interrupt as usize).read().cpu_mxint_pri().bits(); core::mem::transmute::(prio as u8) } #[no_mangle] #[link_section = ".trap"] pub(super) unsafe extern "C" fn _handle_priority() -> u32 { use super::mcause; - let plic_mxint_pri_ptr = PLIC_MXINT0_PRI_REG as *mut u32; - let interrupt_id: isize = unwrap!(mcause::read().code().try_into()); // MSB is whether its exception or interrupt. - let interrupt_priority = plic_mxint_pri_ptr.offset(interrupt_id).read_volatile(); + let plic = &*crate::peripherals::PLIC_MX::PTR; - let thresh_reg = PLIC_MXINT_THRESH_REG as *mut u32; - let prev_interrupt_priority = thresh_reg.read_volatile() & 0x000000FF; - // this is a u8 according to esp-idf, so mask everything else. + let interrupt_id: usize = unwrap!(mcause::read().code().try_into()); // MSB is whether its exception or interrupt. + let interrupt_priority = plic.mxint_pri(interrupt_id).read().cpu_mxint_pri().bits(); + + let prev_interrupt_priority = plic.mxint_thresh().read().cpu_mxint_thresh().bits(); if interrupt_priority < 15 { // leave interrupts disabled if interrupt is of max priority. - thresh_reg.write_volatile(interrupt_priority + 1); + plic.mxint_thresh().write(|w| w.cpu_mxint_thresh().bits(interrupt_priority + 1)); unsafe { riscv::interrupt::enable(); } } - prev_interrupt_priority + prev_interrupt_priority as u32 } #[no_mangle] #[link_section = ".trap"] pub(super) unsafe extern "C" fn _restore_priority(stored_prio: u32) { riscv::interrupt::disable(); - let thresh_reg = PLIC_MXINT_THRESH_REG as *mut u32; - thresh_reg.write_volatile(stored_prio); + let plic = &*crate::peripherals::PLIC_MX::PTR; + plic.mxint_thresh().write(|w| w.cpu_mxint_thresh().bits(stored_prio as u8)); } } diff --git a/esp-hal/src/rtc_cntl/sleep/esp32c3.rs b/esp-hal/src/rtc_cntl/sleep/esp32c3.rs index 783dd8ffe72..632296185e9 100644 --- a/esp-hal/src/rtc_cntl/sleep/esp32c3.rs +++ b/esp-hal/src/rtc_cntl/sleep/esp32c3.rs @@ -394,9 +394,9 @@ fn rtc_sleep_pu(val: bool) { let rtc_cntl = unsafe { &*esp32c3::RTC_CNTL::ptr() }; let syscon = unsafe { &*esp32c3::APB_CTRL::ptr() }; let bb = unsafe { &*esp32c3::BB::ptr() }; - let nrx = unsafe { &*esp32s3::NRX::ptr() }; - let fe = unsafe { &*esp32s3::FE::ptr() }; - let fe2 = unsafe { &*esp32s3::FE2::ptr() }; + let nrx = unsafe { &*esp32c3::NRX::ptr() }; + let fe = unsafe { &*esp32c3::FE::ptr() }; + let fe2 = unsafe { &*esp32c3::FE2::ptr() }; rtc_cntl .dig_pwc() @@ -414,7 +414,6 @@ fn rtc_sleep_pu(val: bool) { bb.bbpd_ctrl() .modify(|_r, w| w.fft_force_pu().bit(val).dc_est_force_pu().bit(val)); - if val { nrx.nrxpd_ctrl().modify(|_, w| { w.rx_rot_force_pu() @@ -442,9 +441,11 @@ fn rtc_sleep_pu(val: bool) { } if val { - fe2.tx_interp_ctrl().modify(|_, w| w.tx_inf_force_pu().set_bit()); + fe2.tx_interp_ctrl() + .modify(|_, w| w.tx_inf_force_pu().set_bit()); } else { - fe2.tx_interp_ctrl().modify(|_, w| w.tx_inf_force_pu().clear_bit()); + fe2.tx_interp_ctrl() + .modify(|_, w| w.tx_inf_force_pu().clear_bit()); } syscon.mem_power_up().modify(|_r, w| unsafe { diff --git a/esp-hal/src/rtc_cntl/sleep/esp32s3.rs b/esp-hal/src/rtc_cntl/sleep/esp32s3.rs index 89737903fdf..3dddc059dba 100644 --- a/esp-hal/src/rtc_cntl/sleep/esp32s3.rs +++ b/esp-hal/src/rtc_cntl/sleep/esp32s3.rs @@ -378,7 +378,7 @@ fn rtc_sleep_pu(val: bool) { .clear_bit() }); } - + if val { fe.gen_ctrl().modify(|_, w| w.iq_est_force_pu().set_bit()); } else { @@ -386,9 +386,11 @@ fn rtc_sleep_pu(val: bool) { } if val { - fe2.tx_interp_ctrl().modify(|_, w| w.tx_inf_force_pu().set_bit()); + fe2.tx_interp_ctrl() + .modify(|_, w| w.tx_inf_force_pu().set_bit()); } else { - fe2.tx_interp_ctrl().modify(|_, w| w.tx_inf_force_pu().clear_bit()); + fe2.tx_interp_ctrl() + .modify(|_, w| w.tx_inf_force_pu().clear_bit()); } syscon.mem_power_up().modify(|_r, w| unsafe { diff --git a/esp-hal/src/soc/esp32c6/radio_clocks.rs b/esp-hal/src/soc/esp32c6/radio_clocks.rs index 83075869ea0..f9319969bcc 100644 --- a/esp-hal/src/soc/esp32c6/radio_clocks.rs +++ b/esp-hal/src/soc/esp32c6/radio_clocks.rs @@ -342,9 +342,9 @@ fn init_clocks() { pmu.hp_active_icg_modem() .modify(|_, w| w.hp_active_dig_icg_modem_code().bits(2)); pmu.imm_modem_icg() - .modify(|_, w| w.update_dig_icg_modem_en().set_bit()); + .write(|w| w.update_dig_icg_modem_en().set_bit()); pmu.imm_sleep_sysclk() - .modify(|_, w| w.update_dig_icg_switch().set_bit()); + .write(|w| w.update_dig_icg_switch().set_bit()); let modem_syscon = &*esp32c6::MODEM_SYSCON::PTR; modem_syscon.clk_conf_power_st().modify(|_, w| { From 576227bd33af1b2a8f0814c40bae41822b762243 Mon Sep 17 00:00:00 2001 From: Kirill Mikhailov Date: Thu, 1 Aug 2024 14:00:01 +0200 Subject: [PATCH 3/8] Roll back `esp-storage` changes --- esp-hal/src/interrupt/riscv.rs | 19 +++++-- esp-storage/src/esp32.rs | 90 ++++++++++++++++++---------------- 2 files changed, 63 insertions(+), 46 deletions(-) diff --git a/esp-hal/src/interrupt/riscv.rs b/esp-hal/src/interrupt/riscv.rs index d9b9213ed53..49232867f1b 100644 --- a/esp-hal/src/interrupt/riscv.rs +++ b/esp-hal/src/interrupt/riscv.rs @@ -572,7 +572,8 @@ mod classic { /// priority of interrupts 1 - 15. pub unsafe fn set_priority(_core: Cpu, which: CpuInterrupt, priority: Priority) { let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR; - intr.cpu_int_pri(which as usize).read().map().bits(priority as u32); + intr.cpu_int_pri(which as usize) + .write(|w| w.map().bits(priority as u8)); } /// Clear a CPU interrupt @@ -596,7 +597,9 @@ mod classic { #[inline] pub(super) unsafe extern "C" fn get_priority(cpu_interrupt: CpuInterrupt) -> Priority { let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR; - core::mem::transmute::(intr.cpu_int_pri(cpu_interrupt as usize).read().map().bits()) + core::mem::transmute::( + intr.cpu_int_pri(cpu_interrupt as usize).read().map().bits(), + ) } #[no_mangle] #[link_section = ".trap"] @@ -725,7 +728,11 @@ mod plic { #[inline] pub(super) unsafe extern "C" fn get_priority(cpu_interrupt: CpuInterrupt) -> Priority { let plic = &*crate::peripherals::PLIC_MX::PTR; - let prio = plic.mxint_pri(cpu_interrupt as usize).read().cpu_mxint_pri().bits(); + let prio = plic + .mxint_pri(cpu_interrupt as usize) + .read() + .cpu_mxint_pri() + .bits(); core::mem::transmute::(prio as u8) } #[no_mangle] @@ -740,7 +747,8 @@ mod plic { let prev_interrupt_priority = plic.mxint_thresh().read().cpu_mxint_thresh().bits(); if interrupt_priority < 15 { // leave interrupts disabled if interrupt is of max priority. - plic.mxint_thresh().write(|w| w.cpu_mxint_thresh().bits(interrupt_priority + 1)); + plic.mxint_thresh() + .write(|w| w.cpu_mxint_thresh().bits(interrupt_priority + 1)); unsafe { riscv::interrupt::enable(); } @@ -752,7 +760,8 @@ mod plic { pub(super) unsafe extern "C" fn _restore_priority(stored_prio: u32) { riscv::interrupt::disable(); let plic = &*crate::peripherals::PLIC_MX::PTR; - plic.mxint_thresh().write(|w| w.cpu_mxint_thresh().bits(stored_prio as u8)); + plic.mxint_thresh() + .write(|w| w.cpu_mxint_thresh().bits(stored_prio as u8)); } } diff --git a/esp-storage/src/esp32.rs b/esp-storage/src/esp32.rs index 3954dace614..352a983ab6b 100644 --- a/esp-storage/src/esp32.rs +++ b/esp-storage/src/esp32.rs @@ -146,12 +146,10 @@ pub(crate) fn esp_rom_spiflash_erase_sector(sector_number: u32) -> i32 { #[link_section = ".rwtext"] fn spi_write_enable() { spiflash_wait_for_ready(); - unsafe { - let spi = &*crate::peripherals::SPI1::PTR; - spi.rd_status().modify(|_, w| w.bits(0)); - spi.cmd().modify(|_, w| w.flash_wren().set_bit()); - while spi.cmd().read().bits() != 0 {} - } + + write_register(SPI_RD_STATUS_REG, 0); + write_register(SPI_CMD_REG, SPI_FLASH_WREN); + while read_register(SPI_CMD_REG) != 0 {} } #[inline(never)] @@ -169,34 +167,35 @@ pub(crate) fn esp_rom_spiflash_write(dest_addr: u32, data: *const u32, len: u32) } spiflash_wait_for_ready(); - unsafe { - let spi = &*crate::peripherals::SPI1::PTR; - - spi.user().modify(|_, w| w.usr_dummy().clear_bit()); - - spi.user1().modify(|_, w| { - w.usr_addr_bitlen() - .bits(ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN) - }); - - for block in (0..len).step_by(32) { - spiflash_wait_for_ready(); - spi_write_enable(); - let block_len = if len - block < 32 { len - block } else { 32 }; - spi.addr() - .modify(|_, w| w.bits(((dest_addr + block) & 0xffffff) | block_len << 24)); - - let data_ptr = data.offset((block / 4) as isize); - for i in 0..block_len / 4 { - spi.w(i) - .modify(|_, w| w.bits(data_ptr.offset(i as isize).read_volatile())); - } - - spi.rd_status().modify(|_, w| w.bits(0)); - spi.cmd().modify(|_, w| w.flash_pp().set_bit()); - while spi.cmd().read().bits() != 0 {} + + write_register(SPI_USER_REG, read_register(SPI_USER_REG) & !SPI_USR_DUMMY); + let addrbits = ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN; + let mut regval = read_register(SPI_USER1_REG); + regval &= !SPI_USR_ADDR_BITLEN_M; + regval |= addrbits << SPI_USR_ADDR_BITLEN_S; + write_register(SPI_USER1_REG, regval); + + for block in (0..len).step_by(32) { + spiflash_wait_for_ready(); + spi_write_enable(); + + let block_len = if len - block < 32 { len - block } else { 32 }; + write_register( + SPI_ADDR_REG, + ((dest_addr + block) & 0xffffff) | block_len << 24, + ); + + let data_ptr = unsafe { data.offset((block / 4) as isize) }; + for i in 0..block_len / 4 { + write_register(SPI_W0_REG + (4 * i), unsafe { + data_ptr.offset(i as isize).read_volatile() + }); } + write_register(SPI_RD_STATUS_REG, 0); + write_register(SPI_CMD_REG, 1 << 25); // FLASH PP + while read_register(SPI_CMD_REG) != 0 { /* wait */ } + wait_for_ready(); } @@ -214,14 +213,26 @@ pub(crate) fn esp_rom_spiflash_write(dest_addr: u32, data: *const u32, len: u32) #[inline(always)] #[link_section = ".rwtext"] -fn wait_for_ready() { +pub fn read_register(address: u32) -> u32 { + unsafe { (address as *const u32).read_volatile() } +} + +#[inline(always)] +#[link_section = ".rwtext"] +pub fn write_register(address: u32, value: u32) { unsafe { - while (&*crate::peripherals::SPI1::PTR).ext2().read().st().bits() != 0 {} - // ESP32_OR_LATER ... we don't support anything earlier - while (&*crate::peripherals::SPI0::PTR).ext2().read().st().bits() != 0 {} + (address as *mut u32).write_volatile(value); } } +#[inline(always)] +#[link_section = ".rwtext"] +fn wait_for_ready() { + while (read_register(SPI_EXT2_REG) & SPI_ST) != 0 {} + // ESP32_OR_LATER ... we don't support anything earlier + while (read_register(SPI0_EXT2_REG) & SPI_ST) != 0 {} +} + #[inline(always)] #[link_section = ".rwtext"] fn spiflash_wait_for_ready() { @@ -261,11 +272,8 @@ pub(crate) fn esp_rom_spiflash_unlock() -> i32 { // Clear all bits except QE, if it is set status &= STATUS_QIE_BIT; - unsafe { - (&*crate::peripherals::SPI1::PTR) - .ctrl() - .modify(|_, w| w.wrsr_2b().set_bit()); - } + + write_register(SPI_CTRL_REG, read_register(SPI_CTRL_REG) | SPI_WRSR_2B); spiflash_wait_for_ready(); if spi_write_status(flashchip, status) != 0 { From f1f4ca265fab9c0f654be4a5a49074ccfe0cc61f Mon Sep 17 00:00:00 2001 From: Kirill Mikhailov Date: Fri, 9 Aug 2024 14:52:43 +0200 Subject: [PATCH 4/8] Small fixes Will not work, needs another patch for PACs --- esp-hal/src/interrupt/riscv.rs | 2 +- esp-hal/src/soc/esp32h2/radio_clocks.rs | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/esp-hal/src/interrupt/riscv.rs b/esp-hal/src/interrupt/riscv.rs index 49232867f1b..fcb8e1d46f1 100644 --- a/esp-hal/src/interrupt/riscv.rs +++ b/esp-hal/src/interrupt/riscv.rs @@ -733,7 +733,7 @@ mod plic { .read() .cpu_mxint_pri() .bits(); - core::mem::transmute::(prio as u8) + core::mem::transmute::(prio) } #[no_mangle] #[link_section = ".trap"] diff --git a/esp-hal/src/soc/esp32h2/radio_clocks.rs b/esp-hal/src/soc/esp32h2/radio_clocks.rs index 350d9e8fc93..101e7ee20ad 100644 --- a/esp-hal/src/soc/esp32h2/radio_clocks.rs +++ b/esp-hal/src/soc/esp32h2/radio_clocks.rs @@ -131,9 +131,9 @@ fn init_clocks() { pmu.hp_active_icg_modem() .modify(|_, w| w.hp_active_dig_icg_modem_code().bits(2)); pmu.imm_modem_icg() - .modify(|_, w| w.update_dig_icg_modem_en().set_bit()); + .write(|w| w.update_dig_icg_modem_en().set_bit()); pmu.imm_sleep_sysclk() - .modify(|_, w| w.update_dig_icg_switch().set_bit()); + .write(|w| w.update_dig_icg_switch().set_bit()); (*esp32h2::MODEM_LPCON::PTR).clk_conf().modify(|_, w| { w.clk_i2c_mst_en() From eeb4161f4d4337455fb195c8a06a396bcc41a57d Mon Sep 17 00:00:00 2001 From: Kirill Mikhailov Date: Fri, 9 Aug 2024 15:30:45 +0200 Subject: [PATCH 5/8] update pacs dep --- esp-hal/Cargo.toml | 1 + 1 file changed, 1 insertion(+) diff --git a/esp-hal/Cargo.toml b/esp-hal/Cargo.toml index 525f41cbae0..aaa9eb32bcb 100644 --- a/esp-hal/Cargo.toml +++ b/esp-hal/Cargo.toml @@ -53,6 +53,7 @@ xtensa-lx = { version = "0.9.0", optional = true } # IMPORTANT: # Each supported device MUST have its PAC included below along with a # corresponding feature. +esp32 = { git = "https://github.com/esp-rs/esp-pacs", rev = "db62264", features = ["critical-section", "rt"], optional = true } esp32 = { git = "https://github.com/esp-rs/esp-pacs", rev = "5270c86", features = ["critical-section", "rt"], optional = true } esp32c2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "5270c86", features = ["critical-section", "rt"], optional = true } esp32c3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "5270c86", features = ["critical-section", "rt"], optional = true } From cc5019a1cb1fb8753c409c67fe15e85d4b196c83 Mon Sep 17 00:00:00 2001 From: Kirill Mikhailov Date: Fri, 9 Aug 2024 16:21:17 +0200 Subject: [PATCH 6/8] Lint --- esp-hal/src/interrupt/riscv.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/esp-hal/src/interrupt/riscv.rs b/esp-hal/src/interrupt/riscv.rs index fcb8e1d46f1..19e062ef5f8 100644 --- a/esp-hal/src/interrupt/riscv.rs +++ b/esp-hal/src/interrupt/riscv.rs @@ -741,7 +741,7 @@ mod plic { use super::mcause; let plic = &*crate::peripherals::PLIC_MX::PTR; - let interrupt_id: usize = unwrap!(mcause::read().code().try_into()); // MSB is whether its exception or interrupt. + let interrupt_id: usize = mcause::read().code(); // MSB is whether its exception or interrupt. let interrupt_priority = plic.mxint_pri(interrupt_id).read().cpu_mxint_pri().bits(); let prev_interrupt_priority = plic.mxint_thresh().read().cpu_mxint_thresh().bits(); From a2504dd26f9d4d45a458bdd2f7cd9f45b14d2681 Mon Sep 17 00:00:00 2001 From: Kirill Mikhailov Date: Mon, 12 Aug 2024 17:32:52 +0200 Subject: [PATCH 7/8] Get rid of unnecessary if-else fix --- esp-hal/src/rtc_cntl/sleep/esp32c3.rs | 42 +++++++-------------------- esp-hal/src/rtc_cntl/sleep/esp32s3.rs | 42 +++++++-------------------- examples/src/bin/wifi_dhcp.rs | 4 +-- 3 files changed, 24 insertions(+), 64 deletions(-) diff --git a/esp-hal/src/rtc_cntl/sleep/esp32c3.rs b/esp-hal/src/rtc_cntl/sleep/esp32c3.rs index 632296185e9..e5a0c89eff6 100644 --- a/esp-hal/src/rtc_cntl/sleep/esp32c3.rs +++ b/esp-hal/src/rtc_cntl/sleep/esp32c3.rs @@ -414,39 +414,19 @@ fn rtc_sleep_pu(val: bool) { bb.bbpd_ctrl() .modify(|_r, w| w.fft_force_pu().bit(val).dc_est_force_pu().bit(val)); - if val { - nrx.nrxpd_ctrl().modify(|_, w| { - w.rx_rot_force_pu() - .set_bit() - .vit_force_pu() - .set_bit() - .demap_force_pu() - .set_bit() - }); - } else { - nrx.nrxpd_ctrl().modify(|_, w| { - w.rx_rot_force_pu() - .clear_bit() - .vit_force_pu() - .clear_bit() - .demap_force_pu() - .clear_bit() - }); - } + nrx.nrxpd_ctrl().modify(|_, w| { + w.rx_rot_force_pu() + .bit(val) + .vit_force_pu() + .bit(val) + .demap_force_pu() + .bit(val) + }); - if val { - fe.gen_ctrl().modify(|_, w| w.iq_est_force_pu().set_bit()); - } else { - fe.gen_ctrl().modify(|_, w| w.iq_est_force_pu().clear_bit()); - } + fe.gen_ctrl().modify(|_, w| w.iq_est_force_pu().bit(val)); - if val { - fe2.tx_interp_ctrl() - .modify(|_, w| w.tx_inf_force_pu().set_bit()); - } else { - fe2.tx_interp_ctrl() - .modify(|_, w| w.tx_inf_force_pu().clear_bit()); - } + fe2.tx_interp_ctrl() + .modify(|_, w| w.tx_inf_force_pu().bit(val)); syscon.mem_power_up().modify(|_r, w| unsafe { w.sram_power_up() diff --git a/esp-hal/src/rtc_cntl/sleep/esp32s3.rs b/esp-hal/src/rtc_cntl/sleep/esp32s3.rs index 3dddc059dba..23a9585825e 100644 --- a/esp-hal/src/rtc_cntl/sleep/esp32s3.rs +++ b/esp-hal/src/rtc_cntl/sleep/esp32s3.rs @@ -359,39 +359,19 @@ fn rtc_sleep_pu(val: bool) { bb.bbpd_ctrl() .modify(|_r, w| w.fft_force_pu().bit(val).dc_est_force_pu().bit(val)); - if val { - nrx.nrxpd_ctrl().modify(|_, w| { - w.rx_rot_force_pu() - .set_bit() - .vit_force_pu() - .set_bit() - .demap_force_pu() - .set_bit() - }); - } else { - nrx.nrxpd_ctrl().modify(|_, w| { - w.rx_rot_force_pu() - .clear_bit() - .vit_force_pu() - .clear_bit() - .demap_force_pu() - .clear_bit() - }); - } + nrx.nrxpd_ctrl().modify(|_, w| { + w.rx_rot_force_pu() + .bit(val) + .vit_force_pu() + .bit(val) + .demap_force_pu() + .bit(val) + }); - if val { - fe.gen_ctrl().modify(|_, w| w.iq_est_force_pu().set_bit()); - } else { - fe.gen_ctrl().modify(|_, w| w.iq_est_force_pu().clear_bit()); - } + fe.gen_ctrl().modify(|_, w| w.iq_est_force_pu().bit(val)); - if val { - fe2.tx_interp_ctrl() - .modify(|_, w| w.tx_inf_force_pu().set_bit()); - } else { - fe2.tx_interp_ctrl() - .modify(|_, w| w.tx_inf_force_pu().clear_bit()); - } + fe2.tx_interp_ctrl() + .modify(|_, w| w.tx_inf_force_pu().bit(val)); syscon.mem_power_up().modify(|_r, w| unsafe { w.sram_power_up() diff --git a/examples/src/bin/wifi_dhcp.rs b/examples/src/bin/wifi_dhcp.rs index 89f842da27d..72183c5ece8 100644 --- a/examples/src/bin/wifi_dhcp.rs +++ b/examples/src/bin/wifi_dhcp.rs @@ -41,8 +41,8 @@ use smoltcp::{ wire::{IpAddress, Ipv4Address}, }; -const SSID: &str = "EspressifSystems"; -const PASSWORD: &str = "Espressif32"; +const SSID: &str = env!("SSID"); +const PASSWORD: &str = env!("PASSWORD"); #[entry] fn main() -> ! { From 592dfa22deb90b68b97a48f086c96c28b49bf6f5 Mon Sep 17 00:00:00 2001 From: Kirill Mikhailov Date: Wed, 14 Aug 2024 18:14:29 +0200 Subject: [PATCH 8/8] New pacs version --- esp-hal/Cargo.toml | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/esp-hal/Cargo.toml b/esp-hal/Cargo.toml index aaa9eb32bcb..11a516cfa89 100644 --- a/esp-hal/Cargo.toml +++ b/esp-hal/Cargo.toml @@ -53,14 +53,13 @@ xtensa-lx = { version = "0.9.0", optional = true } # IMPORTANT: # Each supported device MUST have its PAC included below along with a # corresponding feature. -esp32 = { git = "https://github.com/esp-rs/esp-pacs", rev = "db62264", features = ["critical-section", "rt"], optional = true } -esp32 = { git = "https://github.com/esp-rs/esp-pacs", rev = "5270c86", features = ["critical-section", "rt"], optional = true } -esp32c2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "5270c86", features = ["critical-section", "rt"], optional = true } -esp32c3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "5270c86", features = ["critical-section", "rt"], optional = true } -esp32c6 = { git = "https://github.com/esp-rs/esp-pacs", rev = "5270c86", features = ["critical-section", "rt"], optional = true } -esp32h2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "5270c86", features = ["critical-section", "rt"], optional = true } -esp32s2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "5270c86", features = ["critical-section", "rt"], optional = true } -esp32s3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "5270c86", features = ["critical-section", "rt"], optional = true } +esp32 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true } +esp32c2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true } +esp32c3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true } +esp32c6 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true } +esp32h2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true } +esp32s2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true } +esp32s3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true } [target.'cfg(target_arch = "riscv32")'.dependencies] esp-riscv-rt = { version = "0.9.0", path = "../esp-riscv-rt" }