diff --git a/CHANGELOG.md b/CHANGELOG.md
index d50f4710d06..3aebe06eca9 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -16,6 +16,10 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Add bare-bones PSRAM support for ESP32-S3 (#517)
 - Add async support to the I2C driver (#519)
 
+### Changed
+
+- Move core interrupt handling from Flash to RAM for RISC-V chips (ESP32-H2, ESP32-C2, ESP32-C3, ESP32-C6) (#541)
+
 ### Fixed
 
 - DMA is supported for SPI3 on ESP32-S3 (#507)
diff --git a/esp32c2-hal/ld/bl-riscv-link.x b/esp32c2-hal/ld/bl-riscv-link.x
index 08d16643647..86b77a7d3ea 100644
--- a/esp32c2-hal/ld/bl-riscv-link.x
+++ b/esp32c2-hal/ld/bl-riscv-link.x
@@ -56,12 +56,19 @@ SECTIONS {
     KEEP(*(.init));
     KEEP(*(.init.rust));
     KEEP(*(.text.abort));
-    KEEP(*(.trap));
-    KEEP(*(.trap.rust));
   } > ROTEXT
 }
 INSERT BEFORE .text;
 
+SECTIONS {
+  .trap : ALIGN(4)
+  {
+    KEEP(*(.trap));
+    *(.trap.*);
+  } > RWTEXT
+}
+INSERT AFTER .rwtext;
+
 SECTIONS {
   /**
    * This dummy section represents the .text section but in rodata.
@@ -86,6 +93,7 @@ SECTIONS {
     . = ALIGN(ALIGNOF(.rwtext));
     . = . + SIZEOF(.rwtext);
     . = . + SIZEOF(.rwtext.wifi);
+    . = . + SIZEOF(.trap);
   } > RWDATA
 }
 INSERT BEFORE .data;
diff --git a/esp32c2-hal/ld/db-riscv-link.x b/esp32c2-hal/ld/db-riscv-link.x
index c3e9625f8ad..091e34096a5 100644
--- a/esp32c2-hal/ld/db-riscv-link.x
+++ b/esp32c2-hal/ld/db-riscv-link.x
@@ -55,8 +55,6 @@ SECTIONS
     KEEP(*(.init.rust));
     KEEP(*(.text.abort));
     . = ALIGN(4);
-    KEEP(*(.trap));
-    KEEP(*(.trap.rust));
 
     *(.text .text.*);
     _etext = .;
@@ -93,6 +91,8 @@ SECTIONS
     _srwtext = .;
     *(.rwtext);
     . = ALIGN(4);
+    KEEP(*(.trap));
+    *(.trap.*);
     _erwtext = .;
   } > REGION_RWTEXT
   _rwtext_size = _erwtext - _srwtext + 8;
diff --git a/esp32c3-hal/ld/bl-riscv-link.x b/esp32c3-hal/ld/bl-riscv-link.x
index 432bea95096..2603d6f2ee6 100644
--- a/esp32c3-hal/ld/bl-riscv-link.x
+++ b/esp32c3-hal/ld/bl-riscv-link.x
@@ -56,12 +56,19 @@ SECTIONS {
     KEEP(*(.init));
     KEEP(*(.init.rust));
     KEEP(*(.text.abort));
-    KEEP(*(.trap));
-    KEEP(*(.trap.rust));
   } > ROTEXT
 }
 INSERT BEFORE .text;
 
+SECTIONS {
+  .trap : ALIGN(4)
+  {
+    KEEP(*(.trap));
+    *(.trap.*);
+  } > RWTEXT
+}
+INSERT AFTER .rwtext;
+
 SECTIONS {
   /**
    * This dummy section represents the .text section but in rodata.
@@ -86,6 +93,7 @@ SECTIONS {
     . = ALIGN(ALIGNOF(.rwtext));
     . = . + SIZEOF(.rwtext);
     . = . + SIZEOF(.rwtext.wifi);
+    . = . + SIZEOF(.trap);
   } > RWDATA
 }
 INSERT BEFORE .data;
diff --git a/esp32c3-hal/ld/db-riscv-link.x b/esp32c3-hal/ld/db-riscv-link.x
index 9a8370dd511..316ab1eae8d 100644
--- a/esp32c3-hal/ld/db-riscv-link.x
+++ b/esp32c3-hal/ld/db-riscv-link.x
@@ -55,8 +55,6 @@ SECTIONS
     KEEP(*(.init.rust));
     KEEP(*(.text.abort));
     . = ALIGN(4);
-    KEEP(*(.trap));
-    KEEP(*(.trap.rust));
 
     *(.text .text.*);
     _etext = .;
@@ -93,6 +91,8 @@ SECTIONS
     _srwtext = .;
     *(.rwtext);
     . = ALIGN(4);
+    KEEP(*(.trap));
+    *(.trap.*);
     _erwtext = .;
   } > REGION_RWTEXT
   _rwtext_size = _erwtext - _srwtext + 8;
diff --git a/esp32c3-hal/ld/mb-riscv-link.x b/esp32c3-hal/ld/mb-riscv-link.x
index 2904d51cb59..edfe427c36c 100644
--- a/esp32c3-hal/ld/mb-riscv-link.x
+++ b/esp32c3-hal/ld/mb-riscv-link.x
@@ -66,7 +66,7 @@ SECTIONS
     KEEP(*(.text.abort));
     . = ALIGN(4);
     KEEP(*(.trap));
-    KEEP(*(.trap.rust));
+    *(.trap.*);
 
     *libriscv-*.rlib:riscv.*(.literal .text .literal.* .text.*);
     *libesp_riscv_rt-*.rlib:esp-riscv-rt.*(.literal .text .literal.* .text.*);
diff --git a/esp32c6-hal/ld/bl-riscv-link.x b/esp32c6-hal/ld/bl-riscv-link.x
index f512284a757..4719a464d99 100644
--- a/esp32c6-hal/ld/bl-riscv-link.x
+++ b/esp32c6-hal/ld/bl-riscv-link.x
@@ -60,12 +60,19 @@ SECTIONS {
     KEEP(*(.init));
     KEEP(*(.init.rust));
     KEEP(*(.text.abort));
-    KEEP(*(.trap));
-    KEEP(*(.trap.rust));
   } > ROTEXT
 }
 INSERT BEFORE .text;
 
+SECTIONS {
+  .trap : ALIGN(4)
+  {
+    KEEP(*(.trap));
+    *(.trap.*);
+  } > RWTEXT
+}
+INSERT AFTER .rwtext;
+
 SECTIONS {
   /**
    * Bootloader really wants to have separate segments for ROTEXT and RODATA
diff --git a/esp32c6-hal/ld/db-riscv-link.x b/esp32c6-hal/ld/db-riscv-link.x
index a06c44e52b2..3b1a667e000 100644
--- a/esp32c6-hal/ld/db-riscv-link.x
+++ b/esp32c6-hal/ld/db-riscv-link.x
@@ -60,8 +60,6 @@ SECTIONS
     KEEP(*(.init.rust));
     KEEP(*(.text.abort));
     . = ALIGN(4);
-    KEEP(*(.trap));
-    KEEP(*(.trap.rust));
 
     *(.text .text.*);
     _etext = .;
@@ -98,6 +96,8 @@ SECTIONS
     _srwtext = .;
     *(.rwtext);
     . = ALIGN(4);
+    KEEP(*(.trap));
+    *(.trap.*);
     _erwtext = .;
   } > REGION_RWTEXT
   _rwtext_size = _erwtext - _srwtext + 8;
diff --git a/esp32h2-hal/ld/bl-riscv-link.x b/esp32h2-hal/ld/bl-riscv-link.x
index 701a1684e32..dadd7e7a579 100644
--- a/esp32h2-hal/ld/bl-riscv-link.x
+++ b/esp32h2-hal/ld/bl-riscv-link.x
@@ -54,12 +54,19 @@ SECTIONS {
     KEEP(*(.init));
     KEEP(*(.init.rust));
     KEEP(*(.text.abort));
-    KEEP(*(.trap));
-    KEEP(*(.trap.rust));
   } > ROTEXT
 }
 INSERT BEFORE .text;
 
+SECTIONS {
+  .trap : ALIGN(4)
+  {
+    KEEP(*(.trap));
+    *(.trap.*);
+  } > RWTEXT
+}
+INSERT AFTER .rwtext;
+
 SECTIONS {
   /**
    * Bootloader really wants to have separate segments for ROTEXT and RODATA
diff --git a/esp32h2-hal/ld/db-riscv-link.x b/esp32h2-hal/ld/db-riscv-link.x
index a06c44e52b2..3b1a667e000 100644
--- a/esp32h2-hal/ld/db-riscv-link.x
+++ b/esp32h2-hal/ld/db-riscv-link.x
@@ -60,8 +60,6 @@ SECTIONS
     KEEP(*(.init.rust));
     KEEP(*(.text.abort));
     . = ALIGN(4);
-    KEEP(*(.trap));
-    KEEP(*(.trap.rust));
 
     *(.text .text.*);
     _etext = .;
@@ -98,6 +96,8 @@ SECTIONS
     _srwtext = .;
     *(.rwtext);
     . = ALIGN(4);
+    KEEP(*(.trap));
+    *(.trap.*);
     _erwtext = .;
   } > REGION_RWTEXT
   _rwtext_size = _erwtext - _srwtext + 8;