diff --git a/CHANGELOG.md b/CHANGELOG.md index 58a5fcd1a21..e88720ac121 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -54,10 +54,12 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 - Sometimes half-duplex non-DMA SPI reads were reading garbage in non-release mode (#552) - ESP32-C3: Fix GPIO5 ADC channel id (#562) - ESP32-H2: Fix direct-boot feature +- ESP32-C6: Support FOSC CLK calibration for ECO1+ chip revisions ### Changed - Improve examples documentation (#533) +- esp32h2-hal: added README (#585) ### Breaking diff --git a/esp-hal-common/src/rtc_cntl/rtc/esp32c6.rs b/esp-hal-common/src/rtc_cntl/rtc/esp32c6.rs index 0cb9d5cc181..5ba8ee539cf 100644 --- a/esp-hal-common/src/rtc_cntl/rtc/esp32c6.rs +++ b/esp-hal-common/src/rtc_cntl/rtc/esp32c6.rs @@ -4,6 +4,7 @@ use strum::FromRepr; use crate::{ clock::{clocks_ll::regi2c_write_mask, Clock, XtalClock}, peripherals::{LP_AON, LP_CLKRST, PCR, PMU, TIMG0}, + soc::efuse::{Efuse, WAFER_VERSION_MAJOR, WAFER_VERSION_MINOR}, }; const I2C_DIG_REG: u8 = 0x6d; @@ -106,6 +107,7 @@ fn modem_clk_domain_active_state_icg_map_preinit() { unsafe { let pmu = &*PMU::PTR; let lp_clkrst = &*LP_CLKRST::PTR; + let pcr = &*PCR::PTR; pmu.hp_active_icg_modem .modify(|_, w| w.hp_active_dig_icg_modem_code().bits(2)); @@ -142,6 +144,10 @@ fn modem_clk_domain_active_state_icg_map_preinit() { lp_clkrst .rc32k_cntl .modify(|_, w| w.rc32k_dfreq().bits(100)); + + // https://github.com/espressif/esp-idf/commit/e3148369f32fdc6de62c35a67f7adb6f4faef4e3#diff-cc84d279f2f3d77fe252aa40a64d4813f271a52b5a4055e876efd012d888e135R810-R815 + pcr.ctrl_tick_conf + .modify(|_, w| w.fosc_tick_num().bits(255 as u8)); } } @@ -556,7 +562,24 @@ impl RtcClock { let cal_val = loop { if timg0.rtccalicfg.read().rtc_cali_rdy().bit_is_set() { - break timg0.rtccalicfg1.read().rtc_cali_value().bits(); + let minor: u8 = Efuse::read_field_le(WAFER_VERSION_MINOR); + let major: u8 = Efuse::read_field_le(WAFER_VERSION_MAJOR); + + // The Fosc CLK of calibration circuit is divided by 32 for ECO1. + // So we need to multiply the frequency of the Fosc for ECO1 and above chips by + // 32 times. And ensure that this modification will not affect + // ECO0. PS: For ESP32C6 ECO0 chip version is v0.0 only, which + // means that both MAJOR and MINOR are 0. The chip version is + // calculated using the following formula: MAJOR * 100 + MINOR. (if the result + // is 1, then version is v0.1) https://github.com/espressif/esp-idf/commit/e3148369f32fdc6de62c35a67f7adb6f4faef4e3 + if (major * 100 + minor) > 0 { + if cal_clk == RtcCalSel::RtcCalRcFast { + break timg0.rtccalicfg1.read().rtc_cali_value().bits() >> 5; + } + break timg0.rtccalicfg1.read().rtc_cali_value().bits(); + } else { + break timg0.rtccalicfg1.read().rtc_cali_value().bits(); + } } if timg0.rtccalicfg2.read().rtc_cali_timeout().bit_is_set() { @@ -619,6 +642,22 @@ impl RtcClock { /// issue, or lack of 32 XTAL on board). fn calibrate(cal_clk: RtcCalSel, slowclk_cycles: u32) -> u32 { let xtal_freq = RtcClock::get_xtal_freq(); + + let minor: u8 = Efuse::read_field_le(WAFER_VERSION_MINOR); + let major: u8 = Efuse::read_field_le(WAFER_VERSION_MAJOR); + + // The Fosc CLK of calibration circuit is divided by 32 for ECO1. + // So we need to divide the calibrate cycles of the FOSC for ECO1 and above + // chips by 32 to avoid excessive calibration time.*/ + // PS: For ESP32C6 ECO0 chip version is v0.0 only, which means that both MAJOR + // and MINOR are 0. The chip version is calculated using the following + // formula: MAJOR * 100 + MINOR. (if the result is 1, then version is v0.1) + if (major * 100 + minor) > 0 { + if cal_clk == RtcCalSel::RtcCalRcFast { + let slowclk_cycles = slowclk_cycles >> 5; + } + } + let xtal_cycles = RtcClock::calibrate_internal(cal_clk, slowclk_cycles) as u64; let divider = xtal_freq.mhz() as u64 * slowclk_cycles as u64; let period_64 = ((xtal_cycles << RtcClock::CAL_FRACT) + divider / 2u64 - 1u64) / divider; diff --git a/esp32h2-hal/README.md b/esp32h2-hal/README.md index 4ef79560392..c21b51c476c 100644 --- a/esp32h2-hal/README.md +++ b/esp32h2-hal/README.md @@ -1,9 +1,9 @@ # esp32h2-hal - + +[![Matrix](https://img.shields.io/matrix/esp-rs:matrix.org?label=join%20matrix&labelColor=1C2C2E&color=BEC5C9&logo=matrix&style=flat-square)](https://matrix.to/#/#esp-rs:matrix.org) `no_std` HAL for the ESP32-H2 from Espressif. Implements a number of the traits defined by [embedded-hal](https://github.com/rust-embedded/embedded-hal). @@ -11,7 +11,7 @@ This device uses the RISC-V ISA, which is officially supported by the Rust compi ## Getting Started @@ -27,13 +27,13 @@ $ rustup target add riscv32imac-unknown-none-elf #### IDF Bootloader -The [IDF second stage bootloader](https://docs.espressif.com/projects/esp-idf/en/latest/esp32c6/api-guides/startup.html#second-stage-bootloader) is the default bootloader solution. +The [IDF second stage bootloader](https://docs.espressif.com/projects/esp-idf/en/latest/esp32h2/api-guides/startup.html#second-stage-bootloader) is the default bootloader solution. By default, [espflash](https://github.com/esp-rs/espflash) fetches the required binaries (Bootloader and Partition Table) and flashes them onto the target device together with the Rust-based application firmware image. #### Direct Boot -[Direct Boot](https://github.com/espressif/esp32c6-direct-boot-example#direct-boot-in-esp32-c6) allows an application stored in the External Flash to be executed directly, without being copied into Internal RAM. +Direct Boot allows an application stored in the External Flash to be executed directly, without being copied into Internal RAM. ##### Booting the Hello World example using Direct Boot @@ -52,14 +52,14 @@ cargo espflash --release --format direct-boot --features direct-boot --example h The ROM Bootloader will identify the firmware image built with Direct Boot support and load it appropriately from the External Flash: ```shell -ESP-ROM:esp32c6-20220919 -Build:Sep 19 2022 -rst:0x1 (POWERON),boot:0x6e (SPI_FAST_FLASH_BOOT) +ESP-ROM:esp32h2-20221101 +Build:Nov 1 2022 +rst:0x1 (POWERON),boot:0xc (SPI_FAST_FLASH_BOOT) Hello world! Hello world! Hello world! ``` ---> + ## License Licensed under either of: