diff --git a/CHANGELOG.md b/CHANGELOG.md
index 9cae61683cf..5a9b4f4d09c 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -51,7 +51,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Fixed CI by pinning the log crate to 0.4.18 (#600)
 - ESP32-S3: Fix calculation of PSRAM start address
 - Fixed wrong variable access (FOSC CLK calibration for ESP32-C6 #593)
-
+- Fixed [trap location in ram](https://github.com/esp-rs/esp-hal/pull/605#issuecomment-1604039683) (#605)
 ### Changed
 
 - Improve examples documentation (#533)
diff --git a/esp32c2-hal/ld/bl-riscv-link.x b/esp32c2-hal/ld/bl-riscv-link.x
index 86b77a7d3ea..8155d49ed52 100644
--- a/esp32c2-hal/ld/bl-riscv-link.x
+++ b/esp32c2-hal/ld/bl-riscv-link.x
@@ -67,7 +67,7 @@ SECTIONS {
     *(.trap.*);
   } > RWTEXT
 }
-INSERT AFTER .rwtext;
+INSERT BEFORE .rwtext;
 
 SECTIONS {
   /**
diff --git a/esp32c2-hal/ld/db-riscv-link.x b/esp32c2-hal/ld/db-riscv-link.x
index 091e34096a5..27ac6abdbf0 100644
--- a/esp32c2-hal/ld/db-riscv-link.x
+++ b/esp32c2-hal/ld/db-riscv-link.x
@@ -89,10 +89,10 @@ SECTIONS
   _data_size = _data_end - _data_start + 8;
   .rwtext ORIGIN(REGION_RWTEXT) + _data_size : AT(_text_size + _rodata_size + _data_size){
     _srwtext = .;
-    *(.rwtext);
-    . = ALIGN(4);
     KEEP(*(.trap));
     *(.trap.*);
+    *(.rwtext);
+    . = ALIGN(4);
     _erwtext = .;
   } > REGION_RWTEXT
   _rwtext_size = _erwtext - _srwtext + 8;
diff --git a/esp32c3-hal/ld/bl-riscv-link.x b/esp32c3-hal/ld/bl-riscv-link.x
index 2603d6f2ee6..765bda447f0 100644
--- a/esp32c3-hal/ld/bl-riscv-link.x
+++ b/esp32c3-hal/ld/bl-riscv-link.x
@@ -67,7 +67,7 @@ SECTIONS {
     *(.trap.*);
   } > RWTEXT
 }
-INSERT AFTER .rwtext;
+INSERT BEFORE .rwtext;
 
 SECTIONS {
   /**
diff --git a/esp32c3-hal/ld/db-riscv-link.x b/esp32c3-hal/ld/db-riscv-link.x
index 316ab1eae8d..60d9bc3a1d0 100644
--- a/esp32c3-hal/ld/db-riscv-link.x
+++ b/esp32c3-hal/ld/db-riscv-link.x
@@ -89,10 +89,10 @@ SECTIONS
   _data_size = _data_end - _data_start + 8;
   .rwtext ORIGIN(REGION_RWTEXT) + _data_size : AT(_text_size + _rodata_size + _data_size){
     _srwtext = .;
-    *(.rwtext);
-    . = ALIGN(4);
     KEEP(*(.trap));
     *(.trap.*);
+    *(.rwtext);
+    . = ALIGN(4);
     _erwtext = .;
   } > REGION_RWTEXT
   _rwtext_size = _erwtext - _srwtext + 8;
diff --git a/esp32c3-hal/ld/mb-riscv-link.x b/esp32c3-hal/ld/mb-riscv-link.x
index edfe427c36c..a4945140eba 100644
--- a/esp32c3-hal/ld/mb-riscv-link.x
+++ b/esp32c3-hal/ld/mb-riscv-link.x
@@ -64,9 +64,9 @@ SECTIONS
     KEEP(*(.init));
     KEEP(*(.init.rust));
     KEEP(*(.text.abort));
-    . = ALIGN(4);
     KEEP(*(.trap));
     *(.trap.*);
+    . = ALIGN(4);
 
     *libriscv-*.rlib:riscv.*(.literal .text .literal.* .text.*);
     *libesp_riscv_rt-*.rlib:esp-riscv-rt.*(.literal .text .literal.* .text.*);
diff --git a/esp32c6-hal/ld/bl-riscv-link.x b/esp32c6-hal/ld/bl-riscv-link.x
index 4719a464d99..a76cdf3ad5b 100644
--- a/esp32c6-hal/ld/bl-riscv-link.x
+++ b/esp32c6-hal/ld/bl-riscv-link.x
@@ -71,7 +71,7 @@ SECTIONS {
     *(.trap.*);
   } > RWTEXT
 }
-INSERT AFTER .rwtext;
+INSERT BEFORE .rwtext;
 
 SECTIONS {
   /**
diff --git a/esp32c6-hal/ld/db-riscv-link.x b/esp32c6-hal/ld/db-riscv-link.x
index 3b1a667e000..4105669d967 100644
--- a/esp32c6-hal/ld/db-riscv-link.x
+++ b/esp32c6-hal/ld/db-riscv-link.x
@@ -94,10 +94,10 @@ SECTIONS
   _data_size = _data_end - _data_start + 8;
   .rwtext ORIGIN(REGION_RWTEXT) + _data_size : AT(_text_size + _rodata_size + _data_size){
     _srwtext = .;
-    *(.rwtext);
-    . = ALIGN(4);
     KEEP(*(.trap));
     *(.trap.*);
+    *(.rwtext);
+    . = ALIGN(4);
     _erwtext = .;
   } > REGION_RWTEXT
   _rwtext_size = _erwtext - _srwtext + 8;
diff --git a/esp32h2-hal/ld/bl-riscv-link.x b/esp32h2-hal/ld/bl-riscv-link.x
index 58e8ee7763a..3982c1ec8f8 100644
--- a/esp32h2-hal/ld/bl-riscv-link.x
+++ b/esp32h2-hal/ld/bl-riscv-link.x
@@ -65,7 +65,7 @@ SECTIONS {
     *(.trap.*);
   } > RWTEXT
 }
-INSERT AFTER .rwtext;
+INSERT BEFORE .rwtext;
 
 SECTIONS {
   /**
diff --git a/esp32h2-hal/ld/db-riscv-link.x b/esp32h2-hal/ld/db-riscv-link.x
index c06f798d03b..a0fe551c92e 100644
--- a/esp32h2-hal/ld/db-riscv-link.x
+++ b/esp32h2-hal/ld/db-riscv-link.x
@@ -94,10 +94,10 @@ SECTIONS
   _data_size = _data_end - _data_start + 8;
   .rwtext ORIGIN(REGION_RWTEXT) + _data_size : AT(_text_size + _rodata_size + _data_size){
     _srwtext = .;
-    *(.rwtext);
-    . = ALIGN(4);
     KEEP(*(.trap));
     *(.trap.*);
+    *(.rwtext);
+    . = ALIGN(4);
     _erwtext = .;
   } > REGION_RWTEXT
   _rwtext_size = _erwtext - _srwtext + 8;