diff --git a/CHANGELOG.md b/CHANGELOG.md
index d8da2138948..c8438a0b547 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -40,6 +40,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Update ESP32-H2 and ESP32-C6 clocks and remove `i2c_clock` for all chips but ESP32 (#592)
 - Use both timers in `TIMG0` for embassy time driver when able (#609)
 - Re-work `RadioExt` implementations, add support for ESP32-H2 (#627)
+- Improve examples documentation (#533)
+- esp32h2-hal: added README (#585)
 
 ### Fixed
 
@@ -61,13 +63,9 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Fixed a possible overlap of `.data` and `.rwtext` (#616)
 - Avoid SDA/SCL being low while configuring pins for I2C
 
-### Changed
-
-- Improve examples documentation (#533)
-- esp32h2-hal: added README (#585)
-
 ### Breaking
 
+- Simplified user-facing SpiDma and I2s types (#626)
 - Significantly simplified user-facing GPIO pin types. (#553)
 - No longer re-export the `soc` module and the contents of the `interrupt` module at the package level (#607)
 
diff --git a/esp-hal-common/src/dma/gdma.rs b/esp-hal-common/src/dma/gdma.rs
index e1e7d97852d..a9c0ad55f7d 100644
--- a/esp-hal-common/src/dma/gdma.rs
+++ b/esp-hal-common/src/dma/gdma.rs
@@ -12,6 +12,12 @@ macro_rules! impl_channel {
             #[non_exhaustive]
             pub struct [<Channel $num>] {}
 
+            impl ChannelTypes for [<Channel $num>] {
+                type P = [<SuitablePeripheral $num>];
+                type Tx<'a> = ChannelTx<'a, [<Channel $num TxImpl>], [<Channel $num>]>;
+                type Rx<'a> = ChannelRx<'a, [<Channel $num RxImpl>], [<Channel $num>]>;
+            }
+
             impl RegisterAccess for [<Channel $num>] {
                 fn init_channel() {
                     // nothing special to be done here
@@ -402,7 +408,7 @@ macro_rules! impl_channel {
                     tx_descriptors: &'a mut [u32],
                     rx_descriptors: &'a mut [u32],
                     priority: DmaPriority,
-                ) -> Channel<ChannelTx<'a, [<Channel $num TxImpl>], [<Channel $num>]>, ChannelRx<'a, [<Channel $num RxImpl>], [<Channel $num>]>, [<SuitablePeripheral $num>]> {
+                ) -> Channel<'a, [<Channel $num>]> {
                     let mut tx_impl = [<Channel $num TxImpl>] {};
                     tx_impl.init(burst_mode, priority);
 
@@ -436,7 +442,6 @@ macro_rules! impl_channel {
                     Channel {
                         tx: tx_channel,
                         rx: rx_channel,
-                        _phantom: PhantomData::default(),
                     }
                 }
             }
diff --git a/esp-hal-common/src/dma/mod.rs b/esp-hal-common/src/dma/mod.rs
index 1e08934acc8..7e4f604a3c8 100644
--- a/esp-hal-common/src/dma/mod.rs
+++ b/esp-hal-common/src/dma/mod.rs
@@ -830,16 +830,20 @@ pub trait RegisterAccess {
     fn unlisten_in_eof();
     fn unlisten_out_eof();
 }
+
+pub trait ChannelTypes {
+    type P: PeripheralMarker;
+    type Tx<'a>: Tx;
+    type Rx<'a>: Rx;
+}
+
 /// DMA Channel
-pub struct Channel<TX, RX, P>
+pub struct Channel<'d, C>
 where
-    TX: Tx,
-    RX: Rx,
-    P: PeripheralMarker,
+    C: ChannelTypes,
 {
-    pub(crate) tx: TX,
-    pub(crate) rx: RX,
-    _phantom: PhantomData<P>,
+    pub(crate) tx: C::Tx<'d>,
+    pub(crate) rx: C::Rx<'d>,
 }
 
 /// Trait to be implemented for an in progress dma transfer.
diff --git a/esp-hal-common/src/dma/pdma.rs b/esp-hal-common/src/dma/pdma.rs
index 976de292b7c..e2c254b7eac 100644
--- a/esp-hal-common/src/dma/pdma.rs
+++ b/esp-hal-common/src/dma/pdma.rs
@@ -12,6 +12,12 @@ macro_rules! ImplSpiChannel {
             #[non_exhaustive]
             pub struct [<Spi $num DmaChannel>] {}
 
+            impl ChannelTypes for [<Spi $num DmaChannel>] {
+                type P = [<Spi $num DmaSuitablePeripheral>];
+                type Tx<'a> = ChannelTx<'a,[<Spi $num DmaChannelTxImpl>], [<Spi $num DmaChannel>]>;
+                type Rx<'a> = ChannelRx<'a,[<Spi $num DmaChannelRxImpl>], [<Spi $num DmaChannel>]>;
+            }
+
             impl RegisterAccess for [<Spi $num DmaChannel>] {
                 fn init_channel() {
                     // (only) on ESP32 we need to configure DPORT for the SPI DMA channels
@@ -232,11 +238,7 @@ macro_rules! ImplSpiChannel {
                     tx_descriptors: &'a mut [u32],
                     rx_descriptors: &'a mut [u32],
                     priority: DmaPriority,
-                ) -> Channel<
-                    ChannelTx<'a,[<Spi $num DmaChannelTxImpl>], [<Spi $num DmaChannel>]>,
-                    ChannelRx<'a,[<Spi $num DmaChannelRxImpl>], [<Spi $num DmaChannel>]>,
-                    [<Spi $num DmaSuitablePeripheral>],
-                > {
+                ) -> Channel<'a, [<Spi $num DmaChannel>]> {
                     let mut tx_impl = [<Spi $num DmaChannelTxImpl>] {};
                     tx_impl.init(burst_mode, priority);
 
@@ -270,7 +272,6 @@ macro_rules! ImplSpiChannel {
                     Channel {
                         tx: tx_channel,
                         rx: rx_channel,
-                        _phantom: PhantomData::default(),
                     }
                 }
             }
@@ -283,6 +284,12 @@ macro_rules! ImplI2sChannel {
         paste::paste! {
             pub struct [<I2s $num DmaChannel>] {}
 
+            impl ChannelTypes for [<I2s $num DmaChannel>] {
+                type P = [<I2s $num DmaSuitablePeripheral>];
+                type Tx<'a> = ChannelTx<'a,[<I2s $num DmaChannelTxImpl>], [<I2s $num DmaChannel>]>;
+                type Rx<'a> = ChannelRx<'a,[<I2s $num DmaChannelRxImpl>], [<I2s $num DmaChannel>]>;
+            }
+
             impl RegisterAccess for [<I2s $num DmaChannel>] {
                 fn init_channel() {
                     // nothing to do
@@ -471,11 +478,7 @@ macro_rules! ImplI2sChannel {
                     tx_descriptors: &'a mut [u32],
                     rx_descriptors: &'a mut [u32],
                     priority: DmaPriority,
-                ) -> Channel<
-                    ChannelTx<'a,[<I2s $num DmaChannelTxImpl>], [<I2s $num DmaChannel>]>,
-                    ChannelRx<'a,[<I2s $num DmaChannelRxImpl>], [<I2s $num DmaChannel>]>,
-                    [<I2s $num DmaSuitablePeripheral>],
-                > {
+                ) -> Channel<'a, [<I2s $num DmaChannel>]> {
                     let mut tx_impl = [<I2s $num DmaChannelTxImpl>] {};
                     tx_impl.init(burst_mode, priority);
 
@@ -509,7 +512,6 @@ macro_rules! ImplI2sChannel {
                     Channel {
                         tx: tx_channel,
                         rx: rx_channel,
-                        _phantom: PhantomData::default(),
                     }
                 }
             }
diff --git a/esp-hal-common/src/i2s.rs b/esp-hal-common/src/i2s.rs
index 29895024683..7b4487f0a54 100644
--- a/esp-hal-common/src/i2s.rs
+++ b/esp-hal-common/src/i2s.rs
@@ -7,7 +7,16 @@ use private::*;
 use crate::dma::I2s1Peripheral;
 use crate::{
     clock::Clocks,
-    dma::{Channel, DmaError, DmaTransfer, I2s0Peripheral, I2sPeripheral, Rx, Tx},
+    dma::{
+        Channel,
+        ChannelTypes,
+        DmaError,
+        DmaTransfer,
+        I2s0Peripheral,
+        I2sPeripheral,
+        RxPrivate,
+        TxPrivate,
+    },
     gpio::{InputPin, OutputPin},
     peripheral::{Peripheral, PeripheralRef},
     system::PeripheralClockControl,
@@ -271,21 +280,21 @@ impl I2sMclkPin for NoMclk {
 }
 
 /// An in-progress DMA write transfer.
-pub struct I2sWriteDmaTransfer<T, P, TX, BUFFER>
+pub struct I2sWriteDmaTransfer<'d, T, P, CH, BUFFER>
 where
     T: RegisterAccess,
+    CH: ChannelTypes,
     P: I2sTxPins,
-    TX: Tx,
 {
-    i2s_tx: I2sTx<T, P, TX>,
+    i2s_tx: I2sTx<'d, T, P, CH>,
     buffer: BUFFER,
 }
 
-impl<'d, T, P, TX, BUFFER> I2sWriteDmaTransfer<T, P, TX, BUFFER>
+impl<'d, T, P, CH, BUFFER> I2sWriteDmaTransfer<'d, T, P, CH, BUFFER>
 where
     T: RegisterAccess,
+    CH: ChannelTypes,
     P: I2sTxPins,
-    TX: Tx,
 {
     /// Amount of bytes which can be pushed.
     /// Only useful for circular DMA transfers
@@ -300,16 +309,16 @@ where
     }
 }
 
-impl<'d, T, P, TX, BUFFER> DmaTransfer<BUFFER, I2sTx<T, P, TX>>
-    for I2sWriteDmaTransfer<T, P, TX, BUFFER>
+impl<'d, T, P, CH, BUFFER> DmaTransfer<BUFFER, I2sTx<'d, T, P, CH>>
+    for I2sWriteDmaTransfer<'d, T, P, CH, BUFFER>
 where
     T: RegisterAccess,
+    CH: ChannelTypes,
     P: I2sTxPins,
-    TX: Tx,
 {
     /// Wait for the DMA transfer to complete and return the buffers and the
     /// I2sTx instance.
-    fn wait(self) -> (BUFFER, I2sTx<T, P, TX>) {
+    fn wait(self) -> (BUFFER, I2sTx<'d, T, P, CH>) {
         self.i2s_tx.wait_tx_dma_done().ok(); // waiting for the DMA transfer is not enough
 
         // `DmaTransfer` needs to have a `Drop` implementation, because we accept
@@ -333,11 +342,11 @@ where
     }
 }
 
-impl<'d, T, P, TX, BUFFER> Drop for I2sWriteDmaTransfer<T, P, TX, BUFFER>
+impl<'d, T, P, CH, BUFFER> Drop for I2sWriteDmaTransfer<'d, T, P, CH, BUFFER>
 where
     T: RegisterAccess,
+    CH: ChannelTypes,
     P: I2sTxPins,
-    TX: Tx,
 {
     fn drop(&mut self) {
         self.i2s_tx.wait_tx_dma_done().ok();
@@ -350,20 +359,17 @@ pub trait I2sWrite<W> {
 }
 
 /// Initiate a DMA tx transfer
-pub trait I2sWriteDma<'d, T, P, TX, TXBUF>
+pub trait I2sWriteDma<'d, T, P, CH, TXBUF>
 where
     T: RegisterAccess,
+    CH: ChannelTypes,
     P: I2sTxPins,
-    TX: Tx,
 {
     /// Write I2S.
     /// Returns [I2sWriteDmaTransfer] which represents the in-progress DMA
     /// transfer
-    fn write_dma(self, words: TXBUF) -> Result<I2sWriteDmaTransfer<T, P, TX, TXBUF>, Error>
+    fn write_dma(self, words: TXBUF) -> Result<I2sWriteDmaTransfer<'d, T, P, CH, TXBUF>, Error>
     where
-        T: RegisterAccess,
-        P: I2sTxPins,
-        TX: Tx,
         TXBUF: ReadBuffer<Word = u8>;
 
     /// Continuously write to I2S. Returns [I2sWriteDmaTransfer] which
@@ -371,30 +377,27 @@ where
     fn write_dma_circular(
         self,
         words: TXBUF,
-    ) -> Result<I2sWriteDmaTransfer<T, P, TX, TXBUF>, Error>
+    ) -> Result<I2sWriteDmaTransfer<'d, T, P, CH, TXBUF>, Error>
     where
-        T: RegisterAccess,
-        P: I2sTxPins,
-        TX: Tx,
         TXBUF: ReadBuffer<Word = u8>;
 }
 
 /// An in-progress DMA read transfer.
-pub struct I2sReadDmaTransfer<T, P, RX, BUFFER>
+pub struct I2sReadDmaTransfer<'d, T, P, CH, BUFFER>
 where
     T: RegisterAccess,
+    CH: ChannelTypes,
     P: I2sRxPins,
-    RX: Rx,
 {
-    i2s_rx: I2sRx<T, P, RX>,
+    i2s_rx: I2sRx<'d, T, P, CH>,
     buffer: BUFFER,
 }
 
-impl<'d, T, P, RX, BUFFER> I2sReadDmaTransfer<T, P, RX, BUFFER>
+impl<'d, T, P, CH, BUFFER> I2sReadDmaTransfer<'d, T, P, CH, BUFFER>
 where
     T: RegisterAccess,
+    CH: ChannelTypes,
     P: I2sRxPins,
-    RX: Rx,
 {
     /// Amount of bytes which can be popped
     pub fn available(&mut self) -> usize {
@@ -409,7 +412,7 @@ where
     /// I2sTx instance after copying the read data to the given buffer.
     /// Length of the received data is returned at the third element of the
     /// tuple.
-    pub fn wait_receive(mut self, dst: &mut [u8]) -> (BUFFER, I2sRx<T, P, RX>, usize) {
+    pub fn wait_receive(mut self, dst: &mut [u8]) -> (BUFFER, I2sRx<'d, T, P, CH>, usize) {
         self.i2s_rx.wait_rx_dma_done().ok(); // waiting for the DMA transfer is not enough
 
         let len = self.i2s_rx.rx_channel.drain_buffer(dst).unwrap();
@@ -430,16 +433,16 @@ where
     }
 }
 
-impl<'d, T, P, RX, BUFFER> DmaTransfer<BUFFER, I2sRx<T, P, RX>>
-    for I2sReadDmaTransfer<T, P, RX, BUFFER>
+impl<'d, T, P, CH, BUFFER> DmaTransfer<BUFFER, I2sRx<'d, T, P, CH>>
+    for I2sReadDmaTransfer<'d, T, P, CH, BUFFER>
 where
     T: RegisterAccess,
+    CH: ChannelTypes,
     P: I2sRxPins,
-    RX: Rx,
 {
     /// Wait for the DMA transfer to complete and return the buffers and the
     /// I2sTx instance.
-    fn wait(self) -> (BUFFER, I2sRx<T, P, RX>) {
+    fn wait(self) -> (BUFFER, I2sRx<'d, T, P, CH>) {
         self.i2s_rx.wait_rx_dma_done().ok(); // waiting for the DMA transfer is not enough
 
         // `DmaTransfer` needs to have a `Drop` implementation, because we accept
@@ -463,11 +466,11 @@ where
     }
 }
 
-impl<T, P, RX, BUFFER> Drop for I2sReadDmaTransfer<T, P, RX, BUFFER>
+impl<T, P, CH, BUFFER> Drop for I2sReadDmaTransfer<'_, T, P, CH, BUFFER>
 where
     T: RegisterAccess,
+    CH: ChannelTypes,
     P: I2sRxPins,
-    RX: Rx,
 {
     fn drop(&mut self) {
         self.i2s_rx.wait_rx_dma_done().ok();
@@ -480,70 +483,59 @@ pub trait I2sRead<W> {
 }
 
 /// Initiate a DMA rx transfer
-pub trait I2sReadDma<'d, T, P, RX, RXBUF>
+pub trait I2sReadDma<'d, T, P, CH, RXBUF>
 where
     T: RegisterAccess,
+    CH: ChannelTypes,
     P: I2sRxPins,
-    RX: Rx,
 {
     /// Read I2S.
     /// Returns [I2sReadDmaTransfer] which represents the in-progress DMA
     /// transfer
-    fn read_dma(self, words: RXBUF) -> Result<I2sReadDmaTransfer<T, P, RX, RXBUF>, Error>
+    fn read_dma(self, words: RXBUF) -> Result<I2sReadDmaTransfer<'d, T, P, CH, RXBUF>, Error>
     where
-        T: RegisterAccess,
-        P: I2sRxPins,
-        RX: Rx,
         RXBUF: WriteBuffer<Word = u8>;
 
     /// Continuously read from I2S.
     /// Returns [I2sReadDmaTransfer] which represents the in-progress DMA
     /// transfer
-    fn read_dma_circular(self, words: RXBUF) -> Result<I2sReadDmaTransfer<T, P, RX, RXBUF>, Error>
+    fn read_dma_circular(
+        self,
+        words: RXBUF,
+    ) -> Result<I2sReadDmaTransfer<'d, T, P, CH, RXBUF>, Error>
     where
-        T: RegisterAccess,
-        P: I2sRxPins,
-        RX: Rx,
         RXBUF: WriteBuffer<Word = u8>;
 }
 
 /// Instance of the I2S peripheral driver
-pub struct I2s<'d, I, T, P, TX, RX>
+pub struct I2s<'d, I, P, CH>
 where
-    I: Instance<T>,
-    T: RegisterAccess + Clone,
+    I: Instance,
     P: I2sMclkPin,
-    TX: Tx,
-    RX: Rx,
+    CH: ChannelTypes,
 {
     _peripheral: PeripheralRef<'d, I>,
-    _register_access: T,
     _pins: P,
-    pub i2s_tx: TxCreator<T, TX>,
-    pub i2s_rx: RxCreator<T, RX>,
+    pub i2s_tx: TxCreator<'d, I::Peripheral, CH>,
+    pub i2s_rx: RxCreator<'d, I::Peripheral, CH>,
 }
 
-impl<'d, I, T, P, TX, RX> I2s<'d, I, T, P, TX, RX>
+impl<'d, I, P, CH> I2s<'d, I, P, CH>
 where
-    I: Instance<T>,
-    T: RegisterAccess + Clone,
+    I: Instance,
     P: I2sMclkPin,
-    TX: Tx,
-    RX: Rx,
+    CH: ChannelTypes,
 {
-    fn new_internal<IP>(
+    fn new_internal(
         i2s: impl Peripheral<P = I> + 'd,
         mut pins: P,
         standard: Standard,
         data_format: DataFormat,
         sample_rate: impl Into<fugit::HertzU32>,
-        mut channel: Channel<TX, RX, IP>,
+        mut channel: Channel<'d, CH>,
         peripheral_clock_control: &mut PeripheralClockControl,
         clocks: &Clocks,
-    ) -> Self
-    where
-        IP: I2sPeripheral,
-    {
+    ) -> Self {
         // on ESP32-C3 / ESP32-S3 and later RX and TX are independent and
         // could be configured totally independently but for now handle all
         // the targets the same and force same configuration for both, TX and RX
@@ -566,7 +558,6 @@ where
 
         Self {
             _peripheral: i2s,
-            _register_access: register_access.clone(),
             _pins: pins,
             i2s_tx: TxCreator {
                 register_access: register_access.clone(),
@@ -581,14 +572,12 @@ where
 }
 
 /// Construct a new I2S peripheral driver instance for the first I2S peripheral
-pub trait I2s0New<'d, I, T, P, TX, RX, IP>
+pub trait I2s0New<'d, I, P, CH>
 where
-    I: Instance<T>,
-    T: RegisterAccess + Clone,
+    I: Instance,
     P: I2sMclkPin,
-    TX: Tx,
-    RX: Rx,
-    IP: I2sPeripheral + I2s0Peripheral,
+    CH: ChannelTypes,
+    CH::P: I2sPeripheral + I2s0Peripheral,
 {
     fn new(
         i2s: impl Peripheral<P = I> + 'd,
@@ -596,20 +585,18 @@ where
         standard: Standard,
         data_format: DataFormat,
         sample_rate: impl Into<fugit::HertzU32>,
-        channel: Channel<TX, RX, IP>,
+        channel: Channel<'d, CH>,
         peripheral_clock_control: &mut PeripheralClockControl,
         clocks: &Clocks,
     ) -> Self;
 }
 
-impl<'d, I, T, P, TX, RX, IP> I2s0New<'d, I, T, P, TX, RX, IP> for I2s<'d, I, T, P, TX, RX>
+impl<'d, I, P, CH> I2s0New<'d, I, P, CH> for I2s<'d, I, P, CH>
 where
-    I: Instance<T> + I2s0Instance,
-    T: RegisterAccess + Clone,
+    I: Instance + I2s0Instance,
     P: I2sMclkPin,
-    TX: Tx,
-    RX: Rx,
-    IP: I2sPeripheral + I2s0Peripheral,
+    CH: ChannelTypes,
+    CH::P: I2sPeripheral + I2s0Peripheral,
 {
     fn new(
         i2s: impl Peripheral<P = I> + 'd,
@@ -617,7 +604,7 @@ where
         standard: Standard,
         data_format: DataFormat,
         sample_rate: impl Into<fugit::HertzU32>,
-        channel: Channel<TX, RX, IP>,
+        channel: Channel<'d, CH>,
         peripheral_clock_control: &mut PeripheralClockControl,
         clocks: &Clocks,
     ) -> Self {
@@ -636,14 +623,12 @@ where
 
 /// Construct a new I2S peripheral driver instance for the second I2S peripheral
 #[cfg(any(esp32s3))]
-pub trait I2s1New<'d, I, T, P, TX, RX, IP>
+pub trait I2s1New<'d, I, P, CH>
 where
-    I: Instance<T>,
-    T: RegisterAccess + Clone,
+    I: Instance,
     P: I2sMclkPin,
-    TX: Tx,
-    RX: Rx,
-    IP: I2sPeripheral + I2s1Peripheral,
+    CH: ChannelTypes,
+    CH::P: I2sPeripheral + I2s1Peripheral,
 {
     fn new(
         i2s: impl Peripheral<P = I> + 'd,
@@ -651,21 +636,19 @@ where
         standard: Standard,
         data_format: DataFormat,
         sample_rate: impl Into<fugit::HertzU32>,
-        channel: Channel<TX, RX, IP>,
+        channel: Channel<'d, CH>,
         peripheral_clock_control: &mut PeripheralClockControl,
         clocks: &Clocks,
     ) -> Self;
 }
 
 #[cfg(any(esp32s3))]
-impl<'d, I, T, P, TX, RX, IP> I2s1New<'d, I, T, P, TX, RX, IP> for I2s<'d, I, T, P, TX, RX>
+impl<'d, I, P, CH> I2s1New<'d, I, P, CH> for I2s<'d, I, P, CH>
 where
-    I: Instance<T> + I2s1Instance,
-    T: RegisterAccess + Clone,
+    I: Instance + I2s1Instance,
     P: I2sMclkPin,
-    TX: Tx,
-    RX: Rx,
-    IP: I2sPeripheral + I2s1Peripheral,
+    CH: ChannelTypes,
+    CH::P: I2sPeripheral + I2s1Peripheral,
 {
     fn new(
         i2s: impl Peripheral<P = I> + 'd,
@@ -673,7 +656,7 @@ where
         standard: Standard,
         data_format: DataFormat,
         sample_rate: impl Into<fugit::HertzU32>,
-        channel: Channel<TX, RX, IP>,
+        channel: Channel<'d, CH>,
         peripheral_clock_control: &mut PeripheralClockControl,
         clocks: &Clocks,
     ) -> Self {
@@ -691,24 +674,24 @@ where
 }
 
 /// I2S TX channel
-pub struct I2sTx<T, P, TX>
+pub struct I2sTx<'d, T, P, CH>
 where
     T: RegisterAccess,
+    CH: ChannelTypes,
     P: I2sTxPins,
-    TX: Tx,
 {
     register_access: T,
     _pins: P,
-    tx_channel: TX,
+    tx_channel: CH::Tx<'d>,
 }
 
-impl<T, P, TX> I2sTx<T, P, TX>
+impl<'d, T, P, CH> I2sTx<'d, T, P, CH>
 where
     T: RegisterAccess,
+    CH: ChannelTypes,
     P: I2sTxPins,
-    TX: Tx,
 {
-    fn new(mut register_access: T, mut pins: P, tx_channel: TX) -> Self {
+    fn new(mut register_access: T, mut pins: P, tx_channel: CH::Tx<'d>) -> Self {
         pins.configure(&mut register_access);
 
         Self {
@@ -749,7 +732,7 @@ where
         mut self,
         words: TXBUF,
         circular: bool,
-    ) -> Result<I2sWriteDmaTransfer<T, P, TX, TXBUF>, Error>
+    ) -> Result<I2sWriteDmaTransfer<'d, T, P, CH, TXBUF>, Error>
     where
         TXBUF: ReadBuffer<Word = u8>,
     {
@@ -787,11 +770,11 @@ where
     }
 }
 
-impl<T, P, TX, W> I2sWrite<W> for I2sTx<T, P, TX>
+impl<'d, T, P, W, CH> I2sWrite<W> for I2sTx<'d, T, P, CH>
 where
     T: RegisterAccess,
+    CH: ChannelTypes,
     P: I2sTxPins,
-    TX: Tx,
     W: AcceptedWord,
 {
     fn write(&mut self, words: &[W]) -> Result<(), Error> {
@@ -804,20 +787,23 @@ where
     }
 }
 
-impl<'d, T, P, TX, TXBUF> I2sWriteDma<'d, T, P, TX, TXBUF> for I2sTx<T, P, TX>
+impl<'d, T, P, CH, TXBUF> I2sWriteDma<'d, T, P, CH, TXBUF> for I2sTx<'d, T, P, CH>
 where
     T: RegisterAccess,
+    CH: ChannelTypes,
     P: I2sTxPins,
-    TX: Tx,
 {
-    fn write_dma(self, words: TXBUF) -> Result<I2sWriteDmaTransfer<T, P, TX, TXBUF>, Error>
+    fn write_dma(self, words: TXBUF) -> Result<I2sWriteDmaTransfer<'d, T, P, CH, TXBUF>, Error>
     where
         TXBUF: ReadBuffer<Word = u8>,
     {
         self.start_tx_transfer(words, false)
     }
 
-    fn write_dma_circular(self, words: TXBUF) -> Result<I2sWriteDmaTransfer<T, P, TX, TXBUF>, Error>
+    fn write_dma_circular(
+        self,
+        words: TXBUF,
+    ) -> Result<I2sWriteDmaTransfer<'d, T, P, CH, TXBUF>, Error>
     where
         TXBUF: ReadBuffer<Word = u8>,
     {
@@ -826,24 +812,24 @@ where
 }
 
 /// I2S RX channel
-pub struct I2sRx<T, P, RX>
+pub struct I2sRx<'d, T, P, CH>
 where
     T: RegisterAccess,
+    CH: ChannelTypes,
     P: I2sRxPins,
-    RX: Rx,
 {
     register_access: T,
     _pins: P,
-    rx_channel: RX,
+    rx_channel: CH::Rx<'d>,
 }
 
-impl<'d, T, P, RX> I2sRx<T, P, RX>
+impl<'d, T, P, CH> I2sRx<'d, T, P, CH>
 where
     T: RegisterAccess,
+    CH: ChannelTypes,
     P: I2sRxPins,
-    RX: Rx,
 {
-    fn new(mut register_access: T, mut pins: P, rx_channel: RX) -> Self {
+    fn new(mut register_access: T, mut pins: P, rx_channel: CH::Rx<'d>) -> Self {
         pins.configure(&mut register_access);
 
         Self {
@@ -884,7 +870,7 @@ where
         mut self,
         mut words: RXBUF,
         circular: bool,
-    ) -> Result<I2sReadDmaTransfer<T, P, RX, RXBUF>, Error>
+    ) -> Result<I2sReadDmaTransfer<'d, T, P, CH, RXBUF>, Error>
     where
         RXBUF: WriteBuffer<Word = u8>,
     {
@@ -929,11 +915,11 @@ where
     }
 }
 
-impl<W, T, P, RX> I2sRead<W> for I2sRx<T, P, RX>
+impl<'d, W, T, P, CH> I2sRead<W> for I2sRx<'d, T, P, CH>
 where
     T: RegisterAccess,
+    CH: ChannelTypes,
     P: I2sRxPins,
-    RX: Rx,
     W: AcceptedWord,
 {
     fn read(&mut self, words: &mut [W]) -> Result<(), Error> {
@@ -950,20 +936,23 @@ where
     }
 }
 
-impl<'d, T, P, RX, RXBUF> I2sReadDma<'d, T, P, RX, RXBUF> for I2sRx<T, P, RX>
+impl<'d, T, P, CH, RXBUF> I2sReadDma<'d, T, P, CH, RXBUF> for I2sRx<'d, T, P, CH>
 where
     T: RegisterAccess,
+    CH: ChannelTypes,
     P: I2sRxPins,
-    RX: Rx,
 {
-    fn read_dma(self, words: RXBUF) -> Result<I2sReadDmaTransfer<T, P, RX, RXBUF>, Error>
+    fn read_dma(self, words: RXBUF) -> Result<I2sReadDmaTransfer<'d, T, P, CH, RXBUF>, Error>
     where
         RXBUF: WriteBuffer<Word = u8>,
     {
         self.start_rx_transfer(words, false)
     }
 
-    fn read_dma_circular(self, words: RXBUF) -> Result<I2sReadDmaTransfer<T, P, RX, RXBUF>, Error>
+    fn read_dma_circular(
+        self,
+        words: RXBUF,
+    ) -> Result<I2sReadDmaTransfer<'d, T, P, CH, RXBUF>, Error>
     where
         RXBUF: WriteBuffer<Word = u8>,
     {
@@ -1003,7 +992,7 @@ mod private {
     use crate::peripherals::i2s1::RegisterBlock;
     use crate::{
         clock::Clocks,
-        dma::{DmaPeripheral, Rx, Tx},
+        dma::{ChannelTypes, DmaPeripheral},
         gpio::{InputSignal, OutputSignal},
         peripherals::I2S0,
         system::Peripheral,
@@ -1011,21 +1000,21 @@ mod private {
 
     pub trait I2sPins {}
 
-    pub struct TxCreator<T, TX>
+    pub struct TxCreator<'d, T, CH>
     where
         T: RegisterAccess + Clone,
-        TX: Tx,
+        CH: ChannelTypes,
     {
         pub register_access: T,
-        pub tx_channel: TX,
+        pub tx_channel: CH::Tx<'d>,
     }
 
-    impl<T, TX> TxCreator<T, TX>
+    impl<'d, T, CH> TxCreator<'d, T, CH>
     where
         T: RegisterAccess + Clone,
-        TX: Tx,
+        CH: ChannelTypes,
     {
-        pub fn with_pins<P>(self, pins: P) -> I2sTx<T, P, TX>
+        pub fn with_pins<P>(self, pins: P) -> I2sTx<'d, T, P, CH>
         where
             P: super::I2sTxPins,
         {
@@ -1033,21 +1022,21 @@ mod private {
         }
     }
 
-    pub struct RxCreator<T, RX>
+    pub struct RxCreator<'d, T, CH>
     where
         T: RegisterAccess + Clone,
-        RX: Rx,
+        CH: ChannelTypes,
     {
         pub register_access: T,
-        pub rx_channel: RX,
+        pub rx_channel: CH::Rx<'d>,
     }
 
-    impl<T, RX> RxCreator<T, RX>
+    impl<'d, T, CH> RxCreator<'d, T, CH>
     where
         T: RegisterAccess + Clone,
-        RX: Rx,
+        CH: ChannelTypes,
     {
-        pub fn with_pins<P>(self, pins: P) -> I2sRx<T, P, RX>
+        pub fn with_pins<P>(self, pins: P) -> I2sRx<'d, T, P, CH>
         where
             P: super::I2sRxPins,
         {
@@ -1059,14 +1048,15 @@ mod private {
 
     pub trait I2s1Instance {}
 
-    pub trait Instance<R>
-    where
-        R: RegisterAccess,
-    {
-        fn register_access(&self) -> R;
+    pub trait Instance {
+        type Peripheral: RegisterAccess + Clone;
+
+        fn register_access(&self) -> Self::Peripheral;
     }
 
-    impl Instance<I2sPeripheral0> for I2S0 {
+    impl Instance for I2S0 {
+        type Peripheral = I2sPeripheral0;
+
         fn register_access(&self) -> I2sPeripheral0 {
             I2sPeripheral0 {}
         }
@@ -1075,7 +1065,8 @@ mod private {
     impl I2s0Instance for I2S0 {}
 
     #[cfg(esp32s3)]
-    impl Instance<I2sPeripheral1> for crate::peripherals::I2S1 {
+    impl Instance for crate::peripherals::I2S1 {
+        type Peripheral = I2sPeripheral1;
         fn register_access(&self) -> I2sPeripheral1 {
             I2sPeripheral1 {}
         }
diff --git a/esp-hal-common/src/spi.rs b/esp-hal-common/src/spi.rs
index ba14c7f0b49..a89045617f4 100644
--- a/esp-hal-common/src/spi.rs
+++ b/esp-hal-common/src/spi.rs
@@ -753,42 +753,48 @@ pub mod dma {
     use crate::dma::Spi3Peripheral;
     use crate::{
         clock::Clocks,
-        dma::{Channel, DmaTransfer, DmaTransferRxTx, Rx, Spi2Peripheral, SpiPeripheral, Tx},
+        dma::{
+            Channel,
+            ChannelTypes,
+            DmaTransfer,
+            DmaTransferRxTx,
+            RxPrivate,
+            Spi2Peripheral,
+            SpiPeripheral,
+            TxPrivate,
+        },
         peripheral::PeripheralRef,
     };
 
-    pub trait WithDmaSpi2<'d, T, RX, TX, P, M>
+    pub trait WithDmaSpi2<'d, T, C, M>
     where
         T: Instance + Spi2Instance,
-        TX: Tx,
-        RX: Rx,
-        P: SpiPeripheral,
+        C: ChannelTypes,
+        C::P: SpiPeripheral,
         M: DuplexMode,
     {
-        fn with_dma(self, channel: Channel<TX, RX, P>) -> SpiDma<'d, T, TX, RX, P, M>;
+        fn with_dma(self, channel: Channel<'d, C>) -> SpiDma<'d, T, C, M>;
     }
 
     #[cfg(any(esp32, esp32s2, esp32s3))]
-    pub trait WithDmaSpi3<'d, T, RX, TX, P, M>
+    pub trait WithDmaSpi3<'d, T, C, M>
     where
         T: Instance + Spi3Instance,
-        TX: Tx,
-        RX: Rx,
-        P: SpiPeripheral,
+        C: ChannelTypes,
+        C::P: SpiPeripheral,
         M: DuplexMode,
     {
-        fn with_dma(self, channel: Channel<TX, RX, P>) -> SpiDma<'d, T, TX, RX, P, M>;
+        fn with_dma(self, channel: Channel<'d, C>) -> SpiDma<'d, T, C, M>;
     }
 
-    impl<'d, T, RX, TX, P, M> WithDmaSpi2<'d, T, RX, TX, P, M> for Spi<'d, T, M>
+    impl<'d, T, C, M> WithDmaSpi2<'d, T, C, M> for Spi<'d, T, M>
     where
         T: Instance + Spi2Instance,
-        TX: Tx,
-        RX: Rx,
-        P: SpiPeripheral + Spi2Peripheral,
+        C: ChannelTypes,
+        C::P: SpiPeripheral + Spi2Peripheral,
         M: DuplexMode,
     {
-        fn with_dma(self, mut channel: Channel<TX, RX, P>) -> SpiDma<'d, T, TX, RX, P, M> {
+        fn with_dma(self, mut channel: Channel<'d, C>) -> SpiDma<'d, T, C, M> {
             channel.tx.init_channel(); // no need to call this for both, TX and RX
 
             SpiDma {
@@ -800,51 +806,47 @@ pub mod dma {
     }
 
     #[cfg(any(esp32, esp32s2, esp32s3))]
-    impl<'d, T, RX, TX, P, M> WithDmaSpi3<'d, T, RX, TX, P, M> for Spi<'d, T, M>
+    impl<'d, T, C, M> WithDmaSpi3<'d, T, C, M> for Spi<'d, T, M>
     where
         T: Instance + Spi3Instance,
-        TX: Tx,
-        RX: Rx,
-        P: SpiPeripheral + Spi3Peripheral,
+        C: ChannelTypes,
+        C::P: SpiPeripheral + Spi3Peripheral,
         M: DuplexMode,
     {
-        fn with_dma(self, mut channel: Channel<TX, RX, P>) -> SpiDma<'d, T, TX, RX, P, M> {
+        fn with_dma(self, mut channel: Channel<'d, C>) -> SpiDma<'d, T, C, M> {
             channel.tx.init_channel(); // no need to call this for both, TX and RX
 
             SpiDma {
                 spi: self.spi,
                 channel,
-                _mode: PhantomData::default(),
+                _mode: PhantomData,
             }
         }
     }
     /// An in-progress DMA transfer
-    pub struct SpiDmaTransferRxTx<'d, T, TX, RX, P, RBUFFER, TBUFFER, M>
+    pub struct SpiDmaTransferRxTx<'d, T, C, RBUFFER, TBUFFER, M>
     where
-        T: InstanceDma<TX, RX>,
-        TX: Tx,
-        RX: Rx,
-        P: SpiPeripheral,
+        T: InstanceDma<C::Tx<'d>, C::Rx<'d>>,
+        C: ChannelTypes,
+        C::P: SpiPeripheral,
         M: DuplexMode,
     {
-        spi_dma: SpiDma<'d, T, TX, RX, P, M>,
+        spi_dma: SpiDma<'d, T, C, M>,
         rbuffer: RBUFFER,
         tbuffer: TBUFFER,
     }
 
-    impl<'d, T, TX, RX, P, RXBUF, TXBUF, M>
-        DmaTransferRxTx<RXBUF, TXBUF, SpiDma<'d, T, TX, RX, P, M>>
-        for SpiDmaTransferRxTx<'d, T, TX, RX, P, RXBUF, TXBUF, M>
+    impl<'d, T, C, RXBUF, TXBUF, M> DmaTransferRxTx<RXBUF, TXBUF, SpiDma<'d, T, C, M>>
+        for SpiDmaTransferRxTx<'d, T, C, RXBUF, TXBUF, M>
     where
-        T: InstanceDma<TX, RX>,
-        TX: Tx,
-        RX: Rx,
-        P: SpiPeripheral,
+        T: InstanceDma<C::Tx<'d>, C::Rx<'d>>,
+        C: ChannelTypes,
+        C::P: SpiPeripheral,
         M: DuplexMode,
     {
         /// Wait for the DMA transfer to complete and return the buffers and the
         /// SPI instance.
-        fn wait(mut self) -> (RXBUF, TXBUF, SpiDma<'d, T, TX, RX, P, M>) {
+        fn wait(mut self) -> (RXBUF, TXBUF, SpiDma<'d, T, C, M>) {
             self.spi_dma.spi.flush().ok(); // waiting for the DMA transfer is not enough
 
             // `DmaTransfer` needs to have a `Drop` implementation, because we accept
@@ -870,13 +872,11 @@ pub mod dma {
         }
     }
 
-    impl<'d, T, TX, RX, P, RXBUF, TXBUF, M> Drop
-        for SpiDmaTransferRxTx<'d, T, TX, RX, P, RXBUF, TXBUF, M>
+    impl<'d, T, C, RXBUF, TXBUF, M> Drop for SpiDmaTransferRxTx<'d, T, C, RXBUF, TXBUF, M>
     where
-        T: InstanceDma<TX, RX>,
-        TX: Tx,
-        RX: Rx,
-        P: SpiPeripheral,
+        T: InstanceDma<C::Tx<'d>, C::Rx<'d>>,
+        C: ChannelTypes,
+        C::P: SpiPeripheral,
         M: DuplexMode,
     {
         fn drop(&mut self) {
@@ -885,30 +885,28 @@ pub mod dma {
     }
 
     /// An in-progress DMA transfer.
-    pub struct SpiDmaTransfer<'d, T, TX, RX, P, BUFFER, M>
+    pub struct SpiDmaTransfer<'d, T, C, BUFFER, M>
     where
-        T: InstanceDma<TX, RX>,
-        TX: Tx,
-        RX: Rx,
-        P: SpiPeripheral,
+        T: InstanceDma<C::Tx<'d>, C::Rx<'d>>,
+        C: ChannelTypes,
+        C::P: SpiPeripheral,
         M: DuplexMode,
     {
-        spi_dma: SpiDma<'d, T, TX, RX, P, M>,
+        spi_dma: SpiDma<'d, T, C, M>,
         buffer: BUFFER,
     }
 
-    impl<'d, T, TX, RX, P, BUFFER, M> DmaTransfer<BUFFER, SpiDma<'d, T, TX, RX, P, M>>
-        for SpiDmaTransfer<'d, T, TX, RX, P, BUFFER, M>
+    impl<'d, T, C, BUFFER, M> DmaTransfer<BUFFER, SpiDma<'d, T, C, M>>
+        for SpiDmaTransfer<'d, T, C, BUFFER, M>
     where
-        T: InstanceDma<TX, RX>,
-        TX: Tx,
-        RX: Rx,
-        P: SpiPeripheral,
+        T: InstanceDma<C::Tx<'d>, C::Rx<'d>>,
+        C: ChannelTypes,
+        C::P: SpiPeripheral,
         M: DuplexMode,
     {
         /// Wait for the DMA transfer to complete and return the buffers and the
         /// SPI instance.
-        fn wait(mut self) -> (BUFFER, SpiDma<'d, T, TX, RX, P, M>) {
+        fn wait(mut self) -> (BUFFER, SpiDma<'d, T, C, M>) {
             self.spi_dma.spi.flush().ok(); // waiting for the DMA transfer is not enough
 
             // `DmaTransfer` needs to have a `Drop` implementation, because we accept
@@ -933,12 +931,11 @@ pub mod dma {
         }
     }
 
-    impl<'d, T, TX, RX, P, BUFFER, M> Drop for SpiDmaTransfer<'d, T, TX, RX, P, BUFFER, M>
+    impl<'d, T, C, BUFFER, M> Drop for SpiDmaTransfer<'d, T, C, BUFFER, M>
     where
-        T: InstanceDma<TX, RX>,
-        TX: Tx,
-        RX: Rx,
-        P: SpiPeripheral,
+        T: InstanceDma<C::Tx<'d>, C::Rx<'d>>,
+        C: ChannelTypes,
+        C::P: SpiPeripheral,
         M: DuplexMode,
     {
         fn drop(&mut self) {
@@ -947,24 +944,22 @@ pub mod dma {
     }
 
     /// A DMA capable SPI instance.
-    pub struct SpiDma<'d, T, TX, RX, P, M>
+    pub struct SpiDma<'d, T, C, M>
     where
-        TX: Tx,
-        RX: Rx,
-        P: SpiPeripheral,
+        C: ChannelTypes,
+        C::P: SpiPeripheral,
         M: DuplexMode,
     {
         pub(crate) spi: PeripheralRef<'d, T>,
-        pub(crate) channel: Channel<TX, RX, P>,
+        pub(crate) channel: Channel<'d, C>,
         _mode: PhantomData<M>,
     }
 
-    impl<'d, T, TX, RX, P, M> SpiDma<'d, T, TX, RX, P, M>
+    impl<'d, T, C, M> SpiDma<'d, T, C, M>
     where
-        T: InstanceDma<TX, RX>,
-        TX: Tx,
-        RX: Rx,
-        P: SpiPeripheral,
+        T: InstanceDma<C::Tx<'d>, C::Rx<'d>>,
+        C: ChannelTypes,
+        C::P: SpiPeripheral,
         M: DuplexMode,
     {
         pub fn change_bus_frequency(&mut self, frequency: HertzU32, clocks: &Clocks) {
@@ -972,12 +967,11 @@ pub mod dma {
         }
     }
 
-    impl<'d, T, TX, RX, P, M> SpiDma<'d, T, TX, RX, P, M>
+    impl<'d, T, C, M> SpiDma<'d, T, C, M>
     where
-        T: InstanceDma<TX, RX>,
-        TX: Tx,
-        RX: Rx,
-        P: SpiPeripheral,
+        T: InstanceDma<C::Tx<'d>, C::Rx<'d>>,
+        C: ChannelTypes,
+        C::P: SpiPeripheral,
         M: IsFullDuplex,
     {
         /// Perform a DMA write.
@@ -988,7 +982,7 @@ pub mod dma {
         pub fn dma_write<TXBUF>(
             mut self,
             words: TXBUF,
-        ) -> Result<SpiDmaTransfer<'d, T, TX, RX, P, TXBUF, M>, super::Error>
+        ) -> Result<SpiDmaTransfer<'d, T, C, TXBUF, M>, super::Error>
         where
             TXBUF: ReadBuffer<Word = u8>,
         {
@@ -1014,7 +1008,7 @@ pub mod dma {
         pub fn dma_read<RXBUF>(
             mut self,
             mut words: RXBUF,
-        ) -> Result<SpiDmaTransfer<'d, T, TX, RX, P, RXBUF, M>, super::Error>
+        ) -> Result<SpiDmaTransfer<'d, T, C, RXBUF, M>, super::Error>
         where
             RXBUF: WriteBuffer<Word = u8>,
         {
@@ -1041,7 +1035,7 @@ pub mod dma {
             mut self,
             words: TXBUF,
             mut read_buffer: RXBUF,
-        ) -> Result<SpiDmaTransferRxTx<'d, T, TX, RX, P, RXBUF, TXBUF, M>, super::Error>
+        ) -> Result<SpiDmaTransferRxTx<'d, T, C, RXBUF, TXBUF, M>, super::Error>
         where
             TXBUF: ReadBuffer<Word = u8>,
             RXBUF: WriteBuffer<Word = u8>,
@@ -1069,12 +1063,11 @@ pub mod dma {
         }
     }
 
-    impl<'d, T, TX, RX, P, M> SpiDma<'d, T, TX, RX, P, M>
+    impl<'d, T, C, M> SpiDma<'d, T, C, M>
     where
-        T: InstanceDma<TX, RX>,
-        TX: Tx,
-        RX: Rx,
-        P: SpiPeripheral,
+        T: InstanceDma<C::Tx<'d>, C::Rx<'d>>,
+        C: ChannelTypes,
+        C::P: SpiPeripheral,
         M: IsHalfDuplex,
     {
         pub fn read<RXBUF>(
@@ -1084,7 +1077,7 @@ pub mod dma {
             address: Address,
             dummy: u8,
             mut buffer: RXBUF,
-        ) -> Result<SpiDmaTransfer<'d, T, TX, RX, P, RXBUF, M>, super::Error>
+        ) -> Result<SpiDmaTransfer<'d, T, C, RXBUF, M>, super::Error>
         where
             RXBUF: WriteBuffer<Word = u8>,
         {
@@ -1157,7 +1150,7 @@ pub mod dma {
             address: Address,
             dummy: u8,
             buffer: TXBUF,
-        ) -> Result<SpiDmaTransfer<'d, T, TX, RX, P, TXBUF, M>, super::Error>
+        ) -> Result<SpiDmaTransfer<'d, T, C, TXBUF, M>, super::Error>
         where
             TXBUF: ReadBuffer<Word = u8>,
         {
@@ -1224,12 +1217,11 @@ pub mod dma {
         }
     }
 
-    impl<'d, T, TX, RX, P, M> embedded_hal::blocking::spi::Transfer<u8> for SpiDma<'d, T, TX, RX, P, M>
+    impl<'d, T, C, M> embedded_hal::blocking::spi::Transfer<u8> for SpiDma<'d, T, C, M>
     where
-        T: InstanceDma<TX, RX>,
-        TX: Tx,
-        RX: Rx,
-        P: SpiPeripheral,
+        T: InstanceDma<C::Tx<'d>, C::Rx<'d>>,
+        C: ChannelTypes,
+        C::P: SpiPeripheral,
         M: IsFullDuplex,
     {
         type Error = super::Error;
@@ -1240,12 +1232,11 @@ pub mod dma {
         }
     }
 
-    impl<'d, T, TX, RX, P, M> embedded_hal::blocking::spi::Write<u8> for SpiDma<'d, T, TX, RX, P, M>
+    impl<'d, T, C, M> embedded_hal::blocking::spi::Write<u8> for SpiDma<'d, T, C, M>
     where
-        T: InstanceDma<TX, RX>,
-        TX: Tx,
-        RX: Rx,
-        P: SpiPeripheral,
+        T: InstanceDma<C::Tx<'d>, C::Rx<'d>>,
+        C: ChannelTypes,
+        C::P: SpiPeripheral,
         M: IsFullDuplex,
     {
         type Error = super::Error;
@@ -1261,12 +1252,11 @@ pub mod dma {
     mod asynch {
         use super::*;
 
-        impl<'d, T, TX, RX, P, M> embedded_hal_async::spi::SpiBusWrite for SpiDma<'d, T, TX, RX, P, M>
+        impl<'d, T, C, M> embedded_hal_async::spi::SpiBusWrite for SpiDma<'d, T, C, M>
         where
-            T: InstanceDma<TX, RX>,
-            TX: Tx,
-            RX: Rx,
-            P: SpiPeripheral,
+            T: InstanceDma<C::Tx<'d>, C::Rx<'d>>,
+            C: ChannelTypes,
+            C::P: SpiPeripheral,
             M: IsFullDuplex,
         {
             async fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
@@ -1288,12 +1278,11 @@ pub mod dma {
             }
         }
 
-        impl<'d, T, TX, RX, P, M> embedded_hal_async::spi::SpiBusFlush for SpiDma<'d, T, TX, RX, P, M>
+        impl<'d, T, C, M> embedded_hal_async::spi::SpiBusFlush for SpiDma<'d, T, C, M>
         where
-            T: InstanceDma<TX, RX>,
-            TX: Tx,
-            RX: Rx,
-            P: SpiPeripheral,
+            T: InstanceDma<C::Tx<'d>, C::Rx<'d>>,
+            C: ChannelTypes,
+            C::P: SpiPeripheral,
             M: IsFullDuplex,
         {
             async fn flush(&mut self) -> Result<(), Self::Error> {
@@ -1302,12 +1291,11 @@ pub mod dma {
             }
         }
 
-        impl<'d, T, TX, RX, P, M> embedded_hal_async::spi::SpiBusRead for SpiDma<'d, T, TX, RX, P, M>
+        impl<'d, T, C, M> embedded_hal_async::spi::SpiBusRead for SpiDma<'d, T, C, M>
         where
-            T: InstanceDma<TX, RX>,
-            TX: Tx,
-            RX: Rx,
-            P: SpiPeripheral,
+            T: InstanceDma<C::Tx<'d>, C::Rx<'d>>,
+            C: ChannelTypes,
+            C::P: SpiPeripheral,
             M: IsFullDuplex,
         {
             async fn read(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
@@ -1323,12 +1311,11 @@ pub mod dma {
             }
         }
 
-        impl<'d, T, TX, RX, P, M> embedded_hal_async::spi::SpiBus for SpiDma<'d, T, TX, RX, P, M>
+        impl<'d, T, C, M> embedded_hal_async::spi::SpiBus for SpiDma<'d, T, C, M>
         where
-            T: InstanceDma<TX, RX>,
-            TX: Tx,
-            RX: Rx,
-            P: SpiPeripheral,
+            T: InstanceDma<C::Tx<'d>, C::Rx<'d>>,
+            C: ChannelTypes,
+            C::P: SpiPeripheral,
             M: IsFullDuplex,
         {
             async fn transfer<'a>(
@@ -1407,28 +1394,23 @@ pub mod dma {
         use embedded_hal_1::spi::{SpiBus, SpiBusFlush, SpiBusRead, SpiBusWrite};
 
         use super::{super::InstanceDma, SpiDma, SpiPeripheral};
-        use crate::{
-            dma::{Rx, Tx},
-            spi::IsFullDuplex,
-        };
+        use crate::{dma::ChannelTypes, spi::IsFullDuplex};
 
-        impl<'d, T, TX, RX, P, M> embedded_hal_1::spi::ErrorType for SpiDma<'d, T, TX, RX, P, M>
+        impl<'d, T, C, M> embedded_hal_1::spi::ErrorType for SpiDma<'d, T, C, M>
         where
-            T: InstanceDma<TX, RX>,
-            TX: Tx,
-            RX: Rx,
-            P: SpiPeripheral,
+            T: InstanceDma<C::Tx<'d>, C::Rx<'d>>,
+            C: ChannelTypes,
+            C::P: SpiPeripheral,
             M: IsFullDuplex,
         {
             type Error = super::super::Error;
         }
 
-        impl<'d, T, TX, RX, P, M> SpiBusWrite for SpiDma<'d, T, TX, RX, P, M>
+        impl<'d, T, C, M> SpiBusWrite for SpiDma<'d, T, C, M>
         where
-            T: InstanceDma<TX, RX>,
-            TX: Tx,
-            RX: Rx,
-            P: SpiPeripheral,
+            T: InstanceDma<C::Tx<'d>, C::Rx<'d>>,
+            C: ChannelTypes,
+            C::P: SpiPeripheral,
             M: IsFullDuplex,
         {
             /// See also: [`write_bytes`].
@@ -1438,12 +1420,11 @@ pub mod dma {
             }
         }
 
-        impl<'d, T, TX, RX, P, M> SpiBusRead for SpiDma<'d, T, TX, RX, P, M>
+        impl<'d, T, C, M> SpiBusRead for SpiDma<'d, T, C, M>
         where
-            T: InstanceDma<TX, RX>,
-            TX: Tx,
-            RX: Rx,
-            P: SpiPeripheral,
+            T: InstanceDma<C::Tx<'d>, C::Rx<'d>>,
+            C: ChannelTypes,
+            C::P: SpiPeripheral,
             M: IsFullDuplex,
         {
             fn read(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
@@ -1453,12 +1434,11 @@ pub mod dma {
             }
         }
 
-        impl<'d, T, TX, RX, P, M> SpiBus for SpiDma<'d, T, TX, RX, P, M>
+        impl<'d, T, C, M> SpiBus for SpiDma<'d, T, C, M>
         where
-            T: InstanceDma<TX, RX>,
-            TX: Tx,
-            RX: Rx,
-            P: SpiPeripheral,
+            T: InstanceDma<C::Tx<'d>, C::Rx<'d>>,
+            C: ChannelTypes,
+            C::P: SpiPeripheral,
             M: IsFullDuplex,
         {
             /// Write out data from `write`, read response into `read`.
@@ -1491,12 +1471,11 @@ pub mod dma {
             }
         }
 
-        impl<'d, T, TX, RX, P, M> SpiBusFlush for SpiDma<'d, T, TX, RX, P, M>
+        impl<'d, T, C, M> SpiBusFlush for SpiDma<'d, T, C, M>
         where
-            T: InstanceDma<TX, RX>,
-            TX: Tx,
-            RX: Rx,
-            P: SpiPeripheral,
+            T: InstanceDma<C::Tx<'d>, C::Rx<'d>>,
+            C: ChannelTypes,
+            C::P: SpiPeripheral,
             M: IsFullDuplex,
         {
             fn flush(&mut self) -> Result<(), Self::Error> {
diff --git a/esp32-hal/examples/embassy_spi.rs b/esp32-hal/examples/embassy_spi.rs
index 7182efa0fb9..2c5561e4c0e 100644
--- a/esp32-hal/examples/embassy_spi.rs
+++ b/esp32-hal/examples/embassy_spi.rs
@@ -44,14 +44,7 @@ macro_rules! singleton {
     }};
 }
 
-pub type SpiType<'d> = SpiDma<
-    'd,
-    esp32_hal::peripherals::SPI2,
-    ChannelTx<'d, Spi2DmaChannelTxImpl, Spi2DmaChannel>,
-    ChannelRx<'d, Spi2DmaChannelRxImpl, Spi2DmaChannel>,
-    Spi2DmaSuitablePeripheral,
-    FullDuplexMode,
->;
+pub type SpiType<'d> = SpiDma<'d, esp32_hal::peripherals::SPI2, Spi2DmaChannel, FullDuplexMode>;
 
 #[embassy_executor::task]
 async fn spi_task(spi: &'static mut SpiType<'static>) {
diff --git a/esp32c2-hal/examples/embassy_spi.rs b/esp32c2-hal/examples/embassy_spi.rs
index 0ab270f84c6..7f764fae23e 100644
--- a/esp32c2-hal/examples/embassy_spi.rs
+++ b/esp32c2-hal/examples/embassy_spi.rs
@@ -44,14 +44,8 @@ macro_rules! singleton {
     }};
 }
 
-pub type SpiType<'d> = SpiDma<
-    'd,
-    esp32c2_hal::peripherals::SPI2,
-    ChannelTx<'d, Channel0TxImpl, esp32c2_hal::gdma::Channel0>,
-    ChannelRx<'d, Channel0RxImpl, esp32c2_hal::gdma::Channel0>,
-    SuitablePeripheral0,
-    FullDuplexMode,
->;
+pub type SpiType<'d> =
+    SpiDma<'d, esp32c2_hal::peripherals::SPI2, esp32c2_hal::gdma::Channel0, FullDuplexMode>;
 
 #[embassy_executor::task]
 async fn spi_task(spi: &'static mut SpiType<'static>) {
diff --git a/esp32c3-hal/examples/embassy_spi.rs b/esp32c3-hal/examples/embassy_spi.rs
index 867a6a10470..ab458d17d08 100644
--- a/esp32c3-hal/examples/embassy_spi.rs
+++ b/esp32c3-hal/examples/embassy_spi.rs
@@ -44,14 +44,8 @@ macro_rules! singleton {
     }};
 }
 
-pub type SpiType<'d> = SpiDma<
-    'd,
-    esp32c3_hal::peripherals::SPI2,
-    ChannelTx<'d, Channel0TxImpl, esp32c3_hal::gdma::Channel0>,
-    ChannelRx<'d, Channel0RxImpl, esp32c3_hal::gdma::Channel0>,
-    SuitablePeripheral0,
-    FullDuplexMode,
->;
+pub type SpiType<'d> =
+    SpiDma<'d, esp32c3_hal::peripherals::SPI2, esp32c3_hal::gdma::Channel0, FullDuplexMode>;
 
 #[embassy_executor::task]
 async fn spi_task(spi: &'static mut SpiType<'static>) {
diff --git a/esp32c6-hal/examples/embassy_spi.rs b/esp32c6-hal/examples/embassy_spi.rs
index a295083e77f..cd20adb72c1 100644
--- a/esp32c6-hal/examples/embassy_spi.rs
+++ b/esp32c6-hal/examples/embassy_spi.rs
@@ -44,14 +44,8 @@ macro_rules! singleton {
     }};
 }
 
-pub type SpiType<'d> = SpiDma<
-    'd,
-    esp32c6_hal::peripherals::SPI2,
-    ChannelTx<'d, Channel0TxImpl, esp32c6_hal::gdma::Channel0>,
-    ChannelRx<'d, Channel0RxImpl, esp32c6_hal::gdma::Channel0>,
-    SuitablePeripheral0,
-    FullDuplexMode,
->;
+pub type SpiType<'d> =
+    SpiDma<'d, esp32c6_hal::peripherals::SPI2, esp32c6_hal::gdma::Channel0, FullDuplexMode>;
 
 #[embassy_executor::task]
 async fn spi_task(spi: &'static mut SpiType<'static>) {
diff --git a/esp32h2-hal/examples/embassy_spi.rs b/esp32h2-hal/examples/embassy_spi.rs
index b6a8dc46dba..ddf9ff18bd8 100644
--- a/esp32h2-hal/examples/embassy_spi.rs
+++ b/esp32h2-hal/examples/embassy_spi.rs
@@ -44,14 +44,8 @@ macro_rules! singleton {
     }};
 }
 
-pub type SpiType<'d> = SpiDma<
-    'd,
-    esp32h2_hal::peripherals::SPI2,
-    ChannelTx<'d, Channel0TxImpl, esp32h2_hal::gdma::Channel0>,
-    ChannelRx<'d, Channel0RxImpl, esp32h2_hal::gdma::Channel0>,
-    SuitablePeripheral0,
-    FullDuplexMode,
->;
+pub type SpiType<'d> =
+    SpiDma<'d, esp32h2_hal::peripherals::SPI2, esp32h2_hal::gdma::Channel0, FullDuplexMode>;
 
 #[embassy_executor::task]
 async fn spi_task(spi: &'static mut SpiType<'static>) {
diff --git a/esp32s2-hal/examples/embassy_spi.rs b/esp32s2-hal/examples/embassy_spi.rs
index 9956616ecc1..efff8fadb41 100644
--- a/esp32s2-hal/examples/embassy_spi.rs
+++ b/esp32s2-hal/examples/embassy_spi.rs
@@ -44,14 +44,7 @@ macro_rules! singleton {
     }};
 }
 
-pub type SpiType<'d> = SpiDma<
-    'd,
-    esp32s2_hal::peripherals::SPI2,
-    ChannelTx<'d, Spi2DmaChannelTxImpl, Spi2DmaChannel>,
-    ChannelRx<'d, Spi2DmaChannelRxImpl, Spi2DmaChannel>,
-    Spi2DmaSuitablePeripheral,
-    FullDuplexMode,
->;
+pub type SpiType<'d> = SpiDma<'d, esp32s2_hal::peripherals::SPI2, Spi2DmaChannel, FullDuplexMode>;
 
 #[embassy_executor::task]
 async fn spi_task(spi: &'static mut SpiType<'static>) {
diff --git a/esp32s3-hal/examples/embassy_spi.rs b/esp32s3-hal/examples/embassy_spi.rs
index ee354b11877..3f4269478d9 100644
--- a/esp32s3-hal/examples/embassy_spi.rs
+++ b/esp32s3-hal/examples/embassy_spi.rs
@@ -44,14 +44,9 @@ macro_rules! singleton {
     }};
 }
 
-pub type SpiType<'d> = SpiDma<
-    'd,
-    esp32s3_hal::peripherals::SPI2,
-    ChannelTx<'d, Channel0TxImpl, esp32s3_hal::gdma::Channel0>,
-    ChannelRx<'d, Channel0RxImpl, esp32s3_hal::gdma::Channel0>,
-    SuitablePeripheral0,
-    FullDuplexMode,
->;
+// This example uses SPI3 to test that WithDmaSpi3 is included in the prelude.
+pub type SpiType<'d> =
+    SpiDma<'d, esp32s3_hal::peripherals::SPI3, esp32s3_hal::gdma::Channel0, FullDuplexMode>;
 
 #[embassy_executor::task]
 async fn spi_task(spi: &'static mut SpiType<'static>) {
@@ -129,7 +124,7 @@ fn main() -> ! {
     let rx_descriptors = singleton!([0u32; 8 * 3]);
 
     let spi = singleton!(Spi::new(
-        peripherals.SPI2,
+        peripherals.SPI3,
         sclk,
         mosi,
         miso,
diff --git a/esp32s3-hal/examples/i2s_read.rs b/esp32s3-hal/examples/i2s_read.rs
index c806ff053eb..8af3935b567 100644
--- a/esp32s3-hal/examples/i2s_read.rs
+++ b/esp32s3-hal/examples/i2s_read.rs
@@ -17,15 +17,17 @@
 use esp32s3_hal::{
     clock::ClockControl,
     dma::DmaPriority,
-    gdma::Gdma,
+    gdma::{Channel0, Gdma},
+    gpio::Unknown,
     i2s::{DataFormat, I2s, I2s0New, I2sReadDma, MclkPin, PinsBclkWsDin, Standard},
-    peripherals::Peripherals,
+    peripherals::{Peripherals, I2S0},
     prelude::*,
     timer::TimerGroup,
     Rtc,
     IO,
 };
 use esp_backtrace as _;
+use esp_hal_common::gpio::GpioPin;
 use esp_println::println;
 
 #[entry]
@@ -62,7 +64,11 @@ fn main() -> ! {
     let mut tx_descriptors = [0u32; 8 * 3];
     let mut rx_descriptors = [0u32; 8 * 3];
 
-    let i2s = I2s::new(
+    // Here we test that the type is
+    // 1) reasonably simple (or at least this will flag changes that may make it
+    // more complex)
+    // 2) can be spelled out by the user
+    let i2s: I2s<'_, I2S0, MclkPin<'_, GpioPin<Unknown, 4>>, Channel0> = I2s::new(
         peripherals.I2S0,
         MclkPin::new(io.pins.gpio4),
         Standard::Philips,
diff --git a/esp32s3-hal/examples/spi_loopback_dma_spi3.rs b/esp32s3-hal/examples/spi_loopback_dma_spi3.rs
deleted file mode 100644
index f998bcd3dd6..00000000000
--- a/esp32s3-hal/examples/spi_loopback_dma_spi3.rs
+++ /dev/null
@@ -1,140 +0,0 @@
-//! SPI loopback test using DMA.
-//!
-//! This example is a copy of `spi_loopback_dma.rs` with the only difference
-//! that it uses SPI3 instead of SPI2.
-//!
-//! Folowing pins are used:
-//! SCLK    GPIO6
-//! MISO    GPIO2
-//! MOSI    GPIO7
-//! CS      GPIO10
-//!
-//! Depending on your target and the board you are using you have to change the
-//! pins.
-//!
-//! This example transfers data via SPI.
-//! Connect MISO and MOSI pins to see the outgoing data is read as incoming
-//! data.
-
-#![no_std]
-#![no_main]
-
-use esp32s3_hal::{
-    clock::ClockControl,
-    dma::DmaPriority,
-    gdma::Gdma,
-    gpio::IO,
-    peripherals::Peripherals,
-    prelude::*,
-    spi::{Spi, SpiMode},
-    timer::TimerGroup,
-    Delay,
-    Rtc,
-};
-use esp_backtrace as _;
-use esp_println::println;
-
-#[entry]
-fn main() -> ! {
-    let peripherals = Peripherals::take();
-    let mut system = peripherals.SYSTEM.split();
-    let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
-
-    // Disable the watchdog timers. For the ESP32-S3, this includes the Super WDT,
-    // the RTC WDT, and the TIMG WDTs.
-    let mut rtc = Rtc::new(peripherals.RTC_CNTL);
-    let timer_group0 = TimerGroup::new(
-        peripherals.TIMG0,
-        &clocks,
-        &mut system.peripheral_clock_control,
-    );
-    let mut wdt0 = timer_group0.wdt;
-    let timer_group1 = TimerGroup::new(
-        peripherals.TIMG1,
-        &clocks,
-        &mut system.peripheral_clock_control,
-    );
-    let mut wdt1 = timer_group1.wdt;
-
-    rtc.swd.disable();
-    rtc.rwdt.disable();
-    wdt0.disable();
-    wdt1.disable();
-
-    let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
-    let sclk = io.pins.gpio6;
-    let miso = io.pins.gpio2;
-    let mosi = io.pins.gpio7;
-    let cs = io.pins.gpio10;
-
-    let dma = Gdma::new(peripherals.DMA, &mut system.peripheral_clock_control);
-    let dma_channel = dma.channel0;
-
-    let mut descriptors = [0u32; 8 * 3];
-    let mut rx_descriptors = [0u32; 8 * 3];
-
-    let mut spi = Spi::new(
-        peripherals.SPI3,
-        sclk,
-        mosi,
-        miso,
-        cs,
-        100u32.kHz(),
-        SpiMode::Mode0,
-        &mut system.peripheral_clock_control,
-        &clocks,
-    )
-    .with_dma(dma_channel.configure(
-        false,
-        &mut descriptors,
-        &mut rx_descriptors,
-        DmaPriority::Priority0,
-    ));
-
-    let mut delay = Delay::new(&clocks);
-
-    // DMA buffer require a static life-time
-    let mut send = buffer1();
-    let mut receive = buffer2();
-    let mut i = 0;
-
-    for (i, v) in send.iter_mut().enumerate() {
-        *v = (i % 255) as u8;
-    }
-
-    loop {
-        send[0] = i;
-        send[send.len() - 1] = i;
-        i = i.wrapping_add(1);
-
-        let transfer = spi.dma_transfer(send, receive).unwrap();
-        // here we could do something else while DMA transfer is in progress
-        let mut i = 0;
-        // Check is_done until the transfer is almost done (32000 bytes at 100kHz is
-        // 2.56 seconds), then move to wait().
-        while !transfer.is_done() && i < 10 {
-            delay.delay_ms(250u32);
-            i += 1;
-        }
-        // the buffers and spi is moved into the transfer and we can get it back via
-        // `wait`
-        (receive, send, spi) = transfer.wait();
-        println!(
-            "{:x?} .. {:x?}",
-            &receive[..10],
-            &receive[receive.len() - 10..]
-        );
-
-        delay.delay_ms(250u32);
-    }
-}
-
-fn buffer1() -> &'static mut [u8; 32000] {
-    static mut BUFFER: [u8; 32000] = [0u8; 32000];
-    unsafe { &mut BUFFER }
-}
-
-fn buffer2() -> &'static mut [u8; 32000] {
-    static mut BUFFER: [u8; 32000] = [0u8; 32000];
-    unsafe { &mut BUFFER }
-}