diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md index a03a7e2cbc5..9ae1c6af0f2 100644 --- a/.github/PULL_REQUEST_TEMPLATE.md +++ b/.github/PULL_REQUEST_TEMPLATE.md @@ -5,12 +5,10 @@ Please make sure that your submission includes the following: ### Must -- [ ] The code compiles without `errors` or `warnings`. +- [ ] All examples compile without warnings. - [ ] All examples work. -- [ ] `cargo fmt` was run. -- [ ] Your changes were added to the `CHANGELOG.md` in the proper section. - [ ] You updated existing examples or added examples (if applicable). -- [ ] Added examples are checked in CI +- [ ] Added examples are checked in CI. ### Nice to have diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 4702cf30c64..08a973c2f56 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -45,21 +45,21 @@ jobs: # Check all RISC-V targets: - name: check (esp32c3) - run: cd esp-hal-smartled/ && cargo +nightly check --features=esp32c3 + run: cd esp-hal-smartled/ && cargo +nightly check --features=esp32c3 --target=riscv32imc-unknown-none-elf - name: check (esp32c6) - run: cd esp-hal-smartled/ && cargo +nightly check --features=esp32c6 + run: cd esp-hal-smartled/ && cargo +nightly check --features=esp32c6 --target=riscv32imac-unknown-none-elf - name: check (esp32h2) - run: cd esp-hal-smartled/ && cargo +nightly check --features=esp32h2 + run: cd esp-hal-smartled/ && cargo +nightly check --features=esp32h2 --target=riscv32imac-unknown-none-elf # Check all Xtensa targets: - name: check (esp32) - run: cd esp-hal-smartled/ && cargo +esp check --features=esp32,esp32_40mhz + run: cd esp-hal-smartled/ && cargo +esp check --features=esp32,esp32_40mhz --target=xtensa-esp32-none-elf -Zbuild-std=core - name: check (esp32s2) - run: cd esp-hal-smartled/ && cargo +esp check --features=esp32s2 + run: cd esp-hal-smartled/ && cargo +esp check --features=esp32s2 --target=xtensa-esp32s2-none-elf -Zbuild-std=core - name: check (esp32s3) - run: cd esp-hal-smartled/ && cargo +esp check --features=esp32s3 + run: cd esp-hal-smartled/ && cargo +esp check --features=esp32s3 --target=xtensa-esp32s3-none-elf -Zbuild-std=core # Ensure documentation can be built (requires a chip feature!) - name: rustdoc - run: cd esp-hal-smartled/ && cargo doc --features=esp32c3 + run: cd esp-hal-smartled/ && cargo doc --features=esp32c3,esp-hal-common/eh1 --target=riscv32imc-unknown-none-elf esp32-hal: runs-on: ubuntu-latest @@ -73,6 +73,8 @@ jobs: ldproxy: false - uses: Swatinem/rust-cache@v2 + - name: check esp32-hal + run: cd esp32-hal/ && cargo check # Perform a full build initially to verify that the examples not only # build, but also link successfully. - name: build esp32-hal (no features) @@ -93,7 +95,7 @@ jobs: run: cd esp32-hal/ && cargo check --example=embassy_i2c --features=embassy,embassy-time-timg0,async # Ensure documentation can be built - name: rustdoc - run: cd esp32-hal/ && cargo doc + run: cd esp32-hal/ && cargo doc --features=eh1 esp32c2-hal: runs-on: ubuntu-latest @@ -107,6 +109,8 @@ jobs: components: rust-src - uses: Swatinem/rust-cache@v2 + - name: check esp32c62hal + run: cd esp32c2-hal/ && cargo +nightly check # Perform a full build initially to verify that the examples not only # build, but also link successfully. # We also use this as an opportunity to verify that the examples link @@ -132,10 +136,10 @@ jobs: - name: check esp32c2-hal (async, i2c) run: cd esp32c2-hal/ && cargo +nightly check --example=embassy_i2c --features=embassy,embassy-time-systick,async - name: check esp32c2-hal (interrupt-preemption) - run: cd esp32c2-hal/ && cargo check --example=interrupt_preemption --features=interrupt-preemption + run: cd esp32c2-hal/ && cargo +nightly check --example=interrupt_preemption --features=interrupt-preemption # Ensure documentation can be built - name: rustdoc - run: cd esp32c2-hal/ && cargo doc + run: cd esp32c2-hal/ && cargo doc --features=eh1 esp32c3-hal: runs-on: ubuntu-latest @@ -149,6 +153,8 @@ jobs: components: rust-src - uses: Swatinem/rust-cache@v2 + - name: check esp32c3-hal + run: cd esp32c3-hal/ && cargo +nightly check # Perform a full build initially to verify that the examples not only # build, but also link successfully. # We also use this as an opportunity to verify that the examples link @@ -176,10 +182,10 @@ jobs: - name: check esp32c3-hal (async, i2c) run: cd esp32c3-hal/ && cargo +nightly check --example=embassy_i2c --features=embassy,embassy-time-systick,async - name: check esp32c3-hal (interrupt-preemption) - run: cd esp32c3-hal/ && cargo check --example=interrupt_preemption --features=interrupt-preemption + run: cd esp32c3-hal/ && cargo +nightly check --example=interrupt_preemption --features=interrupt-preemption # Ensure documentation can be built - name: rustdoc - run: cd esp32c3-hal/ && cargo doc + run: cd esp32c3-hal/ && cargo doc --features=eh1 esp32c6-hal: runs-on: ubuntu-latest @@ -193,6 +199,8 @@ jobs: components: rust-src - uses: Swatinem/rust-cache@v2 + - name: check esp32c6-hal + run: cd esp32c6-hal/ && cargo +nightly check # Perform a full build initially to verify that the examples not only # build, but also link successfully. # We also use this as an opportunity to verify that the examples link @@ -218,10 +226,10 @@ jobs: - name: check esp32c6-hal (async, i2c) run: cd esp32c6-hal/ && cargo +nightly check --example=embassy_i2c --features=embassy,embassy-time-systick,async - name: check esp32c6-hal (interrupt-preemption) - run: cd esp32c6-hal/ && cargo check --example=interrupt_preemption --features=interrupt-preemption + run: cd esp32c6-hal/ && cargo +nightly check --example=interrupt_preemption --features=interrupt-preemption # Ensure documentation can be built - name: rustdoc - run: cd esp32c6-hal/ && cargo doc + run: cd esp32c6-hal/ && cargo doc --features=eh1 esp32h2-hal: runs-on: ubuntu-latest @@ -235,6 +243,8 @@ jobs: components: rust-src - uses: Swatinem/rust-cache@v2 + - name: check esp32h2-hal + run: cd esp32h2-hal/ && cargo +nightly check # Perform a full build initially to verify that the examples not only # build, but also link successfully. # We also use this as an opportunity to verify that the examples link @@ -260,10 +270,10 @@ jobs: - name: check esp32h2-hal (async, i2c) run: cd esp32h2-hal/ && cargo +nightly check --example=embassy_i2c --features=embassy,embassy-time-systick,async - name: check esp32h2-hal (interrupt-preemption) - run: cd esp32h2-hal/ && cargo check --example=interrupt_preemption --features=interrupt-preemption + run: cd esp32h2-hal/ && cargo +nightly check --example=interrupt_preemption --features=interrupt-preemption # Ensure documentation can be built - name: rustdoc - run: cd esp32h2-hal/ && cargo doc + run: cd esp32h2-hal/ && cargo doc --features=eh1 esp32s2-hal: runs-on: ubuntu-latest @@ -277,6 +287,8 @@ jobs: ldproxy: false - uses: Swatinem/rust-cache@v2 + - name: check esp32s2-hal + run: cd esp32s2-hal/ && cargo check # Perform a full build initially to verify that the examples not only # build, but also link successfully. - name: check esp32s2-hal (no features) @@ -300,7 +312,7 @@ jobs: run: cd esp32s2-hal/ && cargo check --example=embassy_i2c --features=embassy,embassy-time-timg0,async # Ensure documentation can be built - name: rustdoc - run: cd esp32s2-hal/ && cargo doc + run: cd esp32s2-hal/ && cargo doc --features=eh1 esp32s3-hal: runs-on: ubuntu-latest @@ -314,6 +326,8 @@ jobs: ldproxy: false - uses: Swatinem/rust-cache@v2 + - name: check esp32s3-hal + run: cd esp32s3-hal/ && cargo check # Perform a full build initially to verify that the examples not only # build, but also link successfully. # We also use this as an opportunity to verify that the examples link @@ -342,7 +356,7 @@ jobs: run: cd esp32s3-hal/ && cargo check --example=octal_psram --features=opsram_2m --release # This example requires release! # Ensure documentation can be built - name: rustdoc - run: cd esp32s3-hal/ && cargo doc + run: cd esp32s3-hal/ && cargo doc --features=eh1 esp-riscv-rt: runs-on: ubuntu-latest @@ -417,21 +431,21 @@ jobs: - uses: actions/checkout@v3 - uses: dtolnay/rust-toolchain@v1 with: - toolchain: stable - components: clippy + toolchain: nightly + components: clippy, rust-src - uses: Swatinem/rust-cache@v2 # Run clippy on all packages targeting RISC-V. - name: clippy (esp-riscv-rt) - run: cargo +stable clippy --manifest-path=esp-riscv-rt/Cargo.toml -- --no-deps + run: cd esp-riscv-rt/ && cargo +nightly clippy -- --no-deps - name: clippy (esp32c2-hal) - run: cargo +stable clippy --manifest-path=esp32c2-hal/Cargo.toml -- --no-deps + run: cd esp32c2-hal/ && cargo +nightly clippy -- --no-deps - name: clippy (esp32c3-hal) - run: cargo +stable clippy --manifest-path=esp32c3-hal/Cargo.toml -- --no-deps + run: cd esp32c3-hal/ && cargo +nightly clippy -- --no-deps - name: clippy (esp32c6-hal) - run: cargo +stable clippy --manifest-path=esp32c6-hal/Cargo.toml -- --no-deps + run: cd esp32c6-hal/ && cargo +nightly clippy -- --no-deps - name: clippy (esp32h2-hal) - run: cargo +stable clippy --manifest-path=esp32h2-hal/Cargo.toml -- --no-deps + run: cd esp32h2-hal/ && cargo +nightly clippy -- --no-deps clippy-xtensa: runs-on: ubuntu-latest @@ -448,11 +462,11 @@ jobs: # The ESP32-S2 requires some additional information in order for the # atomic emulation crate to build. - name: clippy (esp32-hal) - run: cargo +esp clippy --manifest-path=esp32-hal/Cargo.toml -- --no-deps + run: cd esp32-hal/ && cargo +esp clippy -- --no-deps - name: clippy (esp32s2-hal) - run: cargo +esp clippy --manifest-path=esp32s2-hal/Cargo.toml -- --no-deps + run: cd esp32s2-hal/ && cargo +esp clippy -- --no-deps - name: clippy (esp32s3-hal) - run: cargo +esp clippy --manifest-path=esp32s3-hal/Cargo.toml -- --no-deps + run: cd esp32s3-hal/ && cargo +esp clippy -- --no-deps rustfmt: runs-on: ubuntu-latest diff --git a/CHANGELOG.md b/CHANGELOG.md index 59e542c89d2..7e4ad425b2d 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -18,7 +18,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 ### Changed - Update `embedded-hal-*` alpha packages to their latest versions (#640) -- Implement the `Clone` and `Copy` traits for the `Rng` driver (#650) +- Implement the `Clone` and `Copy` traits for the `Rng` driver (#650, #666) ### Fixed diff --git a/esp-hal-common/build.rs b/esp-hal-common/build.rs index 5981d1d7f87..240f853575a 100644 --- a/esp-hal-common/build.rs +++ b/esp-hal-common/build.rs @@ -250,6 +250,7 @@ fn gen_efuse_table(device_name: &str, out_dir: impl AsRef) { fields.next().map(|s| s.trim()), ) { (Some(name), Some(block), Some(bit_off), Some(bit_len), Some(desc)) => { + let desc = desc.replace('[', "`[").replace(']', "]`"); writeln!(writer, "/// {desc}").unwrap(); writeln!( writer, diff --git a/esp-hal-common/src/analog/adc/cal_curve.rs b/esp-hal-common/src/analog/adc/cal_curve.rs index 1beaa542a82..9809d63e152 100644 --- a/esp-hal-common/src/analog/adc/cal_curve.rs +++ b/esp-hal-common/src/analog/adc/cal_curve.rs @@ -38,8 +38,8 @@ pub trait AdcHasCurveCal { /// This scheme implements final polynomial error correction using predefined /// coefficient sets for each attenuation. /// -/// This scheme also includes basic calibration ([`AdcCalBasic`]) and line -/// fitting ([`AdcCalLine`]). +/// This scheme also includes basic calibration ([`super::AdcCalBasic`]) and +/// line fitting ([`AdcCalLine`]). #[derive(Clone, Copy)] pub struct AdcCalCurve { line: AdcCalLine, @@ -131,7 +131,7 @@ mod impls { } coeff_tables! { - /// Error curve coefficients derived from https://github.com/espressif/esp-idf/blob/903af13e8/components/esp_adc/esp32c3/curve_fitting_coefficients.c + /// Error curve coefficients derived from #[cfg(esp32c3)] CURVES_COEFFS1 [ Attenuation0dB => [ @@ -158,7 +158,7 @@ mod impls { ], ]; - /// Error curve coefficients derived from https://github.com/espressif/esp-idf/blob/903af13e8/components/esp_adc/esp32c6/curve_fitting_coefficients.c + /// Error curve coefficients derived from #[cfg(esp32c6)] CURVES_COEFFS1 [ Attenuation0dB => [ @@ -183,7 +183,7 @@ mod impls { ], ]; - /// Error curve coefficients derived from https://github.com/espressif/esp-idf/blob/903af13e8/components/esp_adc/esp32s3/curve_fitting_coefficients.c + /// Error curve coefficients derived from #[cfg(esp32s3)] CURVES_COEFFS1 [ Attenuation0dB => [ @@ -210,7 +210,7 @@ mod impls { ], ]; - /// Error curve coefficients derived from https://github.com/espressif/esp-idf/blob/903af13e8/components/esp_adc/esp32s3/curve_fitting_coefficients.c + /// Error curve coefficients derived from #[cfg(esp32s3)] CURVES_COEFFS2 [ Attenuation0dB => [ diff --git a/esp-hal-common/src/analog/adc/xtensa.rs b/esp-hal-common/src/analog/adc/xtensa.rs index 53d67d16c4c..a24fcda7f3c 100644 --- a/esp-hal-common/src/analog/adc/xtensa.rs +++ b/esp-hal-common/src/analog/adc/xtensa.rs @@ -420,7 +420,6 @@ pub mod implementation { use embedded_hal::adc::Channel; - use super::impl_adc_interface; pub use crate::analog::{adc::*, ADC1, ADC2}; use crate::gpio::*; diff --git a/esp-hal-common/src/interrupt/riscv.rs b/esp-hal-common/src/interrupt/riscv.rs index 8584df93598..98fdacc0b55 100644 --- a/esp-hal-common/src/interrupt/riscv.rs +++ b/esp-hal-common/src/interrupt/riscv.rs @@ -510,7 +510,7 @@ pub fn _setup_interrupts() { // at least after the 2nd stage bootloader there are some interrupts enabled // (e.g. UART) for peripheral_interrupt in 0..255 { - crate::soc::peripherals::Interrupt::try_from(peripheral_interrupt) + Interrupt::try_from(peripheral_interrupt) .map(|intr| { #[cfg(multi_core)] disable(Cpu::AppCpu, intr); @@ -548,16 +548,16 @@ pub fn disable(_core: Cpu, interrupt: Interrupt) { pub fn get_status(_core: Cpu) -> u128 { #[cfg(large_intr_status)] unsafe { - ((*crate::peripherals::INTERRUPT_CORE0::PTR) + ((*peripherals::INTERRUPT_CORE0::PTR) .intr_status_reg_0 .read() .bits() as u128) - | ((*crate::peripherals::INTERRUPT_CORE0::PTR) + | ((*peripherals::INTERRUPT_CORE0::PTR) .intr_status_reg_1 .read() .bits() as u128) << 32 - | ((*crate::peripherals::INTERRUPT_CORE0::PTR) + | ((*peripherals::INTERRUPT_CORE0::PTR) .int_status_reg_2 .read() .bits() as u128) @@ -566,11 +566,11 @@ pub fn get_status(_core: Cpu) -> u128 { #[cfg(not(large_intr_status))] unsafe { - ((*crate::peripherals::INTERRUPT_CORE0::PTR) + ((*peripherals::INTERRUPT_CORE0::PTR) .intr_status_reg_0 .read() .bits() as u128) - | ((*crate::peripherals::INTERRUPT_CORE0::PTR) + | ((*peripherals::INTERRUPT_CORE0::PTR) .intr_status_reg_1 .read() .bits() as u128) @@ -593,6 +593,7 @@ pub unsafe fn map(_core: Cpu, interrupt: Interrupt, which: CpuInterrupt) { /// Get cpu interrupt assigned to peripheral interrupt #[inline] +#[cfg(feature = "vectored")] unsafe fn get_assigned_cpu_interrupt(interrupt: Interrupt) -> CpuInterrupt { let interrupt_number = interrupt as isize; let intr_map_base = crate::soc::registers::INTERRUPT_MAP_BASE as *mut u32; @@ -605,18 +606,20 @@ unsafe fn get_assigned_cpu_interrupt(interrupt: Interrupt) -> CpuInterrupt { #[cfg(not(plic))] mod classic { use super::{CpuInterrupt, InterruptKind, Priority}; - use crate::Cpu; + use crate::{peripherals, Cpu}; + #[cfg(feature = "vectored")] pub(super) const PRIORITY_TO_INTERRUPT: [usize; 15] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]; + #[cfg(feature = "vectored")] pub(super) const INTERRUPT_TO_PRIORITY: [usize; 15] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]; /// Enable a CPU interrupt pub unsafe fn enable_cpu_interrupt(which: CpuInterrupt) { let cpu_interrupt_number = which as isize; - let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR; + let intr = &*peripherals::INTERRUPT_CORE0::PTR; intr.cpu_int_enable .modify(|r, w| w.bits((1 << cpu_interrupt_number) | r.bits())); } @@ -628,7 +631,7 @@ mod classic { /// bits. pub fn set_kind(_core: Cpu, which: CpuInterrupt, kind: InterruptKind) { unsafe { - let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR; + let intr = &*peripherals::INTERRUPT_CORE0::PTR; let cpu_interrupt_number = which as isize; let interrupt_type = match kind { @@ -650,7 +653,7 @@ mod classic { /// default). Avoid changing the priority of interrupts 1 - 15 when /// interrupt vectoring is enabled. pub unsafe fn set_priority(_core: Cpu, which: CpuInterrupt, priority: Priority) { - let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR; + let intr = &*peripherals::INTERRUPT_CORE0::PTR; let cpu_interrupt_number = which as isize; let intr_prio_base = intr.cpu_int_pri_0.as_ptr(); @@ -664,7 +667,7 @@ mod classic { pub fn clear(_core: Cpu, which: CpuInterrupt) { unsafe { let cpu_interrupt_number = which as isize; - let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR; + let intr = &*peripherals::INTERRUPT_CORE0::PTR; intr.cpu_int_clear .write(|w| w.bits(1 << cpu_interrupt_number)); } @@ -672,8 +675,9 @@ mod classic { /// Get interrupt priority #[inline] + #[cfg(feature = "vectored")] pub(super) unsafe fn get_priority(cpu_interrupt: CpuInterrupt) -> Priority { - let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR; + let intr = &*peripherals::INTERRUPT_CORE0::PTR; let intr_prio_base = intr.cpu_int_pri_0.as_ptr(); let prio = intr_prio_base @@ -689,7 +693,7 @@ mod classic { use super::mcause; use crate::riscv; let interrupt_id: usize = mcause::read().code(); // MSB is whether its exception or interrupt. - let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR; + let intr = &*peripherals::INTERRUPT_CORE0::PTR; let interrupt_priority = intr .cpu_int_pri_0 .as_ptr() @@ -714,7 +718,7 @@ mod classic { unsafe { riscv::interrupt::disable(); } - let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR; + let intr = &*peripherals::INTERRUPT_CORE0::PTR; intr.cpu_int_thresh.write(|w| w.bits(stored_prio)); } } @@ -727,9 +731,11 @@ mod plic { // don't use interrupts reserved for CLIC (0,3,4,7) // for some reason also CPU interrupt 8 doesn't work by default since it's // disabled after reset - so don't use that, too + #[cfg(feature = "vectored")] pub(super) const PRIORITY_TO_INTERRUPT: [usize; 15] = [1, 2, 5, 6, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]; + #[cfg(feature = "vectored")] pub(super) const INTERRUPT_TO_PRIORITY: [usize; 19] = [ 1, 2, 0, 0, 3, 4, 0, 0, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ]; @@ -797,6 +803,7 @@ mod plic { /// Get interrupt priority #[inline] + #[cfg(feature = "vectored")] pub(super) unsafe fn get_priority(cpu_interrupt: CpuInterrupt) -> Priority { let plic_mxint_pri_ptr = PLIC_MXINT0_PRI_REG as *mut u32; diff --git a/esp-hal-common/src/interrupt/xtensa.rs b/esp-hal-common/src/interrupt/xtensa.rs index 468287c13b8..c83cd5f6276 100644 --- a/esp-hal-common/src/interrupt/xtensa.rs +++ b/esp-hal-common/src/interrupt/xtensa.rs @@ -1,4 +1,4 @@ -use xtensa_lx::interrupt::{self, InterruptNumber}; +use xtensa_lx::interrupt; use xtensa_lx_rt::exception::Context; use crate::{ @@ -93,7 +93,7 @@ pub fn disable(core: Cpu, interrupt: Interrupt) { /// Clear the given CPU interrupt pub fn clear(_core: Cpu, which: CpuInterrupt) { unsafe { - xtensa_lx::interrupt::clear(1 << which as u32); + interrupt::clear(1 << which as u32); } } @@ -161,25 +161,23 @@ pub fn get_status(core: Cpu) -> u128 { } #[cfg(esp32)] -unsafe fn core0_interrupt_peripheral() -> *const crate::peripherals::dport::RegisterBlock { - crate::peripherals::DPORT::PTR +unsafe fn core0_interrupt_peripheral() -> *const peripherals::dport::RegisterBlock { + peripherals::DPORT::PTR } #[cfg(esp32)] -unsafe fn core1_interrupt_peripheral() -> *const crate::peripherals::dport::RegisterBlock { - crate::peripherals::DPORT::PTR +unsafe fn core1_interrupt_peripheral() -> *const peripherals::dport::RegisterBlock { + peripherals::DPORT::PTR } #[cfg(any(esp32s2, esp32s3))] -unsafe fn core0_interrupt_peripheral() -> *const crate::peripherals::interrupt_core0::RegisterBlock -{ - crate::peripherals::INTERRUPT_CORE0::PTR +unsafe fn core0_interrupt_peripheral() -> *const peripherals::interrupt_core0::RegisterBlock { + peripherals::INTERRUPT_CORE0::PTR } #[cfg(esp32s3)] -unsafe fn core1_interrupt_peripheral() -> *const crate::peripherals::interrupt_core1::RegisterBlock -{ - crate::peripherals::INTERRUPT_CORE1::PTR +unsafe fn core1_interrupt_peripheral() -> *const peripherals::interrupt_core1::RegisterBlock { + peripherals::INTERRUPT_CORE1::PTR } #[cfg(feature = "vectored")] @@ -188,6 +186,7 @@ pub use vectored::*; #[cfg(feature = "vectored")] mod vectored { use procmacros::ram; + use xtensa_lx::interrupt::InterruptNumber; use super::*; use crate::get_core; @@ -298,9 +297,7 @@ mod vectored { unsafe { map(get_core(), interrupt, cpu_interrupt); - xtensa_lx::interrupt::enable_mask( - xtensa_lx::interrupt::get_mask() | 1 << cpu_interrupt as u32, - ); + interrupt::enable_mask(interrupt::get_mask() | 1 << cpu_interrupt as u32); } Ok(()) } diff --git a/esp-hal-common/src/lib.rs b/esp-hal-common/src/lib.rs index e4f3668279c..fdf8a674c0e 100644 --- a/esp-hal-common/src/lib.rs +++ b/esp-hal-common/src/lib.rs @@ -31,6 +31,7 @@ feature(impl_trait_projections) )] #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")] +#![deny(warnings)] #[cfg(riscv)] pub use esp_riscv_rt::{self, entry, riscv}; diff --git a/esp-hal-common/src/rmt.rs b/esp-hal-common/src/rmt.rs index cd1ccd4b609..d6254259a80 100644 --- a/esp-hal-common/src/rmt.rs +++ b/esp-hal-common/src/rmt.rs @@ -28,7 +28,7 @@ //! signals. //! * The **ESP32-S2** has 4 channels, each of them can be either receiver or //! transmitter. -//! * The **ESP32-S3** has 8 channels, `Channel0`-`Channel3` hardcdoded for +//! * The **ESP32-S3** has 8 channels, `Channel0`-`Channel3` hardcoded for //! transmitting signals and `Channel4`-`Channel7` hardcoded for receiving //! signals. //! @@ -103,7 +103,7 @@ pub enum Error { /// Convenience representation of a pulse code entry. /// -/// Allows for the assignment of two levels and their lenghts +/// Allows for the assignment of two levels and their lengths #[derive(Clone, Copy, Debug, Default)] pub struct PulseCode { /// Logical output level in the first pulse code interval @@ -386,21 +386,21 @@ where } } -/// An in-progress continous TX transaction -pub struct ContinousTxTransaction +/// An in-progress continuous TX transaction +pub struct ContinuousTxTransaction where C: TxChannel, { channel: C, } -impl ContinousTxTransaction +impl ContinuousTxTransaction where C: TxChannel, { /// Stop transaction when the current iteration ends. pub fn stop_next(self) -> Result { - >::set_continous(false); + >::set_continuous(false); >::update(); loop { @@ -418,7 +418,7 @@ where /// Stop transaction as soon as possible. pub fn stop(self) -> Result { - >::set_continous(false); + >::set_continuous(false); >::update(); let ptr = (constants::RMT_RAM_START @@ -791,7 +791,7 @@ pub struct Channel7 {} pub trait TxChannel: private::TxChannelInternal { /// Start transmitting the given pulse code sequence. - /// This returns a [SingleShotTxTransaction] which can be used to wait for + /// This returns a [`SingleShotTxTransaction`] which can be used to wait for /// the transaction to complete and get back the channel for further /// use. fn transmit<'a, T: Into + Copy>( @@ -809,28 +809,28 @@ pub trait TxChannel: private::TxChannelInternal { } } - /// Start transmitting the given pulse code continously. - /// This returns a [ContinousTxTransaction] which can be used to stop the + /// Start transmitting the given pulse code continuously. + /// This returns a [`ContinuousTxTransaction`] which can be used to stop the /// ongoing transmission and get back the channel for further use. /// The length of sequence cannot exceed the size of the allocated RMT RAM. - fn transmit_continously<'a, T: Into + Copy>( + fn transmit_continuously<'a, T: Into + Copy>( self, data: &'a [T], - ) -> Result, Error> + ) -> Result, Error> where Self: Sized, { - self.transmit_continously_with_loopcount(0, data) + self.transmit_continuously_with_loopcount(0, data) } - /// Like [transmit_continously] but also sets a loop count. - /// [ContinousTxTransaction] can be used to check if the loop count is + /// Like [`Self::transmit_continuously`] but also sets a loop count. + /// [`ContinuousTxTransaction`] can be used to check if the loop count is /// reached. - fn transmit_continously_with_loopcount<'a, T: Into + Copy>( + fn transmit_continuously_with_loopcount<'a, T: Into + Copy>( self, loopcount: u16, data: &'a [T], - ) -> Result, Error> + ) -> Result, Error> where Self: Sized, { @@ -839,7 +839,7 @@ pub trait TxChannel: private::TxChannelInternal { } let _index = Self::send_raw(data, true, loopcount); - Ok(ContinousTxTransaction { channel: self }) + Ok(ContinuousTxTransaction { channel: self }) } } @@ -928,7 +928,7 @@ mod private { fn clear_interrupts(); - fn set_continous(continous: bool); + fn set_continuous(continuous: bool); fn set_wrap_mode(wrap: bool); @@ -952,7 +952,7 @@ mod private { fn is_loopcount_interrupt_set() -> bool; - fn send_raw + Copy>(data: &[T], continous: bool, repeat: u16) -> usize { + fn send_raw + Copy>(data: &[T], continuous: bool, repeat: u16) -> usize { Self::clear_interrupts(); let ptr = (constants::RMT_RAM_START @@ -969,7 +969,7 @@ mod private { } Self::set_threshold((constants::RMT_CHANNEL_RAM_SIZE / 2) as u8); - Self::set_continous(continous); + Self::set_continuous(continuous); Self::set_generate_repeat_interrupt(repeat); Self::set_wrap_mode(true); Self::set_memsize(1); @@ -1130,10 +1130,10 @@ mod chip_specific { }); } - fn set_continous(continous: bool) { + fn set_continuous(continuous: bool) { let rmt = unsafe { &*crate::peripherals::RMT::PTR }; - rmt.ch_tx_conf0[$num].modify(|_, w| w.tx_conti_mode().bit(continous)); + rmt.ch_tx_conf0[$num].modify(|_, w| w.tx_conti_mode().bit(continuous)); } fn set_wrap_mode(wrap: bool) { @@ -1414,10 +1414,10 @@ mod chip_specific { }); } - fn set_continous(continous: bool) { + fn set_continuous(continuous: bool) { let rmt = unsafe { &*crate::peripherals::RMT::PTR }; - rmt.[< ch $ch_num conf1 >].modify(|_, w| w.tx_conti_mode().bit(continous)); + rmt.[< ch $ch_num conf1 >].modify(|_, w| w.tx_conti_mode().bit(continuous)); } fn set_wrap_mode(_wrap: bool) { diff --git a/esp-hal-common/src/soc/esp32c2/efuse.rs b/esp-hal-common/src/soc/esp32c2/efuse.rs index 7519566c940..8e456a47cf0 100644 --- a/esp-hal-common/src/soc/esp32c2/efuse.rs +++ b/esp-hal-common/src/soc/esp32c2/efuse.rs @@ -39,10 +39,10 @@ impl Efuse { /// Get efuse block version /// - /// see https://github.com/espressif/esp-idf/blob/dc016f5987/components/hal/efuse_hal.c#L27-L30 + /// see pub fn get_block_version() -> (u8, u8) { - // see https://github.com/espressif/esp-idf/blob/dc016f5987/components/hal/esp32c2/include/hal/efuse_ll.h#L65-L73 - // https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c2/esp_efuse_table.csv#L90-L91 + // see + // ( Self::read_field_le::(BLK_VERSION_MAJOR), Self::read_field_le::(BLK_VERSION_MINOR), @@ -51,7 +51,7 @@ impl Efuse { /// Get version of RTC calibration block /// - /// see https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c2/esp_efuse_rtc_calib.c#L14 + /// see pub fn get_rtc_calib_version() -> u8 { let (major, _minor) = Self::get_block_version(); if major == 0 { @@ -63,7 +63,7 @@ impl Efuse { /// Get ADC initial code for specified attenuation from efuse /// - /// see https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c2/esp_efuse_rtc_calib.c#L27 + /// see pub fn get_rtc_calib_init_code(_unit: u8, atten: Attenuation) -> Option { let version = Self::get_rtc_calib_version(); @@ -71,7 +71,7 @@ impl Efuse { return None; } - // see https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c2/esp_efuse_table.csv#L94 + // see let diff_code0: u16 = Self::read_field_le(ADC1_INIT_CODE_ATTEN0); let code0 = if diff_code0 & (1 << 7) != 0 { 2160 - (diff_code0 & 0x7f) @@ -83,7 +83,7 @@ impl Efuse { return Some(code0); } - // see https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c2/esp_efuse_table.csv#L95 + // see let diff_code11: u16 = Self::read_field_le(ADC1_INIT_CODE_ATTEN3); let code11 = code0 + diff_code11; @@ -92,7 +92,7 @@ impl Efuse { /// Get ADC reference point voltage for specified attenuation in millivolts /// - /// see https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c2/esp_efuse_rtc_calib.c#L65 + /// see pub fn get_rtc_calib_cal_mv(_unit: u8, atten: Attenuation) -> u16 { match atten { Attenuation::Attenuation0dB => 400, @@ -102,7 +102,7 @@ impl Efuse { /// Get ADC reference point digital code for specified attenuation /// - /// see https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c2/esp_efuse_rtc_calib.c#L65 + /// see pub fn get_rtc_calib_cal_code(_unit: u8, atten: Attenuation) -> Option { let version = Self::get_rtc_calib_version(); @@ -110,7 +110,7 @@ impl Efuse { return None; } - // see https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c2/esp_efuse_table.csv#L96 + // see let diff_code0: u16 = Self::read_field_le(ADC1_CAL_VOL_ATTEN0); let code0 = if diff_code0 & (1 << 7) != 0 { 1540 - (diff_code0 & 0x7f) @@ -122,7 +122,7 @@ impl Efuse { return Some(code0); } - // see https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c2/esp_efuse_table.csv#L97 + // see let diff_code11: u16 = Self::read_field_le(ADC1_CAL_VOL_ATTEN3); let code11 = if diff_code0 & (1 << 5) != 0 { code0 - (diff_code11 & 0x1f) diff --git a/esp-hal-common/src/soc/esp32c3/efuse.rs b/esp-hal-common/src/soc/esp32c3/efuse.rs index 25a4b61f98a..5fd1501202b 100644 --- a/esp-hal-common/src/soc/esp32c3/efuse.rs +++ b/esp-hal-common/src/soc/esp32c3/efuse.rs @@ -39,11 +39,11 @@ impl Efuse { /// Get efuse block version /// - /// see https://github.com/espressif/esp-idf/blob/dc016f5987/components/hal/efuse_hal.c#L27-L30 + /// see pub fn get_block_version() -> (u8, u8) { - // see https://github.com/espressif/esp-idf/blob/dc016f5987/components/hal/esp32c3/include/hal/efuse_ll.h#L70-L78 - // https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c3/esp_efuse_table.csv#L163 - // https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c3/esp_efuse_table.csv#L173 + // see + // + // ( Self::read_field_le::(BLK_VERSION_MAJOR), Self::read_field_le::(BLK_VERSION_MINOR), @@ -52,7 +52,7 @@ impl Efuse { /// Get version of RTC calibration block /// - /// see https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c3/esp_efuse_rtc_calib.c#L12 + /// see pub fn get_rtc_calib_version() -> u8 { let (major, _minor) = Self::get_block_version(); if major == 1 { @@ -64,7 +64,7 @@ impl Efuse { /// Get ADC initial code for specified attenuation from efuse /// - /// see https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c3/esp_efuse_rtc_calib.c#L25 + /// see pub fn get_rtc_calib_init_code(_unit: u8, atten: Attenuation) -> Option { let version = Self::get_rtc_calib_version(); @@ -72,7 +72,7 @@ impl Efuse { return None; } - // See https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c3/esp_efuse_table.csv#L176-L179 + // See let init_code: u16 = Self::read_field_le(match atten { Attenuation::Attenuation0dB => ADC1_INIT_CODE_ATTEN0, Attenuation::Attenuation2p5dB => ADC1_INIT_CODE_ATTEN1, @@ -85,7 +85,7 @@ impl Efuse { /// Get ADC reference point voltage for specified attenuation in millivolts /// - /// see https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c3/esp_efuse_rtc_calib.c#L49 + /// see pub fn get_rtc_calib_cal_mv(_unit: u8, atten: Attenuation) -> u16 { match atten { Attenuation::Attenuation0dB => 400, @@ -97,7 +97,7 @@ impl Efuse { /// Get ADC reference point digital code for specified attenuation /// - /// see https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c3/esp_efuse_rtc_calib.c#L49 + /// see pub fn get_rtc_calib_cal_code(_unit: u8, atten: Attenuation) -> Option { let version = Self::get_rtc_calib_version(); @@ -105,7 +105,7 @@ impl Efuse { return None; } - // See https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c3/esp_efuse_table.csv#L180-L183 + // See let cal_code: u16 = Self::read_field_le(match atten { Attenuation::Attenuation0dB => ADC1_CAL_VOL_ATTEN0, Attenuation::Attenuation2p5dB => ADC1_CAL_VOL_ATTEN1, diff --git a/esp-hal-common/src/soc/esp32c6/efuse.rs b/esp-hal-common/src/soc/esp32c6/efuse.rs index bb502c822b5..4f22dc9f9ae 100644 --- a/esp-hal-common/src/soc/esp32c6/efuse.rs +++ b/esp-hal-common/src/soc/esp32c6/efuse.rs @@ -39,10 +39,10 @@ impl Efuse { /// Get efuse block version /// - /// see https://github.com/espressif/esp-idf/blob/dc016f5987/components/hal/efuse_hal.c#L27-L30 + /// see pub fn get_block_version() -> (u8, u8) { - // see https://github.com/espressif/esp-idf/blob/dc016f5987/components/hal/esp32c6/include/hal/efuse_ll.h#L65-L73 - // https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c6/esp_efuse_table.csv#L156 + // see + // ( Self::read_field_le::(BLK_VERSION_MAJOR), Self::read_field_le::(BLK_VERSION_MINOR), @@ -51,7 +51,7 @@ impl Efuse { /// Get version of RTC calibration block /// - /// see https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c6/esp_efuse_rtc_calib.c#L20 + /// see pub fn get_rtc_calib_version() -> u8 { let (_major, minor) = Self::get_block_version(); if minor >= 1 { @@ -63,7 +63,7 @@ impl Efuse { /// Get ADC initial code for specified attenuation from efuse /// - /// see https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c6/esp_efuse_rtc_calib.c#L32 + /// see pub fn get_rtc_calib_init_code(_unit: u8, atten: Attenuation) -> Option { let version = Self::get_rtc_calib_version(); @@ -71,7 +71,7 @@ impl Efuse { return None; } - // See https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c6/esp_efuse_table.csv#L147-L152 + // See let init_code: u16 = Self::read_field_le(match atten { Attenuation::Attenuation0dB => ADC1_INIT_CODE_ATTEN0, Attenuation::Attenuation2p5dB => ADC1_INIT_CODE_ATTEN1, @@ -84,7 +84,7 @@ impl Efuse { /// Get ADC reference point voltage for specified attenuation in millivolts /// - /// see https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c6/esp_efuse_rtc_calib.c#L42 + /// see pub fn get_rtc_calib_cal_mv(_unit: u8, atten: Attenuation) -> u16 { match atten { Attenuation::Attenuation0dB => 400, @@ -96,7 +96,7 @@ impl Efuse { /// Get ADC reference point digital code for specified attenuation /// - /// see https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c6/esp_efuse_rtc_calib.c#L42 + /// see pub fn get_rtc_calib_cal_code(_unit: u8, atten: Attenuation) -> Option { let version = Self::get_rtc_calib_version(); @@ -104,7 +104,7 @@ impl Efuse { return None; } - // See https://github.com/espressif/esp-idf/blob/903af13e8/components/efuse/esp32c6/esp_efuse_table.csv#L153-L156 + // See let cal_code: u16 = Self::read_field_le(match atten { Attenuation::Attenuation0dB => ADC1_CAL_VOL_ATTEN0, Attenuation::Attenuation2p5dB => ADC1_CAL_VOL_ATTEN1, diff --git a/esp-hal-common/src/spi.rs b/esp-hal-common/src/spi.rs index 35b47bbc815..3420bcf6e59 100644 --- a/esp-hal-common/src/spi.rs +++ b/esp-hal-common/src/spi.rs @@ -34,17 +34,16 @@ //! - Use the [`SpiBus`](embedded_hal_1::spi::SpiBus) trait (requires the "eh1" //! feature) and its associated functions to initiate transactions with //! simultaneous reads and writes, or -//! - Use the [`SpiBusWrite`](embedded_hal_1::spi::SpiBusWrite) and -//! [`SpiBusRead`](embedded_hal_1::spi::SpiBusRead) traits (requires the "eh1" -//! feature) and their associated functions to read or write mutiple bytes at -//! a time. +// TODO async moved to embedded-hal-bus: +//! - Use the `ExclusiveDevice` struct from `embedded-hal-bus` or +//! `embedded-hal-async` (recommended). //! //! //! ## Shared SPI access //! //! If you have multiple devices on the same SPI bus that each have their own CS -//! line, you may want to have a look at the [`SpiBusController`] and -//! [`SpiBusDevice`] implemented here. These give exclusive access to the +//! line, you may want to have a look at the [`ehal1::SpiBusController`] and +//! [`ehal1::SpiBusDevice`] implemented here. These give exclusive access to the //! underlying SPI bus by means of a Mutex. This ensures that device //! transactions do not interfere with each other. @@ -2408,7 +2407,7 @@ pub trait Instance { /// sequential transfers are performed. This function will return before /// all bytes of the last chunk to transmit have been sent to the wire. If /// you must ensure that the whole messages was written correctly, use - /// [`flush`]. + /// [`Self::flush`]. // FIXME: See below. fn write_bytes(&mut self, words: &[u8]) -> Result<(), Error> { let reg_block = self.register_block(); @@ -2472,7 +2471,7 @@ pub trait Instance { /// /// Sends out a stuffing byte for every byte to read. This function doesn't /// perform flushing. If you want to read the response to something you - /// have written before, consider using [`transfer`] instead. + /// have written before, consider using [`Self::transfer`] instead. fn read_bytes(&mut self, words: &mut [u8]) -> Result<(), Error> { let empty_array = [EMPTY_WRITE_PAD; FIFO_SIZE]; @@ -2488,7 +2487,7 @@ pub trait Instance { /// /// Copies the contents of the SPI receive FIFO into `words`. This function /// doesn't perform flushing. If you want to read the response to - /// something you have written before, consider using [`transfer`] + /// something you have written before, consider using [`Self::transfer`] /// instead. // FIXME: Using something like `core::slice::from_raw_parts` and // `copy_from_slice` on the receive registers works only for the esp32 and diff --git a/esp-hal-procmacros/src/lib.rs b/esp-hal-procmacros/src/lib.rs index e3a58a97f24..7061dbb67df 100644 --- a/esp-hal-procmacros/src/lib.rs +++ b/esp-hal-procmacros/src/lib.rs @@ -2,6 +2,7 @@ //! marking interrupt handlers. #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")] +#![deny(warnings)] use darling::{ast::NestedMeta, FromMeta}; use proc_macro::{self, Span, TokenStream}; diff --git a/esp-hal-smartled/.cargo/config.toml b/esp-hal-smartled/.cargo/config.toml new file mode 100644 index 00000000000..2a098def58d --- /dev/null +++ b/esp-hal-smartled/.cargo/config.toml @@ -0,0 +1,18 @@ +[target.xtensa-esp32s2-none-elf] +rustflags = [ + # enable the atomic codegen option for Xtensa + "-C", "target-feature=+s32c1i", + + # tell the core library have atomics even though it's not specified in the target definition + "--cfg", "target_has_atomic_load_store", + "--cfg", 'target_has_atomic_load_store="8"', + "--cfg", 'target_has_atomic_load_store="16"', + "--cfg", 'target_has_atomic_load_store="32"', + "--cfg", 'target_has_atomic_load_store="ptr"', + # enable cas + "--cfg", "target_has_atomic", + "--cfg", 'target_has_atomic="8"', + "--cfg", 'target_has_atomic="16"', + "--cfg", 'target_has_atomic="32"', + "--cfg", 'target_has_atomic="ptr"', +] diff --git a/esp-hal-smartled/src/lib.rs b/esp-hal-smartled/src/lib.rs index 839ec4f8375..4b63785e94c 100644 --- a/esp-hal-smartled/src/lib.rs +++ b/esp-hal-smartled/src/lib.rs @@ -26,8 +26,9 @@ //! ``` #![no_std] -#![deny(missing_docs)] #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")] +#![deny(missing_docs)] +#![deny(warnings)] use core::slice::IterMut; diff --git a/esp-riscv-rt/src/lib.rs b/esp-riscv-rt/src/lib.rs index bfba0f0bcd7..64a8aee0815 100644 --- a/esp-riscv-rt/src/lib.rs +++ b/esp-riscv-rt/src/lib.rs @@ -15,6 +15,7 @@ // NOTE: Adapted from riscv-rt/src/lib.rs #![no_std] +#![deny(warnings)] use core::arch::global_asm; @@ -50,7 +51,7 @@ extern "C" { /// never returns. #[link_section = ".init.rust"] #[export_name = "_start_rust"] -pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! { +extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! { extern "Rust" { // This symbol will be provided by the user via `#[entry]` fn main(a0: usize, a1: usize, a2: usize) -> !; @@ -61,11 +62,13 @@ pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! { } - __post_init(); + unsafe { + __post_init(); - _setup_interrupts(); + _setup_interrupts(); - main(a0, a1, a2); + main(a0, a1, a2); + } } /// Registers saved in trap handler @@ -117,7 +120,7 @@ pub struct TrapFrame { /// ExceptionHandler or one of the core interrupt handlers is called. #[link_section = ".trap.rust"] #[export_name = "_start_trap_rust"] -pub unsafe extern "C" fn start_trap_rust(trap_frame: *const TrapFrame) { +extern "C" fn start_trap_rust(trap_frame: *const TrapFrame) { extern "C" { fn ExceptionHandler(trap_frame: &TrapFrame); fn DefaultHandler(); diff --git a/esp32h2-hal/examples/rmt_tx.rs b/esp32h2-hal/examples/rmt_tx.rs index 4ef2c34ef1a..aeda3b555bd 100644 --- a/esp32h2-hal/examples/rmt_tx.rs +++ b/esp32h2-hal/examples/rmt_tx.rs @@ -20,7 +20,7 @@ use esp_backtrace as _; #[entry] fn main() -> ! { let peripherals = Peripherals::take(); - let mut system = peripherals.PCR.split(); + let system = peripherals.PCR.split(); let mut clock_control = system.peripheral_clock_control; let clocks = ClockControl::boot_defaults(system.clock_control).freeze(); diff --git a/esp32s3-hal/examples/rmt_tx.rs b/esp32s3-hal/examples/rmt_tx.rs index c1ae5f75432..5bb1b733588 100644 --- a/esp32s3-hal/examples/rmt_tx.rs +++ b/esp32s3-hal/examples/rmt_tx.rs @@ -18,7 +18,6 @@ use esp_hal_common::{ rmt::{PulseCode, TxChannel, TxChannelConfig, TxChannelCreator}, Rmt, }; -use esp_println::println; #[entry] fn main() -> ! {