From 364a0ec4f9abaff30c403fdce745002e1c564aa7 Mon Sep 17 00:00:00 2001
From: dragonn <dragonn@op.pl>
Date: Sun, 17 Sep 2023 11:37:04 +0200
Subject: [PATCH 1/2] Add new_no_miso to Spi FullDuplexMode

---
 esp-hal-common/src/spi.rs | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/esp-hal-common/src/spi.rs b/esp-hal-common/src/spi.rs
index e556a2d30b6..48210b6777f 100644
--- a/esp-hal-common/src/spi.rs
+++ b/esp-hal-common/src/spi.rs
@@ -477,6 +477,30 @@ where
         Self::new_internal(spi, frequency, mode, peripheral_clock_control, clocks)
     }
 
+    /// Constructs an SPI instance in 8bit dataframe mode without MISO pin.
+    pub fn new_no_miso<SCK: OutputPin, MOSI: OutputPin, CS: OutputPin>(
+        spi: impl Peripheral<P = T> + 'd,
+        sck: impl Peripheral<P = SCK> + 'd,
+        mosi: impl Peripheral<P = MOSI> + 'd,
+        cs: impl Peripheral<P = CS> + 'd,
+        frequency: HertzU32,
+        mode: SpiMode,
+        peripheral_clock_control: &mut PeripheralClockControl,
+        clocks: &Clocks,
+    ) -> Spi<'d, T, FullDuplexMode> {
+        crate::into_ref!(spi, sck, mosi, cs);
+        sck.set_to_push_pull_output()
+            .connect_peripheral_to_output(spi.sclk_signal());
+
+        mosi.set_to_push_pull_output()
+            .connect_peripheral_to_output(spi.mosi_signal());
+
+        cs.set_to_push_pull_output()
+            .connect_peripheral_to_output(spi.cs_signal());
+
+        Self::new_internal(spi, frequency, mode, peripheral_clock_control, clocks)
+    }
+
     /// Constructs an SPI instance in 8bit dataframe mode without CS and MISO
     /// pin.
     pub fn new_no_cs_no_miso<SCK: OutputPin, MOSI: OutputPin>(

From 0b4e5e71799355f3a2c37550a53b756c07df367d Mon Sep 17 00:00:00 2001
From: dragonn <dragonn@op.pl>
Date: Sun, 17 Sep 2023 11:43:21 +0200
Subject: [PATCH 2/2] adjust changelog

---
 CHANGELOG.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 24f755d14e7..1bbac456fc8 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -14,6 +14,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Implement enabling/disabling BLE clock on ESP32-C6 (#784)
 - Async support for RMT (#787)
 - Implement `defmt::Format` for more types (#786)
+- Add new_no_miso to Spi FullDuplexMode (#794)
 
 ### Changed