diff --git a/esp32h2/src/ledc/ch_conf0.rs b/esp32h2/src/ledc/ch_conf0.rs index b0cf362269..7811404f35 100644 --- a/esp32h2/src/ledc/ch_conf0.rs +++ b/esp32h2/src/ledc/ch_conf0.rs @@ -34,100 +34,99 @@ impl From> for W { W(writer) } } -#[doc = "Field `TIMER_SEL_CH` reader - This field is used to select one of timers for channel %s. 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3"] -pub type TIMER_SEL_CH_R = crate::FieldReader; -#[doc = "Field `TIMER_SEL_CH` writer - This field is used to select one of timers for channel %s. 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3"] -pub type TIMER_SEL_CH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CH_CONF0_SPEC, u8, u8, 2, O>; -#[doc = "Field `SIG_OUT_EN_CH` reader - Set this bit to enable signal output on channel %s."] -pub type SIG_OUT_EN_CH_R = crate::BitReader; -#[doc = "Field `SIG_OUT_EN_CH` writer - Set this bit to enable signal output on channel %s."] -pub type SIG_OUT_EN_CH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH_CONF0_SPEC, bool, O>; -#[doc = "Field `IDLE_LV_CH` reader - This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0)."] -pub type IDLE_LV_CH_R = crate::BitReader; -#[doc = "Field `IDLE_LV_CH` writer - This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0)."] -pub type IDLE_LV_CH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH_CONF0_SPEC, bool, O>; -#[doc = "Field `PARA_UP_CH` writer - This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware."] -pub type PARA_UP_CH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH_CONF0_SPEC, bool, O>; -#[doc = "Field `OVF_NUM_CH` reader - This register is used to configure the maximum times of overflow minus 1. The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times."] -pub type OVF_NUM_CH_R = crate::FieldReader; -#[doc = "Field `OVF_NUM_CH` writer - This register is used to configure the maximum times of overflow minus 1. The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times."] -pub type OVF_NUM_CH_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, CH_CONF0_SPEC, u16, u16, 10, O>; -#[doc = "Field `OVF_CNT_EN_CH` reader - This bit is used to enable the ovf_cnt of channel %s."] -pub type OVF_CNT_EN_CH_R = crate::BitReader; -#[doc = "Field `OVF_CNT_EN_CH` writer - This bit is used to enable the ovf_cnt of channel %s."] -pub type OVF_CNT_EN_CH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH_CONF0_SPEC, bool, O>; -#[doc = "Field `OVF_CNT_RESET_CH` writer - Set this bit to reset the ovf_cnt of channel %s."] -pub type OVF_CNT_RESET_CH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH_CONF0_SPEC, bool, O>; +#[doc = "Field `TIMER_SEL` reader - This field is used to select one of timers for channel %s. 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3"] +pub type TIMER_SEL_R = crate::FieldReader; +#[doc = "Field `TIMER_SEL` writer - This field is used to select one of timers for channel %s. 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3"] +pub type TIMER_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CH_CONF0_SPEC, u8, u8, 2, O>; +#[doc = "Field `SIG_OUT_EN` reader - Set this bit to enable signal output on channel %s."] +pub type SIG_OUT_EN_R = crate::BitReader; +#[doc = "Field `SIG_OUT_EN` writer - Set this bit to enable signal output on channel %s."] +pub type SIG_OUT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH_CONF0_SPEC, bool, O>; +#[doc = "Field `IDLE_LV` reader - This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0)."] +pub type IDLE_LV_R = crate::BitReader; +#[doc = "Field `IDLE_LV` writer - This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0)."] +pub type IDLE_LV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH_CONF0_SPEC, bool, O>; +#[doc = "Field `PARA_UP` writer - This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware."] +pub type PARA_UP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH_CONF0_SPEC, bool, O>; +#[doc = "Field `OVF_NUM` reader - This register is used to configure the maximum times of overflow minus 1. The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times."] +pub type OVF_NUM_R = crate::FieldReader; +#[doc = "Field `OVF_NUM` writer - This register is used to configure the maximum times of overflow minus 1. The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times."] +pub type OVF_NUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CH_CONF0_SPEC, u16, u16, 10, O>; +#[doc = "Field `OVF_CNT_EN` reader - This bit is used to enable the ovf_cnt of channel %s."] +pub type OVF_CNT_EN_R = crate::BitReader; +#[doc = "Field `OVF_CNT_EN` writer - This bit is used to enable the ovf_cnt of channel %s."] +pub type OVF_CNT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH_CONF0_SPEC, bool, O>; +#[doc = "Field `OVF_CNT_RESET` writer - Set this bit to reset the ovf_cnt of channel %s."] +pub type OVF_CNT_RESET_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH_CONF0_SPEC, bool, O>; impl R { #[doc = "Bits 0:1 - This field is used to select one of timers for channel %s. 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3"] #[inline(always)] - pub fn timer_sel_ch(&self) -> TIMER_SEL_CH_R { - TIMER_SEL_CH_R::new((self.bits & 3) as u8) + pub fn timer_sel(&self) -> TIMER_SEL_R { + TIMER_SEL_R::new((self.bits & 3) as u8) } #[doc = "Bit 2 - Set this bit to enable signal output on channel %s."] #[inline(always)] - pub fn sig_out_en_ch(&self) -> SIG_OUT_EN_CH_R { - SIG_OUT_EN_CH_R::new(((self.bits >> 2) & 1) != 0) + pub fn sig_out_en(&self) -> SIG_OUT_EN_R { + SIG_OUT_EN_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bit 3 - This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0)."] #[inline(always)] - pub fn idle_lv_ch(&self) -> IDLE_LV_CH_R { - IDLE_LV_CH_R::new(((self.bits >> 3) & 1) != 0) + pub fn idle_lv(&self) -> IDLE_LV_R { + IDLE_LV_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bits 5:14 - This register is used to configure the maximum times of overflow minus 1. The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times."] #[inline(always)] - pub fn ovf_num_ch(&self) -> OVF_NUM_CH_R { - OVF_NUM_CH_R::new(((self.bits >> 5) & 0x03ff) as u16) + pub fn ovf_num(&self) -> OVF_NUM_R { + OVF_NUM_R::new(((self.bits >> 5) & 0x03ff) as u16) } #[doc = "Bit 15 - This bit is used to enable the ovf_cnt of channel %s."] #[inline(always)] - pub fn ovf_cnt_en_ch(&self) -> OVF_CNT_EN_CH_R { - OVF_CNT_EN_CH_R::new(((self.bits >> 15) & 1) != 0) + pub fn ovf_cnt_en(&self) -> OVF_CNT_EN_R { + OVF_CNT_EN_R::new(((self.bits >> 15) & 1) != 0) } } impl W { #[doc = "Bits 0:1 - This field is used to select one of timers for channel %s. 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3"] #[inline(always)] #[must_use] - pub fn timer_sel_ch(&mut self) -> TIMER_SEL_CH_W<0> { - TIMER_SEL_CH_W::new(self) + pub fn timer_sel(&mut self) -> TIMER_SEL_W<0> { + TIMER_SEL_W::new(self) } #[doc = "Bit 2 - Set this bit to enable signal output on channel %s."] #[inline(always)] #[must_use] - pub fn sig_out_en_ch(&mut self) -> SIG_OUT_EN_CH_W<2> { - SIG_OUT_EN_CH_W::new(self) + pub fn sig_out_en(&mut self) -> SIG_OUT_EN_W<2> { + SIG_OUT_EN_W::new(self) } #[doc = "Bit 3 - This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0)."] #[inline(always)] #[must_use] - pub fn idle_lv_ch(&mut self) -> IDLE_LV_CH_W<3> { - IDLE_LV_CH_W::new(self) + pub fn idle_lv(&mut self) -> IDLE_LV_W<3> { + IDLE_LV_W::new(self) } #[doc = "Bit 4 - This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware."] #[inline(always)] #[must_use] - pub fn para_up_ch(&mut self) -> PARA_UP_CH_W<4> { - PARA_UP_CH_W::new(self) + pub fn para_up(&mut self) -> PARA_UP_W<4> { + PARA_UP_W::new(self) } #[doc = "Bits 5:14 - This register is used to configure the maximum times of overflow minus 1. The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times."] #[inline(always)] #[must_use] - pub fn ovf_num_ch(&mut self) -> OVF_NUM_CH_W<5> { - OVF_NUM_CH_W::new(self) + pub fn ovf_num(&mut self) -> OVF_NUM_W<5> { + OVF_NUM_W::new(self) } #[doc = "Bit 15 - This bit is used to enable the ovf_cnt of channel %s."] #[inline(always)] #[must_use] - pub fn ovf_cnt_en_ch(&mut self) -> OVF_CNT_EN_CH_W<15> { - OVF_CNT_EN_CH_W::new(self) + pub fn ovf_cnt_en(&mut self) -> OVF_CNT_EN_W<15> { + OVF_CNT_EN_W::new(self) } #[doc = "Bit 16 - Set this bit to reset the ovf_cnt of channel %s."] #[inline(always)] #[must_use] - pub fn ovf_cnt_reset_ch(&mut self) -> OVF_CNT_RESET_CH_W<16> { - OVF_CNT_RESET_CH_W::new(self) + pub fn ovf_cnt_reset(&mut self) -> OVF_CNT_RESET_W<16> { + OVF_CNT_RESET_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32h2/src/ledc/ch_conf1.rs b/esp32h2/src/ledc/ch_conf1.rs index f50c747e83..e0de28cb42 100644 --- a/esp32h2/src/ledc/ch_conf1.rs +++ b/esp32h2/src/ledc/ch_conf1.rs @@ -34,23 +34,23 @@ impl From> for W { W(writer) } } -#[doc = "Field `DUTY_START_CH` reader - Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1."] -pub type DUTY_START_CH_R = crate::BitReader; -#[doc = "Field `DUTY_START_CH` writer - Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1."] -pub type DUTY_START_CH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH_CONF1_SPEC, bool, O>; +#[doc = "Field `DUTY_START` reader - Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1."] +pub type DUTY_START_R = crate::BitReader; +#[doc = "Field `DUTY_START` writer - Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1."] +pub type DUTY_START_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH_CONF1_SPEC, bool, O>; impl R { #[doc = "Bit 31 - Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1."] #[inline(always)] - pub fn duty_start_ch(&self) -> DUTY_START_CH_R { - DUTY_START_CH_R::new(((self.bits >> 31) & 1) != 0) + pub fn duty_start(&self) -> DUTY_START_R { + DUTY_START_R::new(((self.bits >> 31) & 1) != 0) } } impl W { #[doc = "Bit 31 - Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1."] #[inline(always)] #[must_use] - pub fn duty_start_ch(&mut self) -> DUTY_START_CH_W<31> { - DUTY_START_CH_W::new(self) + pub fn duty_start(&mut self) -> DUTY_START_W<31> { + DUTY_START_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32h2/src/ledc/ch_duty.rs b/esp32h2/src/ledc/ch_duty.rs index 922071e5e3..2431deab4d 100644 --- a/esp32h2/src/ledc/ch_duty.rs +++ b/esp32h2/src/ledc/ch_duty.rs @@ -34,23 +34,23 @@ impl From> for W { W(writer) } } -#[doc = "Field `DUTY_CH` reader - This register is used to change the output duty by controlling the Lpoint. The output value turns to low when the selected timers has reached the Lpoint."] -pub type DUTY_CH_R = crate::FieldReader; -#[doc = "Field `DUTY_CH` writer - This register is used to change the output duty by controlling the Lpoint. The output value turns to low when the selected timers has reached the Lpoint."] -pub type DUTY_CH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CH_DUTY_SPEC, u32, u32, 25, O>; +#[doc = "Field `DUTY` reader - This register is used to change the output duty by controlling the Lpoint. The output value turns to low when the selected timers has reached the Lpoint."] +pub type DUTY_R = crate::FieldReader; +#[doc = "Field `DUTY` writer - This register is used to change the output duty by controlling the Lpoint. The output value turns to low when the selected timers has reached the Lpoint."] +pub type DUTY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CH_DUTY_SPEC, u32, u32, 25, O>; impl R { #[doc = "Bits 0:24 - This register is used to change the output duty by controlling the Lpoint. The output value turns to low when the selected timers has reached the Lpoint."] #[inline(always)] - pub fn duty_ch(&self) -> DUTY_CH_R { - DUTY_CH_R::new(self.bits & 0x01ff_ffff) + pub fn duty(&self) -> DUTY_R { + DUTY_R::new(self.bits & 0x01ff_ffff) } } impl W { #[doc = "Bits 0:24 - This register is used to change the output duty by controlling the Lpoint. The output value turns to low when the selected timers has reached the Lpoint."] #[inline(always)] #[must_use] - pub fn duty_ch(&mut self) -> DUTY_CH_W<0> { - DUTY_CH_W::new(self) + pub fn duty(&mut self) -> DUTY_W<0> { + DUTY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32h2/src/ledc/ch_hpoint.rs b/esp32h2/src/ledc/ch_hpoint.rs index 0c1c73a1a4..31338f59c6 100644 --- a/esp32h2/src/ledc/ch_hpoint.rs +++ b/esp32h2/src/ledc/ch_hpoint.rs @@ -34,24 +34,23 @@ impl From> for W { W(writer) } } -#[doc = "Field `HPOINT_CH` reader - The output value changes to high when the selected timers has reached the value specified by this register."] -pub type HPOINT_CH_R = crate::FieldReader; -#[doc = "Field `HPOINT_CH` writer - The output value changes to high when the selected timers has reached the value specified by this register."] -pub type HPOINT_CH_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, CH_HPOINT_SPEC, u32, u32, 20, O>; +#[doc = "Field `HPOINT` reader - The output value changes to high when the selected timers has reached the value specified by this register."] +pub type HPOINT_R = crate::FieldReader; +#[doc = "Field `HPOINT` writer - The output value changes to high when the selected timers has reached the value specified by this register."] +pub type HPOINT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CH_HPOINT_SPEC, u32, u32, 20, O>; impl R { #[doc = "Bits 0:19 - The output value changes to high when the selected timers has reached the value specified by this register."] #[inline(always)] - pub fn hpoint_ch(&self) -> HPOINT_CH_R { - HPOINT_CH_R::new(self.bits & 0x000f_ffff) + pub fn hpoint(&self) -> HPOINT_R { + HPOINT_R::new(self.bits & 0x000f_ffff) } } impl W { #[doc = "Bits 0:19 - The output value changes to high when the selected timers has reached the value specified by this register."] #[inline(always)] #[must_use] - pub fn hpoint_ch(&mut self) -> HPOINT_CH_W<0> { - HPOINT_CH_W::new(self) + pub fn hpoint(&mut self) -> HPOINT_W<0> { + HPOINT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32h2/src/ledc/timer_conf.rs b/esp32h2/src/ledc/timer_conf.rs index 297efe6e44..73dfe48be2 100644 --- a/esp32h2/src/ledc/timer_conf.rs +++ b/esp32h2/src/ledc/timer_conf.rs @@ -34,93 +34,91 @@ impl From> for W { W(writer) } } -#[doc = "Field `TIMER_DUTY_RES` reader - This register is used to control the range of the counter in timer %s."] -pub type TIMER_DUTY_RES_R = crate::FieldReader; -#[doc = "Field `TIMER_DUTY_RES` writer - This register is used to control the range of the counter in timer %s."] -pub type TIMER_DUTY_RES_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, TIMER_CONF_SPEC, u8, u8, 5, O>; -#[doc = "Field `CLK_DIV_TIMER` reader - This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part."] -pub type CLK_DIV_TIMER_R = crate::FieldReader; -#[doc = "Field `CLK_DIV_TIMER` writer - This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part."] -pub type CLK_DIV_TIMER_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, TIMER_CONF_SPEC, u32, u32, 18, O>; -#[doc = "Field `TIMER_PAUSE` reader - This bit is used to suspend the counter in timer %s."] -pub type TIMER_PAUSE_R = crate::BitReader; -#[doc = "Field `TIMER_PAUSE` writer - This bit is used to suspend the counter in timer %s."] -pub type TIMER_PAUSE_W<'a, const O: u8> = crate::BitWriter<'a, u32, TIMER_CONF_SPEC, bool, O>; -#[doc = "Field `TIMER_RST` reader - This bit is used to reset timer %s. The counter will show 0 after reset."] -pub type TIMER_RST_R = crate::BitReader; -#[doc = "Field `TIMER_RST` writer - This bit is used to reset timer %s. The counter will show 0 after reset."] -pub type TIMER_RST_W<'a, const O: u8> = crate::BitWriter<'a, u32, TIMER_CONF_SPEC, bool, O>; -#[doc = "Field `TICK_SEL_TIMER` reader - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL\\[1:0\\] should be 1, otherwise the timer clock may be not accurate. 1'h0: SLOW_CLK 1'h1: REF_TICK"] -pub type TICK_SEL_TIMER_R = crate::BitReader; -#[doc = "Field `TICK_SEL_TIMER` writer - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL\\[1:0\\] should be 1, otherwise the timer clock may be not accurate. 1'h0: SLOW_CLK 1'h1: REF_TICK"] -pub type TICK_SEL_TIMER_W<'a, const O: u8> = crate::BitWriter<'a, u32, TIMER_CONF_SPEC, bool, O>; -#[doc = "Field `TIMER_PARA_UP` writer - Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES."] -pub type TIMER_PARA_UP_W<'a, const O: u8> = crate::BitWriter<'a, u32, TIMER_CONF_SPEC, bool, O>; +#[doc = "Field `DUTY_RES` reader - This register is used to control the range of the counter in timer %s."] +pub type DUTY_RES_R = crate::FieldReader; +#[doc = "Field `DUTY_RES` writer - This register is used to control the range of the counter in timer %s."] +pub type DUTY_RES_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TIMER_CONF_SPEC, u8, u8, 5, O>; +#[doc = "Field `CLK_DIV` reader - This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part."] +pub type CLK_DIV_R = crate::FieldReader; +#[doc = "Field `CLK_DIV` writer - This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part."] +pub type CLK_DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TIMER_CONF_SPEC, u32, u32, 18, O>; +#[doc = "Field `PAUSE` reader - This bit is used to suspend the counter in timer %s."] +pub type PAUSE_R = crate::BitReader; +#[doc = "Field `PAUSE` writer - This bit is used to suspend the counter in timer %s."] +pub type PAUSE_W<'a, const O: u8> = crate::BitWriter<'a, u32, TIMER_CONF_SPEC, bool, O>; +#[doc = "Field `RST` reader - This bit is used to reset timer %s. The counter will show 0 after reset."] +pub type RST_R = crate::BitReader; +#[doc = "Field `RST` writer - This bit is used to reset timer %s. The counter will show 0 after reset."] +pub type RST_W<'a, const O: u8> = crate::BitWriter<'a, u32, TIMER_CONF_SPEC, bool, O>; +#[doc = "Field `TICK_SEL` reader - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL\\[1:0\\] should be 1, otherwise the timer clock may be not accurate. 1'h0: SLOW_CLK 1'h1: REF_TICK"] +pub type TICK_SEL_R = crate::BitReader; +#[doc = "Field `TICK_SEL` writer - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL\\[1:0\\] should be 1, otherwise the timer clock may be not accurate. 1'h0: SLOW_CLK 1'h1: REF_TICK"] +pub type TICK_SEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, TIMER_CONF_SPEC, bool, O>; +#[doc = "Field `PARA_UP` writer - Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES."] +pub type PARA_UP_W<'a, const O: u8> = crate::BitWriter<'a, u32, TIMER_CONF_SPEC, bool, O>; impl R { #[doc = "Bits 0:4 - This register is used to control the range of the counter in timer %s."] #[inline(always)] - pub fn timer_duty_res(&self) -> TIMER_DUTY_RES_R { - TIMER_DUTY_RES_R::new((self.bits & 0x1f) as u8) + pub fn duty_res(&self) -> DUTY_RES_R { + DUTY_RES_R::new((self.bits & 0x1f) as u8) } #[doc = "Bits 5:22 - This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part."] #[inline(always)] - pub fn clk_div_timer(&self) -> CLK_DIV_TIMER_R { - CLK_DIV_TIMER_R::new((self.bits >> 5) & 0x0003_ffff) + pub fn clk_div(&self) -> CLK_DIV_R { + CLK_DIV_R::new((self.bits >> 5) & 0x0003_ffff) } #[doc = "Bit 23 - This bit is used to suspend the counter in timer %s."] #[inline(always)] - pub fn timer_pause(&self) -> TIMER_PAUSE_R { - TIMER_PAUSE_R::new(((self.bits >> 23) & 1) != 0) + pub fn pause(&self) -> PAUSE_R { + PAUSE_R::new(((self.bits >> 23) & 1) != 0) } #[doc = "Bit 24 - This bit is used to reset timer %s. The counter will show 0 after reset."] #[inline(always)] - pub fn timer_rst(&self) -> TIMER_RST_R { - TIMER_RST_R::new(((self.bits >> 24) & 1) != 0) + pub fn rst(&self) -> RST_R { + RST_R::new(((self.bits >> 24) & 1) != 0) } #[doc = "Bit 25 - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL\\[1:0\\] should be 1, otherwise the timer clock may be not accurate. 1'h0: SLOW_CLK 1'h1: REF_TICK"] #[inline(always)] - pub fn tick_sel_timer(&self) -> TICK_SEL_TIMER_R { - TICK_SEL_TIMER_R::new(((self.bits >> 25) & 1) != 0) + pub fn tick_sel(&self) -> TICK_SEL_R { + TICK_SEL_R::new(((self.bits >> 25) & 1) != 0) } } impl W { #[doc = "Bits 0:4 - This register is used to control the range of the counter in timer %s."] #[inline(always)] #[must_use] - pub fn timer_duty_res(&mut self) -> TIMER_DUTY_RES_W<0> { - TIMER_DUTY_RES_W::new(self) + pub fn duty_res(&mut self) -> DUTY_RES_W<0> { + DUTY_RES_W::new(self) } #[doc = "Bits 5:22 - This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part."] #[inline(always)] #[must_use] - pub fn clk_div_timer(&mut self) -> CLK_DIV_TIMER_W<5> { - CLK_DIV_TIMER_W::new(self) + pub fn clk_div(&mut self) -> CLK_DIV_W<5> { + CLK_DIV_W::new(self) } #[doc = "Bit 23 - This bit is used to suspend the counter in timer %s."] #[inline(always)] #[must_use] - pub fn timer_pause(&mut self) -> TIMER_PAUSE_W<23> { - TIMER_PAUSE_W::new(self) + pub fn pause(&mut self) -> PAUSE_W<23> { + PAUSE_W::new(self) } #[doc = "Bit 24 - This bit is used to reset timer %s. The counter will show 0 after reset."] #[inline(always)] #[must_use] - pub fn timer_rst(&mut self) -> TIMER_RST_W<24> { - TIMER_RST_W::new(self) + pub fn rst(&mut self) -> RST_W<24> { + RST_W::new(self) } #[doc = "Bit 25 - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL\\[1:0\\] should be 1, otherwise the timer clock may be not accurate. 1'h0: SLOW_CLK 1'h1: REF_TICK"] #[inline(always)] #[must_use] - pub fn tick_sel_timer(&mut self) -> TICK_SEL_TIMER_W<25> { - TICK_SEL_TIMER_W::new(self) + pub fn tick_sel(&mut self) -> TICK_SEL_W<25> { + TICK_SEL_W::new(self) } #[doc = "Bit 26 - Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES."] #[inline(always)] #[must_use] - pub fn timer_para_up(&mut self) -> TIMER_PARA_UP_W<26> { - TIMER_PARA_UP_W::new(self) + pub fn para_up(&mut self) -> PARA_UP_W<26> { + PARA_UP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] diff --git a/esp32h2/svd/patches/esp32h2.yaml b/esp32h2/svd/patches/esp32h2.yaml index ee5d55e9e7..2ee2bf0664 100644 --- a/esp32h2/svd/patches/esp32h2.yaml +++ b/esp32h2/svd/patches/esp32h2.yaml @@ -187,3 +187,14 @@ RMT: name: CH0_RX_ERR_INT_CLR RX_CH3_ERR_INT_CLR: name: CH1_RX_ERR_INT_CLR + +LEDC: + "*": + _strip_end: "_CH" + "TIMER%s_CONF": + _strip: "TIMER_" + _modify: + TICK_SEL_TIMER: + name: TICK_SEL + CLK_DIV_TIMER: + name: CLK_DIV \ No newline at end of file