diff --git a/esp32c3/src/fe.rs b/esp32c3/src/fe.rs new file mode 100644 index 0000000000..7249177834 --- /dev/null +++ b/esp32c3/src/fe.rs @@ -0,0 +1,18 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved0: [u8; 0x90], + gen_ctrl: GEN_CTRL, +} +impl RegisterBlock { + #[doc = "0x90 - FE General Control Register"] + #[inline(always)] + pub const fn gen_ctrl(&self) -> &GEN_CTRL { + &self.gen_ctrl + } +} +#[doc = "GEN_CTRL (rw) register accessor: FE General Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`gen_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gen_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gen_ctrl`] module"] +pub type GEN_CTRL = crate::Reg; +#[doc = "FE General Control Register"] +pub mod gen_ctrl; diff --git a/esp32c3/src/fe/gen_ctrl.rs b/esp32c3/src/fe/gen_ctrl.rs new file mode 100644 index 0000000000..b0d00836ae --- /dev/null +++ b/esp32c3/src/fe/gen_ctrl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `GEN_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `GEN_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `IQ_EST_FORCE_PD` reader - Force Power Down for IQ Estimation"] +pub type IQ_EST_FORCE_PD_R = crate::BitReader; +#[doc = "Field `IQ_EST_FORCE_PD` writer - Force Power Down for IQ Estimation"] +pub type IQ_EST_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IQ_EST_FORCE_PU` reader - Force Power Up for IQ Estimation"] +pub type IQ_EST_FORCE_PU_R = crate::BitReader; +#[doc = "Field `IQ_EST_FORCE_PU` writer - Force Power Up for IQ Estimation"] +pub type IQ_EST_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 4 - Force Power Down for IQ Estimation"] + #[inline(always)] + pub fn iq_est_force_pd(&self) -> IQ_EST_FORCE_PD_R { + IQ_EST_FORCE_PD_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Force Power Up for IQ Estimation"] + #[inline(always)] + pub fn iq_est_force_pu(&self) -> IQ_EST_FORCE_PU_R { + IQ_EST_FORCE_PU_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GEN_CTRL") + .field("iq_est_force_pu", &self.iq_est_force_pu()) + .field("iq_est_force_pd", &self.iq_est_force_pd()) + .finish() + } +} +impl W { + #[doc = "Bit 4 - Force Power Down for IQ Estimation"] + #[inline(always)] + #[must_use] + pub fn iq_est_force_pd(&mut self) -> IQ_EST_FORCE_PD_W { + IQ_EST_FORCE_PD_W::new(self, 4) + } + #[doc = "Bit 5 - Force Power Up for IQ Estimation"] + #[inline(always)] + #[must_use] + pub fn iq_est_force_pu(&mut self) -> IQ_EST_FORCE_PU_W { + IQ_EST_FORCE_PU_W::new(self, 5) + } +} +#[doc = "FE General Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`gen_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gen_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GEN_CTRL_SPEC; +impl crate::RegisterSpec for GEN_CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`gen_ctrl::R`](R) reader structure"] +impl crate::Readable for GEN_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gen_ctrl::W`](W) writer structure"] +impl crate::Writable for GEN_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0; +} +#[doc = "`reset()` method sets GEN_CTRL to value 0"] +impl crate::Resettable for GEN_CTRL_SPEC { + const RESET_VALUE: u8 = 0; +} diff --git a/esp32c3/src/fe2.rs b/esp32c3/src/fe2.rs new file mode 100644 index 0000000000..d45b5ddad5 --- /dev/null +++ b/esp32c3/src/fe2.rs @@ -0,0 +1,18 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved0: [u8; 0xf0], + tx_interp_ctrl: TX_INTERP_CTRL, +} +impl RegisterBlock { + #[doc = "0xf0 - FE2 TX Interpolation Control Register"] + #[inline(always)] + pub const fn tx_interp_ctrl(&self) -> &TX_INTERP_CTRL { + &self.tx_interp_ctrl + } +} +#[doc = "TX_INTERP_CTRL (rw) register accessor: FE2 TX Interpolation Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_interp_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_interp_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_interp_ctrl`] module"] +pub type TX_INTERP_CTRL = crate::Reg; +#[doc = "FE2 TX Interpolation Control Register"] +pub mod tx_interp_ctrl; diff --git a/esp32c3/src/fe2/tx_interp_ctrl.rs b/esp32c3/src/fe2/tx_interp_ctrl.rs new file mode 100644 index 0000000000..c019b49ecc --- /dev/null +++ b/esp32c3/src/fe2/tx_interp_ctrl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `TX_INTERP_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `TX_INTERP_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `TX_INF_FORCE_PD` reader - Force Power Down field"] +pub type TX_INF_FORCE_PD_R = crate::BitReader; +#[doc = "Field `TX_INF_FORCE_PD` writer - Force Power Down field"] +pub type TX_INF_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_INF_FORCE_PU` reader - Force Power Up field"] +pub type TX_INF_FORCE_PU_R = crate::BitReader; +#[doc = "Field `TX_INF_FORCE_PU` writer - Force Power Up field"] +pub type TX_INF_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 9 - Force Power Down field"] + #[inline(always)] + pub fn tx_inf_force_pd(&self) -> TX_INF_FORCE_PD_R { + TX_INF_FORCE_PD_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Force Power Up field"] + #[inline(always)] + pub fn tx_inf_force_pu(&self) -> TX_INF_FORCE_PU_R { + TX_INF_FORCE_PU_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_INTERP_CTRL") + .field("tx_inf_force_pu", &self.tx_inf_force_pu()) + .field("tx_inf_force_pd", &self.tx_inf_force_pd()) + .finish() + } +} +impl W { + #[doc = "Bit 9 - Force Power Down field"] + #[inline(always)] + #[must_use] + pub fn tx_inf_force_pd(&mut self) -> TX_INF_FORCE_PD_W { + TX_INF_FORCE_PD_W::new(self, 9) + } + #[doc = "Bit 10 - Force Power Up field"] + #[inline(always)] + #[must_use] + pub fn tx_inf_force_pu(&mut self) -> TX_INF_FORCE_PU_W { + TX_INF_FORCE_PU_W::new(self, 10) + } +} +#[doc = "FE2 TX Interpolation Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_interp_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_interp_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_INTERP_CTRL_SPEC; +impl crate::RegisterSpec for TX_INTERP_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_interp_ctrl::R`](R) reader structure"] +impl crate::Readable for TX_INTERP_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_interp_ctrl::W`](W) writer structure"] +impl crate::Writable for TX_INTERP_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TX_INTERP_CTRL to value 0"] +impl crate::Resettable for TX_INTERP_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c3/src/lib.rs b/esp32c3/src/lib.rs index 30f6310131..ad6aa88a93 100644 --- a/esp32c3/src/lib.rs +++ b/esp32c3/src/lib.rs @@ -1909,6 +1909,144 @@ impl core::fmt::Debug for XTS_AES { } #[doc = "XTS-AES-128 Flash Encryption"] pub mod xts_aes; +#[doc = "NRX Peripheral"] +pub struct NRX { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for NRX {} +impl NRX { + #[doc = r"Pointer to the register block"] + pub const PTR: *const nrx::RegisterBlock = 0x6001_cc00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const nrx::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for NRX { + type Target = nrx::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for NRX { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("NRX").finish() + } +} +#[doc = "NRX Peripheral"] +pub mod nrx; +#[doc = "need des"] +pub struct FE { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for FE {} +impl FE { + #[doc = r"Pointer to the register block"] + pub const PTR: *const fe::RegisterBlock = 0x6000_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const fe::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for FE { + type Target = fe::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for FE { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FE").finish() + } +} +#[doc = "need des"] +pub mod fe; +#[doc = "need des"] +pub struct FE2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for FE2 {} +impl FE2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const fe2::RegisterBlock = 0x6000_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const fe2::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for FE2 { + type Target = fe2::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for FE2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FE2").finish() + } +} +#[doc = "need des"] +pub mod fe2; #[no_mangle] static mut DEVICE_PERIPHERALS: bool = false; #[doc = r" All the peripherals."] @@ -1988,6 +2126,12 @@ pub struct Peripherals { pub USB_DEVICE: USB_DEVICE, #[doc = "XTS_AES"] pub XTS_AES: XTS_AES, + #[doc = "NRX"] + pub NRX: NRX, + #[doc = "FE"] + pub FE: FE, + #[doc = "FE2"] + pub FE2: FE2, } impl Peripherals { #[doc = r" Returns all the peripherals *once*."] @@ -2047,6 +2191,9 @@ impl Peripherals { UHCI1: UHCI1::steal(), USB_DEVICE: USB_DEVICE::steal(), XTS_AES: XTS_AES::steal(), + NRX: NRX::steal(), + FE: FE::steal(), + FE2: FE2::steal(), } } } diff --git a/esp32c3/src/nrx.rs b/esp32c3/src/nrx.rs new file mode 100644 index 0000000000..e027171e30 --- /dev/null +++ b/esp32c3/src/nrx.rs @@ -0,0 +1,18 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved0: [u8; 0xd4], + nrxpd_ctrl: NRXPD_CTRL, +} +impl RegisterBlock { + #[doc = "0xd4 - NRX Power Down Control Register"] + #[inline(always)] + pub const fn nrxpd_ctrl(&self) -> &NRXPD_CTRL { + &self.nrxpd_ctrl + } +} +#[doc = "NRXPD_CTRL (rw) register accessor: NRX Power Down Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`nrxpd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nrxpd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nrxpd_ctrl`] module"] +pub type NRXPD_CTRL = crate::Reg; +#[doc = "NRX Power Down Control Register"] +pub mod nrxpd_ctrl; diff --git a/esp32c3/src/nrx/nrxpd_ctrl.rs b/esp32c3/src/nrx/nrxpd_ctrl.rs new file mode 100644 index 0000000000..4de238a244 --- /dev/null +++ b/esp32c3/src/nrx/nrxpd_ctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `NRXPD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `NRXPD_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `DEMAP_FORCE_PD` reader - Force Power Down for Demapper"] +pub type DEMAP_FORCE_PD_R = crate::BitReader; +#[doc = "Field `DEMAP_FORCE_PD` writer - Force Power Down for Demapper"] +pub type DEMAP_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEMAP_FORCE_PU` reader - Force Power Up for Demapper"] +pub type DEMAP_FORCE_PU_R = crate::BitReader; +#[doc = "Field `DEMAP_FORCE_PU` writer - Force Power Up for Demapper"] +pub type DEMAP_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VIT_FORCE_PD` reader - Force Power Down for Viterbi Decoder"] +pub type VIT_FORCE_PD_R = crate::BitReader; +#[doc = "Field `VIT_FORCE_PD` writer - Force Power Down for Viterbi Decoder"] +pub type VIT_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VIT_FORCE_PU` reader - Force Power Up for Viterbi Decoder"] +pub type VIT_FORCE_PU_R = crate::BitReader; +#[doc = "Field `VIT_FORCE_PU` writer - Force Power Up for Viterbi Decoder"] +pub type VIT_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_ROT_FORCE_PD` reader - Force Power Down for RX Rotation"] +pub type RX_ROT_FORCE_PD_R = crate::BitReader; +#[doc = "Field `RX_ROT_FORCE_PD` writer - Force Power Down for RX Rotation"] +pub type RX_ROT_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_ROT_FORCE_PU` reader - Force Power Up for RX Rotation"] +pub type RX_ROT_FORCE_PU_R = crate::BitReader; +#[doc = "Field `RX_ROT_FORCE_PU` writer - Force Power Up for RX Rotation"] +pub type RX_ROT_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CHAN_EST_FORCE_PD` reader - Force Power Down for Channel Estimation"] +pub type CHAN_EST_FORCE_PD_R = crate::BitReader; +#[doc = "Field `CHAN_EST_FORCE_PD` writer - Force Power Down for Channel Estimation"] +pub type CHAN_EST_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CHAN_EST_FORCE_PU` reader - Force Power Up for Channel Estimation"] +pub type CHAN_EST_FORCE_PU_R = crate::BitReader; +#[doc = "Field `CHAN_EST_FORCE_PU` writer - Force Power Up for Channel Estimation"] +pub type CHAN_EST_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Force Power Down for Demapper"] + #[inline(always)] + pub fn demap_force_pd(&self) -> DEMAP_FORCE_PD_R { + DEMAP_FORCE_PD_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Force Power Up for Demapper"] + #[inline(always)] + pub fn demap_force_pu(&self) -> DEMAP_FORCE_PU_R { + DEMAP_FORCE_PU_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Force Power Down for Viterbi Decoder"] + #[inline(always)] + pub fn vit_force_pd(&self) -> VIT_FORCE_PD_R { + VIT_FORCE_PD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Force Power Up for Viterbi Decoder"] + #[inline(always)] + pub fn vit_force_pu(&self) -> VIT_FORCE_PU_R { + VIT_FORCE_PU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Force Power Down for RX Rotation"] + #[inline(always)] + pub fn rx_rot_force_pd(&self) -> RX_ROT_FORCE_PD_R { + RX_ROT_FORCE_PD_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Force Power Up for RX Rotation"] + #[inline(always)] + pub fn rx_rot_force_pu(&self) -> RX_ROT_FORCE_PU_R { + RX_ROT_FORCE_PU_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Force Power Down for Channel Estimation"] + #[inline(always)] + pub fn chan_est_force_pd(&self) -> CHAN_EST_FORCE_PD_R { + CHAN_EST_FORCE_PD_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Force Power Up for Channel Estimation"] + #[inline(always)] + pub fn chan_est_force_pu(&self) -> CHAN_EST_FORCE_PU_R { + CHAN_EST_FORCE_PU_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("NRXPD_CTRL") + .field("chan_est_force_pu", &self.chan_est_force_pu()) + .field("chan_est_force_pd", &self.chan_est_force_pd()) + .field("rx_rot_force_pu", &self.rx_rot_force_pu()) + .field("rx_rot_force_pd", &self.rx_rot_force_pd()) + .field("vit_force_pu", &self.vit_force_pu()) + .field("vit_force_pd", &self.vit_force_pd()) + .field("demap_force_pu", &self.demap_force_pu()) + .field("demap_force_pd", &self.demap_force_pd()) + .finish() + } +} +impl W { + #[doc = "Bit 0 - Force Power Down for Demapper"] + #[inline(always)] + #[must_use] + pub fn demap_force_pd(&mut self) -> DEMAP_FORCE_PD_W { + DEMAP_FORCE_PD_W::new(self, 0) + } + #[doc = "Bit 1 - Force Power Up for Demapper"] + #[inline(always)] + #[must_use] + pub fn demap_force_pu(&mut self) -> DEMAP_FORCE_PU_W { + DEMAP_FORCE_PU_W::new(self, 1) + } + #[doc = "Bit 2 - Force Power Down for Viterbi Decoder"] + #[inline(always)] + #[must_use] + pub fn vit_force_pd(&mut self) -> VIT_FORCE_PD_W { + VIT_FORCE_PD_W::new(self, 2) + } + #[doc = "Bit 3 - Force Power Up for Viterbi Decoder"] + #[inline(always)] + #[must_use] + pub fn vit_force_pu(&mut self) -> VIT_FORCE_PU_W { + VIT_FORCE_PU_W::new(self, 3) + } + #[doc = "Bit 4 - Force Power Down for RX Rotation"] + #[inline(always)] + #[must_use] + pub fn rx_rot_force_pd(&mut self) -> RX_ROT_FORCE_PD_W { + RX_ROT_FORCE_PD_W::new(self, 4) + } + #[doc = "Bit 5 - Force Power Up for RX Rotation"] + #[inline(always)] + #[must_use] + pub fn rx_rot_force_pu(&mut self) -> RX_ROT_FORCE_PU_W { + RX_ROT_FORCE_PU_W::new(self, 5) + } + #[doc = "Bit 6 - Force Power Down for Channel Estimation"] + #[inline(always)] + #[must_use] + pub fn chan_est_force_pd(&mut self) -> CHAN_EST_FORCE_PD_W { + CHAN_EST_FORCE_PD_W::new(self, 6) + } + #[doc = "Bit 7 - Force Power Up for Channel Estimation"] + #[inline(always)] + #[must_use] + pub fn chan_est_force_pu(&mut self) -> CHAN_EST_FORCE_PU_W { + CHAN_EST_FORCE_PU_W::new(self, 7) + } +} +#[doc = "NRX Power Down Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`nrxpd_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nrxpd_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NRXPD_CTRL_SPEC; +impl crate::RegisterSpec for NRXPD_CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`nrxpd_ctrl::R`](R) reader structure"] +impl crate::Readable for NRXPD_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nrxpd_ctrl::W`](W) writer structure"] +impl crate::Writable for NRXPD_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0; +} +#[doc = "`reset()` method sets NRXPD_CTRL to value 0"] +impl crate::Resettable for NRXPD_CTRL_SPEC { + const RESET_VALUE: u8 = 0; +} diff --git a/esp32c3/svd/patches/esp32c3.yaml b/esp32c3/svd/patches/esp32c3.yaml index 4e58dfe841..894ef6454d 100644 --- a/esp32c3/svd/patches/esp32c3.yaml +++ b/esp32c3/svd/patches/esp32c3.yaml @@ -1,5 +1,113 @@ _svd: ../esp32c3.base.svd +_add: + NRX: + description: NRX Peripheral + baseAddress: 0x6001CC00 + groupName: NRX + addressBlock: + offset: 0x0 + size: 0x4 + usage: registers + registers: + NRXPD_CTRL: + description: "NRX Power Down Control Register" + addressOffset: 0xD4 + size: 0x4 + access: read-write + fields: + CHAN_EST_FORCE_PU: + description: "Force Power Up for Channel Estimation" + bitOffset: 7 + bitWidth: 1 + access: read-write + CHAN_EST_FORCE_PD: + description: "Force Power Down for Channel Estimation" + bitOffset: 6 + bitWidth: 1 + access: read-write + RX_ROT_FORCE_PU: + description: "Force Power Up for RX Rotation" + bitOffset: 5 + bitWidth: 1 + access: read-write + RX_ROT_FORCE_PD: + description: "Force Power Down for RX Rotation" + bitOffset: 4 + bitWidth: 1 + access: read-write + VIT_FORCE_PU: + description: "Force Power Up for Viterbi Decoder" + bitOffset: 3 + bitWidth: 1 + access: read-write + VIT_FORCE_PD: + description: "Force Power Down for Viterbi Decoder" + bitOffset: 2 + bitWidth: 1 + access: read-write + DEMAP_FORCE_PU: + description: "Force Power Up for Demapper" + bitOffset: 1 + bitWidth: 1 + access: read-write + DEMAP_FORCE_PD: + description: "Force Power Down for Demapper" + bitOffset: 0 + bitWidth: 1 + access: read-write + FE: + description: need des + baseAddress: 0x60006000 + groupName: FE + addressBlock: + offset: 0x0 + size: 0x4 + usage: registers + registers: + GEN_CTRL: + description: "FE General Control Register" + addressOffset: 0x0090 + size: 0x2 + access: read-write + fields: + IQ_EST_FORCE_PU: + description: "Force Power Up for IQ Estimation" + bitOffset: 5 + bitWidth: 1 + access: read-write + IQ_EST_FORCE_PD: + description: "Force Power Down for IQ Estimation" + bitOffset: 4 + bitWidth: 1 + access: read-write + FE2: + description: need des + baseAddress: 0x60005000 + groupName: FE + addressBlock: + offset: 0x0 + size: 0x4 + usage: registers + registers: + TX_INTERP_CTRL: + description: "FE2 TX Interpolation Control Register" + addressOffset: 0x00f0 + size: 0x20 + access: read-write + fields: + TX_INF_FORCE_PU: + description: "Force Power Up field" + bitOffset: 10 + bitWidth: 1 + access: read-write + TX_INF_FORCE_PD: + description: "Force Power Down field" + bitOffset: 9 + bitWidth: 1 + access: read-write + + _modify: SPI?: groupName: SPI diff --git a/esp32c6/src/lib.rs b/esp32c6/src/lib.rs index fd71ba76d8..c4bb525d62 100644 --- a/esp32c6/src/lib.rs +++ b/esp32c6/src/lib.rs @@ -3247,6 +3247,98 @@ impl core::fmt::Debug for USB_DEVICE { } #[doc = "Full-speed USB Serial/JTAG Controller"] pub mod usb_device; +#[doc = "PLIC Peripheral"] +pub struct PLIC_MX { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PLIC_MX {} +impl PLIC_MX { + #[doc = r"Pointer to the register block"] + pub const PTR: *const plic_mx::RegisterBlock = 0x2000_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const plic_mx::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PLIC_MX { + type Target = plic_mx::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PLIC_MX { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PLIC_MX").finish() + } +} +#[doc = "PLIC Peripheral"] +pub mod plic_mx; +#[doc = "PLIC Peripheral"] +pub struct PLIC_UX { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PLIC_UX {} +impl PLIC_UX { + #[doc = r"Pointer to the register block"] + pub const PTR: *const plic_ux::RegisterBlock = 0x2000_1400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const plic_ux::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PLIC_UX { + type Target = plic_ux::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PLIC_UX { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PLIC_UX").finish() + } +} +#[doc = "PLIC Peripheral"] +pub mod plic_ux; #[no_mangle] static mut DEVICE_PERIPHERALS: bool = false; #[doc = r" All the peripherals."] @@ -3382,6 +3474,10 @@ pub struct Peripherals { pub UHCI0: UHCI0, #[doc = "USB_DEVICE"] pub USB_DEVICE: USB_DEVICE, + #[doc = "PLIC_MX"] + pub PLIC_MX: PLIC_MX, + #[doc = "PLIC_UX"] + pub PLIC_UX: PLIC_UX, } impl Peripherals { #[doc = r" Returns all the peripherals *once*."] @@ -3469,6 +3565,8 @@ impl Peripherals { UART1: UART1::steal(), UHCI0: UHCI0::steal(), USB_DEVICE: USB_DEVICE::steal(), + PLIC_MX: PLIC_MX::steal(), + PLIC_UX: PLIC_UX::steal(), } } } diff --git a/esp32c6/src/plic_mx.rs b/esp32c6/src/plic_mx.rs new file mode 100644 index 0000000000..7958897250 --- /dev/null +++ b/esp32c6/src/plic_mx.rs @@ -0,0 +1,258 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "Register block"] +pub struct RegisterBlock { + mxint_enable: MXINT_ENABLE, + mxint_type: MXINT_TYPE, + mxint_clear: MXINT_CLEAR, + emip_status: EMIP_STATUS, + mxint_pri: (), + _reserved5: [u8; 0x80], + mxint_thresh: MXINT_THRESH, + mxint_claim: MXINT_CLAIM, +} +impl RegisterBlock { + #[doc = "0x00 - PLIC MX Interrupt Enable Register"] + #[inline(always)] + pub const fn mxint_enable(&self) -> &MXINT_ENABLE { + &self.mxint_enable + } + #[doc = "0x04 - PLIC MX Interrupt Type Register"] + #[inline(always)] + pub const fn mxint_type(&self) -> &MXINT_TYPE { + &self.mxint_type + } + #[doc = "0x08 - PLIC MX Interrupt Clear Register"] + #[inline(always)] + pub const fn mxint_clear(&self) -> &MXINT_CLEAR { + &self.mxint_clear + } + #[doc = "0x0c - PLIC EMIP Status Register"] + #[inline(always)] + pub const fn emip_status(&self) -> &EMIP_STATUS { + &self.emip_status + } + #[doc = "0x10..0x90 - PLIC MX Interrupt %s Priority Register"] + #[inline(always)] + pub const fn mxint_pri(&self, n: usize) -> &MXINT_PRI { + #[allow(clippy::no_effect)] + [(); 32][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(16) + .add(32 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x10..0x90 - PLIC MX Interrupt %s Priority Register"] + #[inline(always)] + pub fn mxint_pri_iter(&self) -> impl Iterator { + (0..32).map(move |n| unsafe { + &*(self as *const Self) + .cast::() + .add(16) + .add(32 * n) + .cast() + }) + } + #[doc = "0x10 - PLIC MX Interrupt 0 Priority Register"] + #[inline(always)] + pub const fn mxint0_pri(&self) -> &MXINT_PRI { + self.mxint_pri(0) + } + #[doc = "0x30 - PLIC MX Interrupt 1 Priority Register"] + #[inline(always)] + pub const fn mxint1_pri(&self) -> &MXINT_PRI { + self.mxint_pri(1) + } + #[doc = "0x50 - PLIC MX Interrupt 2 Priority Register"] + #[inline(always)] + pub const fn mxint2_pri(&self) -> &MXINT_PRI { + self.mxint_pri(2) + } + #[doc = "0x70 - PLIC MX Interrupt 3 Priority Register"] + #[inline(always)] + pub const fn mxint3_pri(&self) -> &MXINT_PRI { + self.mxint_pri(3) + } + #[doc = "0x90 - PLIC MX Interrupt 4 Priority Register"] + #[inline(always)] + pub const fn mxint4_pri(&self) -> &MXINT_PRI { + self.mxint_pri(4) + } + #[doc = "0xb0 - PLIC MX Interrupt 5 Priority Register"] + #[inline(always)] + pub const fn mxint5_pri(&self) -> &MXINT_PRI { + self.mxint_pri(5) + } + #[doc = "0xd0 - PLIC MX Interrupt 6 Priority Register"] + #[inline(always)] + pub const fn mxint6_pri(&self) -> &MXINT_PRI { + self.mxint_pri(6) + } + #[doc = "0xf0 - PLIC MX Interrupt 7 Priority Register"] + #[inline(always)] + pub const fn mxint7_pri(&self) -> &MXINT_PRI { + self.mxint_pri(7) + } + #[doc = "0x110 - PLIC MX Interrupt 8 Priority Register"] + #[inline(always)] + pub const fn mxint8_pri(&self) -> &MXINT_PRI { + self.mxint_pri(8) + } + #[doc = "0x130 - PLIC MX Interrupt 9 Priority Register"] + #[inline(always)] + pub const fn mxint9_pri(&self) -> &MXINT_PRI { + self.mxint_pri(9) + } + #[doc = "0x150 - PLIC MX Interrupt 10 Priority Register"] + #[inline(always)] + pub const fn mxint10_pri(&self) -> &MXINT_PRI { + self.mxint_pri(10) + } + #[doc = "0x170 - PLIC MX Interrupt 11 Priority Register"] + #[inline(always)] + pub const fn mxint11_pri(&self) -> &MXINT_PRI { + self.mxint_pri(11) + } + #[doc = "0x190 - PLIC MX Interrupt 12 Priority Register"] + #[inline(always)] + pub const fn mxint12_pri(&self) -> &MXINT_PRI { + self.mxint_pri(12) + } + #[doc = "0x1b0 - PLIC MX Interrupt 13 Priority Register"] + #[inline(always)] + pub const fn mxint13_pri(&self) -> &MXINT_PRI { + self.mxint_pri(13) + } + #[doc = "0x1d0 - PLIC MX Interrupt 14 Priority Register"] + #[inline(always)] + pub const fn mxint14_pri(&self) -> &MXINT_PRI { + self.mxint_pri(14) + } + #[doc = "0x1f0 - PLIC MX Interrupt 15 Priority Register"] + #[inline(always)] + pub const fn mxint15_pri(&self) -> &MXINT_PRI { + self.mxint_pri(15) + } + #[doc = "0x210 - PLIC MX Interrupt 16 Priority Register"] + #[inline(always)] + pub const fn mxint16_pri(&self) -> &MXINT_PRI { + self.mxint_pri(16) + } + #[doc = "0x230 - PLIC MX Interrupt 17 Priority Register"] + #[inline(always)] + pub const fn mxint17_pri(&self) -> &MXINT_PRI { + self.mxint_pri(17) + } + #[doc = "0x250 - PLIC MX Interrupt 18 Priority Register"] + #[inline(always)] + pub const fn mxint18_pri(&self) -> &MXINT_PRI { + self.mxint_pri(18) + } + #[doc = "0x270 - PLIC MX Interrupt 19 Priority Register"] + #[inline(always)] + pub const fn mxint19_pri(&self) -> &MXINT_PRI { + self.mxint_pri(19) + } + #[doc = "0x290 - PLIC MX Interrupt 20 Priority Register"] + #[inline(always)] + pub const fn mxint20_pri(&self) -> &MXINT_PRI { + self.mxint_pri(20) + } + #[doc = "0x2b0 - PLIC MX Interrupt 21 Priority Register"] + #[inline(always)] + pub const fn mxint21_pri(&self) -> &MXINT_PRI { + self.mxint_pri(21) + } + #[doc = "0x2d0 - PLIC MX Interrupt 22 Priority Register"] + #[inline(always)] + pub const fn mxint22_pri(&self) -> &MXINT_PRI { + self.mxint_pri(22) + } + #[doc = "0x2f0 - PLIC MX Interrupt 23 Priority Register"] + #[inline(always)] + pub const fn mxint23_pri(&self) -> &MXINT_PRI { + self.mxint_pri(23) + } + #[doc = "0x310 - PLIC MX Interrupt 24 Priority Register"] + #[inline(always)] + pub const fn mxint24_pri(&self) -> &MXINT_PRI { + self.mxint_pri(24) + } + #[doc = "0x330 - PLIC MX Interrupt 25 Priority Register"] + #[inline(always)] + pub const fn mxint25_pri(&self) -> &MXINT_PRI { + self.mxint_pri(25) + } + #[doc = "0x350 - PLIC MX Interrupt 26 Priority Register"] + #[inline(always)] + pub const fn mxint26_pri(&self) -> &MXINT_PRI { + self.mxint_pri(26) + } + #[doc = "0x370 - PLIC MX Interrupt 27 Priority Register"] + #[inline(always)] + pub const fn mxint27_pri(&self) -> &MXINT_PRI { + self.mxint_pri(27) + } + #[doc = "0x390 - PLIC MX Interrupt 28 Priority Register"] + #[inline(always)] + pub const fn mxint28_pri(&self) -> &MXINT_PRI { + self.mxint_pri(28) + } + #[doc = "0x3b0 - PLIC MX Interrupt 29 Priority Register"] + #[inline(always)] + pub const fn mxint29_pri(&self) -> &MXINT_PRI { + self.mxint_pri(29) + } + #[doc = "0x3d0 - PLIC MX Interrupt 30 Priority Register"] + #[inline(always)] + pub const fn mxint30_pri(&self) -> &MXINT_PRI { + self.mxint_pri(30) + } + #[doc = "0x3f0 - PLIC MX Interrupt 31 Priority Register"] + #[inline(always)] + pub const fn mxint31_pri(&self) -> &MXINT_PRI { + self.mxint_pri(31) + } + #[doc = "0x90 - PLIC MX Interrupt Threshold Register"] + #[inline(always)] + pub const fn mxint_thresh(&self) -> &MXINT_THRESH { + &self.mxint_thresh + } + #[doc = "0x94 - PLIC MX Interrupt Claim Register"] + #[inline(always)] + pub const fn mxint_claim(&self) -> &MXINT_CLAIM { + &self.mxint_claim + } +} +#[doc = "MXINT_ENABLE (rw) register accessor: PLIC MX Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mxint_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mxint_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mxint_enable`] module"] +pub type MXINT_ENABLE = crate::Reg; +#[doc = "PLIC MX Interrupt Enable Register"] +pub mod mxint_enable; +#[doc = "MXINT_TYPE (rw) register accessor: PLIC MX Interrupt Type Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mxint_type::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mxint_type::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mxint_type`] module"] +pub type MXINT_TYPE = crate::Reg; +#[doc = "PLIC MX Interrupt Type Register"] +pub mod mxint_type; +#[doc = "MXINT_CLEAR (rw) register accessor: PLIC MX Interrupt Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mxint_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mxint_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mxint_clear`] module"] +pub type MXINT_CLEAR = crate::Reg; +#[doc = "PLIC MX Interrupt Clear Register"] +pub mod mxint_clear; +#[doc = "EMIP_STATUS (r) register accessor: PLIC EMIP Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`emip_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emip_status`] module"] +pub type EMIP_STATUS = crate::Reg; +#[doc = "PLIC EMIP Status Register"] +pub mod emip_status; +#[doc = "MXINT_PRI (rw) register accessor: PLIC MX Interrupt %s Priority Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mxint_pri::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mxint_pri::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mxint_pri`] module"] +pub type MXINT_PRI = crate::Reg; +#[doc = "PLIC MX Interrupt %s Priority Register"] +pub mod mxint_pri; +#[doc = "MXINT_THRESH (rw) register accessor: PLIC MX Interrupt Threshold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mxint_thresh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mxint_thresh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mxint_thresh`] module"] +pub type MXINT_THRESH = crate::Reg; +#[doc = "PLIC MX Interrupt Threshold Register"] +pub mod mxint_thresh; +#[doc = "MXINT_CLAIM (rw) register accessor: PLIC MX Interrupt Claim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mxint_claim::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mxint_claim::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mxint_claim`] module"] +pub type MXINT_CLAIM = crate::Reg; +#[doc = "PLIC MX Interrupt Claim Register"] +pub mod mxint_claim; diff --git a/esp32c6/src/plic_mx/emip_status.rs b/esp32c6/src/plic_mx/emip_status.rs new file mode 100644 index 0000000000..dba2f6d9ab --- /dev/null +++ b/esp32c6/src/plic_mx/emip_status.rs @@ -0,0 +1,30 @@ +#[doc = "Register `EMIP_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `CPU_EIP_STATUS` reader - "] +pub type CPU_EIP_STATUS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn cpu_eip_status(&self) -> CPU_EIP_STATUS_R { + CPU_EIP_STATUS_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EMIP_STATUS") + .field("cpu_eip_status", &self.cpu_eip_status()) + .finish() + } +} +#[doc = "PLIC EMIP Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`emip_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EMIP_STATUS_SPEC; +impl crate::RegisterSpec for EMIP_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`emip_status::R`](R) reader structure"] +impl crate::Readable for EMIP_STATUS_SPEC {} +#[doc = "`reset()` method sets EMIP_STATUS to value 0"] +impl crate::Resettable for EMIP_STATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/plic_mx/mxint_claim.rs b/esp32c6/src/plic_mx/mxint_claim.rs new file mode 100644 index 0000000000..b206880f66 --- /dev/null +++ b/esp32c6/src/plic_mx/mxint_claim.rs @@ -0,0 +1,48 @@ +#[doc = "Register `MXINT_CLAIM` reader"] +pub type R = crate::R; +#[doc = "Register `MXINT_CLAIM` writer"] +pub type W = crate::W; +#[doc = "Field `CPU_MXINT_CLAIM` reader - hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag."] +pub type CPU_MXINT_CLAIM_R = crate::FieldReader; +#[doc = "Field `CPU_MXINT_CLAIM` writer - hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag."] +pub type CPU_MXINT_CLAIM_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag."] + #[inline(always)] + pub fn cpu_mxint_claim(&self) -> CPU_MXINT_CLAIM_R { + CPU_MXINT_CLAIM_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MXINT_CLAIM") + .field("cpu_mxint_claim", &self.cpu_mxint_claim()) + .finish() + } +} +impl W { + #[doc = "Bits 0:31 - hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag."] + #[inline(always)] + #[must_use] + pub fn cpu_mxint_claim(&mut self) -> CPU_MXINT_CLAIM_W { + CPU_MXINT_CLAIM_W::new(self, 0) + } +} +#[doc = "PLIC MX Interrupt Claim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mxint_claim::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mxint_claim::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MXINT_CLAIM_SPEC; +impl crate::RegisterSpec for MXINT_CLAIM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mxint_claim::R`](R) reader structure"] +impl crate::Readable for MXINT_CLAIM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mxint_claim::W`](W) writer structure"] +impl crate::Writable for MXINT_CLAIM_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MXINT_CLAIM to value 0"] +impl crate::Resettable for MXINT_CLAIM_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/plic_mx/mxint_clear.rs b/esp32c6/src/plic_mx/mxint_clear.rs new file mode 100644 index 0000000000..90c63b5bdd --- /dev/null +++ b/esp32c6/src/plic_mx/mxint_clear.rs @@ -0,0 +1,48 @@ +#[doc = "Register `MXINT_CLEAR` reader"] +pub type R = crate::R; +#[doc = "Register `MXINT_CLEAR` writer"] +pub type W = crate::W; +#[doc = "Field `CPU_MXINT_CLEAR` reader - "] +pub type CPU_MXINT_CLEAR_R = crate::FieldReader; +#[doc = "Field `CPU_MXINT_CLEAR` writer - "] +pub type CPU_MXINT_CLEAR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn cpu_mxint_clear(&self) -> CPU_MXINT_CLEAR_R { + CPU_MXINT_CLEAR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MXINT_CLEAR") + .field("cpu_mxint_clear", &self.cpu_mxint_clear()) + .finish() + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn cpu_mxint_clear(&mut self) -> CPU_MXINT_CLEAR_W { + CPU_MXINT_CLEAR_W::new(self, 0) + } +} +#[doc = "PLIC MX Interrupt Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mxint_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mxint_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MXINT_CLEAR_SPEC; +impl crate::RegisterSpec for MXINT_CLEAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mxint_clear::R`](R) reader structure"] +impl crate::Readable for MXINT_CLEAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mxint_clear::W`](W) writer structure"] +impl crate::Writable for MXINT_CLEAR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MXINT_CLEAR to value 0"] +impl crate::Resettable for MXINT_CLEAR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/plic_mx/mxint_enable.rs b/esp32c6/src/plic_mx/mxint_enable.rs new file mode 100644 index 0000000000..281b4e37b9 --- /dev/null +++ b/esp32c6/src/plic_mx/mxint_enable.rs @@ -0,0 +1,48 @@ +#[doc = "Register `MXINT_ENABLE` reader"] +pub type R = crate::R; +#[doc = "Register `MXINT_ENABLE` writer"] +pub type W = crate::W; +#[doc = "Field `CPU_MXINT_ENABLE` reader - "] +pub type CPU_MXINT_ENABLE_R = crate::FieldReader; +#[doc = "Field `CPU_MXINT_ENABLE` writer - "] +pub type CPU_MXINT_ENABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn cpu_mxint_enable(&self) -> CPU_MXINT_ENABLE_R { + CPU_MXINT_ENABLE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MXINT_ENABLE") + .field("cpu_mxint_enable", &self.cpu_mxint_enable()) + .finish() + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn cpu_mxint_enable(&mut self) -> CPU_MXINT_ENABLE_W { + CPU_MXINT_ENABLE_W::new(self, 0) + } +} +#[doc = "PLIC MX Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mxint_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mxint_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MXINT_ENABLE_SPEC; +impl crate::RegisterSpec for MXINT_ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mxint_enable::R`](R) reader structure"] +impl crate::Readable for MXINT_ENABLE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mxint_enable::W`](W) writer structure"] +impl crate::Writable for MXINT_ENABLE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MXINT_ENABLE to value 0"] +impl crate::Resettable for MXINT_ENABLE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/plic_mx/mxint_pri.rs b/esp32c6/src/plic_mx/mxint_pri.rs new file mode 100644 index 0000000000..abea8833cb --- /dev/null +++ b/esp32c6/src/plic_mx/mxint_pri.rs @@ -0,0 +1,48 @@ +#[doc = "Register `MXINT%s_PRI` reader"] +pub type R = crate::R; +#[doc = "Register `MXINT%s_PRI` writer"] +pub type W = crate::W; +#[doc = "Field `CPU_MXINT_PRI` reader - "] +pub type CPU_MXINT_PRI_R = crate::FieldReader; +#[doc = "Field `CPU_MXINT_PRI` writer - "] +pub type CPU_MXINT_PRI_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3"] + #[inline(always)] + pub fn cpu_mxint_pri(&self) -> CPU_MXINT_PRI_R { + CPU_MXINT_PRI_R::new((self.bits & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MXINT_PRI") + .field("cpu_mxint_pri", &self.cpu_mxint_pri()) + .finish() + } +} +impl W { + #[doc = "Bits 0:3"] + #[inline(always)] + #[must_use] + pub fn cpu_mxint_pri(&mut self) -> CPU_MXINT_PRI_W { + CPU_MXINT_PRI_W::new(self, 0) + } +} +#[doc = "PLIC MX Interrupt %s Priority Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mxint_pri::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mxint_pri::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MXINT_PRI_SPEC; +impl crate::RegisterSpec for MXINT_PRI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mxint_pri::R`](R) reader structure"] +impl crate::Readable for MXINT_PRI_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mxint_pri::W`](W) writer structure"] +impl crate::Writable for MXINT_PRI_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MXINT%s_PRI to value 0"] +impl crate::Resettable for MXINT_PRI_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/plic_mx/mxint_thresh.rs b/esp32c6/src/plic_mx/mxint_thresh.rs new file mode 100644 index 0000000000..513db39cdc --- /dev/null +++ b/esp32c6/src/plic_mx/mxint_thresh.rs @@ -0,0 +1,48 @@ +#[doc = "Register `MXINT_THRESH` reader"] +pub type R = crate::R; +#[doc = "Register `MXINT_THRESH` writer"] +pub type W = crate::W; +#[doc = "Field `CPU_MXINT_THRESH` reader - "] +pub type CPU_MXINT_THRESH_R = crate::FieldReader; +#[doc = "Field `CPU_MXINT_THRESH` writer - "] +pub type CPU_MXINT_THRESH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn cpu_mxint_thresh(&self) -> CPU_MXINT_THRESH_R { + CPU_MXINT_THRESH_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MXINT_THRESH") + .field("cpu_mxint_thresh", &self.cpu_mxint_thresh()) + .finish() + } +} +impl W { + #[doc = "Bits 0:7"] + #[inline(always)] + #[must_use] + pub fn cpu_mxint_thresh(&mut self) -> CPU_MXINT_THRESH_W { + CPU_MXINT_THRESH_W::new(self, 0) + } +} +#[doc = "PLIC MX Interrupt Threshold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mxint_thresh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mxint_thresh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MXINT_THRESH_SPEC; +impl crate::RegisterSpec for MXINT_THRESH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mxint_thresh::R`](R) reader structure"] +impl crate::Readable for MXINT_THRESH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mxint_thresh::W`](W) writer structure"] +impl crate::Writable for MXINT_THRESH_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MXINT_THRESH to value 0"] +impl crate::Resettable for MXINT_THRESH_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/plic_mx/mxint_type.rs b/esp32c6/src/plic_mx/mxint_type.rs new file mode 100644 index 0000000000..5ad347650c --- /dev/null +++ b/esp32c6/src/plic_mx/mxint_type.rs @@ -0,0 +1,48 @@ +#[doc = "Register `MXINT_TYPE` reader"] +pub type R = crate::R; +#[doc = "Register `MXINT_TYPE` writer"] +pub type W = crate::W; +#[doc = "Field `CPU_MXINT_TYPE` reader - "] +pub type CPU_MXINT_TYPE_R = crate::FieldReader; +#[doc = "Field `CPU_MXINT_TYPE` writer - "] +pub type CPU_MXINT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn cpu_mxint_type(&self) -> CPU_MXINT_TYPE_R { + CPU_MXINT_TYPE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MXINT_TYPE") + .field("cpu_mxint_type", &self.cpu_mxint_type()) + .finish() + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn cpu_mxint_type(&mut self) -> CPU_MXINT_TYPE_W { + CPU_MXINT_TYPE_W::new(self, 0) + } +} +#[doc = "PLIC MX Interrupt Type Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mxint_type::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mxint_type::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MXINT_TYPE_SPEC; +impl crate::RegisterSpec for MXINT_TYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mxint_type::R`](R) reader structure"] +impl crate::Readable for MXINT_TYPE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mxint_type::W`](W) writer structure"] +impl crate::Writable for MXINT_TYPE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MXINT_TYPE to value 0"] +impl crate::Resettable for MXINT_TYPE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/plic_ux.rs b/esp32c6/src/plic_ux.rs new file mode 100644 index 0000000000..35b666c565 --- /dev/null +++ b/esp32c6/src/plic_ux.rs @@ -0,0 +1,248 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "Register block"] +pub struct RegisterBlock { + uxint_enable: UXINT_ENABLE, + uxint_type: UXINT_TYPE, + uxint_clear: UXINT_CLEAR, + euip_status: EUIP_STATUS, + uxint_pri: (), + _reserved5: [u8; 0x84], + uxint_thresh: UXINT_THRESH, +} +impl RegisterBlock { + #[doc = "0x00 - PLIC UX Interrupt Enable Register"] + #[inline(always)] + pub const fn uxint_enable(&self) -> &UXINT_ENABLE { + &self.uxint_enable + } + #[doc = "0x04 - PLIC UX Interrupt Type Register"] + #[inline(always)] + pub const fn uxint_type(&self) -> &UXINT_TYPE { + &self.uxint_type + } + #[doc = "0x08 - PLIC UX Interrupt Clear Register"] + #[inline(always)] + pub const fn uxint_clear(&self) -> &UXINT_CLEAR { + &self.uxint_clear + } + #[doc = "0x0c - PLIC EMIP Status Register"] + #[inline(always)] + pub const fn euip_status(&self) -> &EUIP_STATUS { + &self.euip_status + } + #[doc = "0x10..0x90 - PLIC UX Interrupt %s Priority Register"] + #[inline(always)] + pub const fn uxint_pri(&self, n: usize) -> &UXINT_PRI { + #[allow(clippy::no_effect)] + [(); 32][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(16) + .add(32 * n) + .cast() + } + } + #[doc = "Iterator for array of:"] + #[doc = "0x10..0x90 - PLIC UX Interrupt %s Priority Register"] + #[inline(always)] + pub fn uxint_pri_iter(&self) -> impl Iterator { + (0..32).map(move |n| unsafe { + &*(self as *const Self) + .cast::() + .add(16) + .add(32 * n) + .cast() + }) + } + #[doc = "0x10 - PLIC UX Interrupt 0 Priority Register"] + #[inline(always)] + pub const fn uxint0_pri(&self) -> &UXINT_PRI { + self.uxint_pri(0) + } + #[doc = "0x30 - PLIC UX Interrupt 1 Priority Register"] + #[inline(always)] + pub const fn uxint1_pri(&self) -> &UXINT_PRI { + self.uxint_pri(1) + } + #[doc = "0x50 - PLIC UX Interrupt 2 Priority Register"] + #[inline(always)] + pub const fn uxint2_pri(&self) -> &UXINT_PRI { + self.uxint_pri(2) + } + #[doc = "0x70 - PLIC UX Interrupt 3 Priority Register"] + #[inline(always)] + pub const fn uxint3_pri(&self) -> &UXINT_PRI { + self.uxint_pri(3) + } + #[doc = "0x90 - PLIC UX Interrupt 4 Priority Register"] + #[inline(always)] + pub const fn uxint4_pri(&self) -> &UXINT_PRI { + self.uxint_pri(4) + } + #[doc = "0xb0 - PLIC UX Interrupt 5 Priority Register"] + #[inline(always)] + pub const fn uxint5_pri(&self) -> &UXINT_PRI { + self.uxint_pri(5) + } + #[doc = "0xd0 - PLIC UX Interrupt 6 Priority Register"] + #[inline(always)] + pub const fn uxint6_pri(&self) -> &UXINT_PRI { + self.uxint_pri(6) + } + #[doc = "0xf0 - PLIC UX Interrupt 7 Priority Register"] + #[inline(always)] + pub const fn uxint7_pri(&self) -> &UXINT_PRI { + self.uxint_pri(7) + } + #[doc = "0x110 - PLIC UX Interrupt 8 Priority Register"] + #[inline(always)] + pub const fn uxint8_pri(&self) -> &UXINT_PRI { + self.uxint_pri(8) + } + #[doc = "0x130 - PLIC UX Interrupt 9 Priority Register"] + #[inline(always)] + pub const fn uxint9_pri(&self) -> &UXINT_PRI { + self.uxint_pri(9) + } + #[doc = "0x150 - PLIC UX Interrupt 10 Priority Register"] + #[inline(always)] + pub const fn uxint10_pri(&self) -> &UXINT_PRI { + self.uxint_pri(10) + } + #[doc = "0x170 - PLIC UX Interrupt 11 Priority Register"] + #[inline(always)] + pub const fn uxint11_pri(&self) -> &UXINT_PRI { + self.uxint_pri(11) + } + #[doc = "0x190 - PLIC UX Interrupt 12 Priority Register"] + #[inline(always)] + pub const fn uxint12_pri(&self) -> &UXINT_PRI { + self.uxint_pri(12) + } + #[doc = "0x1b0 - PLIC UX Interrupt 13 Priority Register"] + #[inline(always)] + pub const fn uxint13_pri(&self) -> &UXINT_PRI { + self.uxint_pri(13) + } + #[doc = "0x1d0 - PLIC UX Interrupt 14 Priority Register"] + #[inline(always)] + pub const fn uxint14_pri(&self) -> &UXINT_PRI { + self.uxint_pri(14) + } + #[doc = "0x1f0 - PLIC UX Interrupt 15 Priority Register"] + #[inline(always)] + pub const fn uxint15_pri(&self) -> &UXINT_PRI { + self.uxint_pri(15) + } + #[doc = "0x210 - PLIC UX Interrupt 16 Priority Register"] + #[inline(always)] + pub const fn uxint16_pri(&self) -> &UXINT_PRI { + self.uxint_pri(16) + } + #[doc = "0x230 - PLIC UX Interrupt 17 Priority Register"] + #[inline(always)] + pub const fn uxint17_pri(&self) -> &UXINT_PRI { + self.uxint_pri(17) + } + #[doc = "0x250 - PLIC UX Interrupt 18 Priority Register"] + #[inline(always)] + pub const fn uxint18_pri(&self) -> &UXINT_PRI { + self.uxint_pri(18) + } + #[doc = "0x270 - PLIC UX Interrupt 19 Priority Register"] + #[inline(always)] + pub const fn uxint19_pri(&self) -> &UXINT_PRI { + self.uxint_pri(19) + } + #[doc = "0x290 - PLIC UX Interrupt 20 Priority Register"] + #[inline(always)] + pub const fn uxint20_pri(&self) -> &UXINT_PRI { + self.uxint_pri(20) + } + #[doc = "0x2b0 - PLIC UX Interrupt 21 Priority Register"] + #[inline(always)] + pub const fn uxint21_pri(&self) -> &UXINT_PRI { + self.uxint_pri(21) + } + #[doc = "0x2d0 - PLIC UX Interrupt 22 Priority Register"] + #[inline(always)] + pub const fn uxint22_pri(&self) -> &UXINT_PRI { + self.uxint_pri(22) + } + #[doc = "0x2f0 - PLIC UX Interrupt 23 Priority Register"] + #[inline(always)] + pub const fn uxint23_pri(&self) -> &UXINT_PRI { + self.uxint_pri(23) + } + #[doc = "0x310 - PLIC UX Interrupt 24 Priority Register"] + #[inline(always)] + pub const fn uxint24_pri(&self) -> &UXINT_PRI { + self.uxint_pri(24) + } + #[doc = "0x330 - PLIC UX Interrupt 25 Priority Register"] + #[inline(always)] + pub const fn uxint25_pri(&self) -> &UXINT_PRI { + self.uxint_pri(25) + } + #[doc = "0x350 - PLIC UX Interrupt 26 Priority Register"] + #[inline(always)] + pub const fn uxint26_pri(&self) -> &UXINT_PRI { + self.uxint_pri(26) + } + #[doc = "0x370 - PLIC UX Interrupt 27 Priority Register"] + #[inline(always)] + pub const fn uxint27_pri(&self) -> &UXINT_PRI { + self.uxint_pri(27) + } + #[doc = "0x390 - PLIC UX Interrupt 28 Priority Register"] + #[inline(always)] + pub const fn uxint28_pri(&self) -> &UXINT_PRI { + self.uxint_pri(28) + } + #[doc = "0x3b0 - PLIC UX Interrupt 29 Priority Register"] + #[inline(always)] + pub const fn uxint29_pri(&self) -> &UXINT_PRI { + self.uxint_pri(29) + } + #[doc = "0x3d0 - PLIC UX Interrupt 30 Priority Register"] + #[inline(always)] + pub const fn uxint30_pri(&self) -> &UXINT_PRI { + self.uxint_pri(30) + } + #[doc = "0x3f0 - PLIC UX Interrupt 31 Priority Register"] + #[inline(always)] + pub const fn uxint31_pri(&self) -> &UXINT_PRI { + self.uxint_pri(31) + } + #[doc = "0x94 - PLIC UX Interrupt Claim Register"] + #[inline(always)] + pub const fn uxint_thresh(&self) -> &UXINT_THRESH { + &self.uxint_thresh + } +} +#[doc = "UXINT_ENABLE (rw) register accessor: PLIC UX Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uxint_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uxint_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uxint_enable`] module"] +pub type UXINT_ENABLE = crate::Reg; +#[doc = "PLIC UX Interrupt Enable Register"] +pub mod uxint_enable; +#[doc = "UXINT_TYPE (rw) register accessor: PLIC UX Interrupt Type Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uxint_type::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uxint_type::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uxint_type`] module"] +pub type UXINT_TYPE = crate::Reg; +#[doc = "PLIC UX Interrupt Type Register"] +pub mod uxint_type; +#[doc = "UXINT_CLEAR (rw) register accessor: PLIC UX Interrupt Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uxint_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uxint_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uxint_clear`] module"] +pub type UXINT_CLEAR = crate::Reg; +#[doc = "PLIC UX Interrupt Clear Register"] +pub mod uxint_clear; +#[doc = "EUIP_STATUS (r) register accessor: PLIC EMIP Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`euip_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@euip_status`] module"] +pub type EUIP_STATUS = crate::Reg; +#[doc = "PLIC EMIP Status Register"] +pub mod euip_status; +#[doc = "UXINT_PRI (rw) register accessor: PLIC UX Interrupt %s Priority Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uxint_pri::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uxint_pri::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uxint_pri`] module"] +pub type UXINT_PRI = crate::Reg; +#[doc = "PLIC UX Interrupt %s Priority Register"] +pub mod uxint_pri; +#[doc = "UXINT_THRESH (rw) register accessor: PLIC UX Interrupt Claim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uxint_thresh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uxint_thresh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uxint_thresh`] module"] +pub type UXINT_THRESH = crate::Reg; +#[doc = "PLIC UX Interrupt Claim Register"] +pub mod uxint_thresh; diff --git a/esp32c6/src/plic_ux/euip_status.rs b/esp32c6/src/plic_ux/euip_status.rs new file mode 100644 index 0000000000..7ea88f6a10 --- /dev/null +++ b/esp32c6/src/plic_ux/euip_status.rs @@ -0,0 +1,30 @@ +#[doc = "Register `EUIP_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `CPU_EIP_STATUS` reader - "] +pub type CPU_EIP_STATUS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn cpu_eip_status(&self) -> CPU_EIP_STATUS_R { + CPU_EIP_STATUS_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EUIP_STATUS") + .field("cpu_eip_status", &self.cpu_eip_status()) + .finish() + } +} +#[doc = "PLIC EMIP Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`euip_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EUIP_STATUS_SPEC; +impl crate::RegisterSpec for EUIP_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`euip_status::R`](R) reader structure"] +impl crate::Readable for EUIP_STATUS_SPEC {} +#[doc = "`reset()` method sets EUIP_STATUS to value 0"] +impl crate::Resettable for EUIP_STATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/plic_ux/uxint_clear.rs b/esp32c6/src/plic_ux/uxint_clear.rs new file mode 100644 index 0000000000..d11f236dd1 --- /dev/null +++ b/esp32c6/src/plic_ux/uxint_clear.rs @@ -0,0 +1,48 @@ +#[doc = "Register `UXINT_CLEAR` reader"] +pub type R = crate::R; +#[doc = "Register `UXINT_CLEAR` writer"] +pub type W = crate::W; +#[doc = "Field `CPU_UXINT_CLEAR` reader - "] +pub type CPU_UXINT_CLEAR_R = crate::FieldReader; +#[doc = "Field `CPU_UXINT_CLEAR` writer - "] +pub type CPU_UXINT_CLEAR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn cpu_uxint_clear(&self) -> CPU_UXINT_CLEAR_R { + CPU_UXINT_CLEAR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UXINT_CLEAR") + .field("cpu_uxint_clear", &self.cpu_uxint_clear()) + .finish() + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn cpu_uxint_clear(&mut self) -> CPU_UXINT_CLEAR_W { + CPU_UXINT_CLEAR_W::new(self, 0) + } +} +#[doc = "PLIC UX Interrupt Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uxint_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uxint_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UXINT_CLEAR_SPEC; +impl crate::RegisterSpec for UXINT_CLEAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uxint_clear::R`](R) reader structure"] +impl crate::Readable for UXINT_CLEAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uxint_clear::W`](W) writer structure"] +impl crate::Writable for UXINT_CLEAR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UXINT_CLEAR to value 0"] +impl crate::Resettable for UXINT_CLEAR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/plic_ux/uxint_enable.rs b/esp32c6/src/plic_ux/uxint_enable.rs new file mode 100644 index 0000000000..db3bf4e2df --- /dev/null +++ b/esp32c6/src/plic_ux/uxint_enable.rs @@ -0,0 +1,48 @@ +#[doc = "Register `UXINT_ENABLE` reader"] +pub type R = crate::R; +#[doc = "Register `UXINT_ENABLE` writer"] +pub type W = crate::W; +#[doc = "Field `CPU_UXINT_ENABLE` reader - "] +pub type CPU_UXINT_ENABLE_R = crate::FieldReader; +#[doc = "Field `CPU_UXINT_ENABLE` writer - "] +pub type CPU_UXINT_ENABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn cpu_uxint_enable(&self) -> CPU_UXINT_ENABLE_R { + CPU_UXINT_ENABLE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UXINT_ENABLE") + .field("cpu_uxint_enable", &self.cpu_uxint_enable()) + .finish() + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn cpu_uxint_enable(&mut self) -> CPU_UXINT_ENABLE_W { + CPU_UXINT_ENABLE_W::new(self, 0) + } +} +#[doc = "PLIC UX Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uxint_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uxint_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UXINT_ENABLE_SPEC; +impl crate::RegisterSpec for UXINT_ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uxint_enable::R`](R) reader structure"] +impl crate::Readable for UXINT_ENABLE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uxint_enable::W`](W) writer structure"] +impl crate::Writable for UXINT_ENABLE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UXINT_ENABLE to value 0"] +impl crate::Resettable for UXINT_ENABLE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/plic_ux/uxint_pri.rs b/esp32c6/src/plic_ux/uxint_pri.rs new file mode 100644 index 0000000000..977f13dfe2 --- /dev/null +++ b/esp32c6/src/plic_ux/uxint_pri.rs @@ -0,0 +1,48 @@ +#[doc = "Register `UXINT%s_PRI` reader"] +pub type R = crate::R; +#[doc = "Register `UXINT%s_PRI` writer"] +pub type W = crate::W; +#[doc = "Field `CPU_UXINT0_PRI` reader - "] +pub type CPU_UXINT0_PRI_R = crate::FieldReader; +#[doc = "Field `CPU_UXINT0_PRI` writer - "] +pub type CPU_UXINT0_PRI_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3"] + #[inline(always)] + pub fn cpu_uxint0_pri(&self) -> CPU_UXINT0_PRI_R { + CPU_UXINT0_PRI_R::new((self.bits & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UXINT_PRI") + .field("cpu_uxint0_pri", &self.cpu_uxint0_pri()) + .finish() + } +} +impl W { + #[doc = "Bits 0:3"] + #[inline(always)] + #[must_use] + pub fn cpu_uxint0_pri(&mut self) -> CPU_UXINT0_PRI_W { + CPU_UXINT0_PRI_W::new(self, 0) + } +} +#[doc = "PLIC UX Interrupt %s Priority Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uxint_pri::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uxint_pri::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UXINT_PRI_SPEC; +impl crate::RegisterSpec for UXINT_PRI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uxint_pri::R`](R) reader structure"] +impl crate::Readable for UXINT_PRI_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uxint_pri::W`](W) writer structure"] +impl crate::Writable for UXINT_PRI_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UXINT%s_PRI to value 0"] +impl crate::Resettable for UXINT_PRI_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/plic_ux/uxint_thresh.rs b/esp32c6/src/plic_ux/uxint_thresh.rs new file mode 100644 index 0000000000..04882e40bc --- /dev/null +++ b/esp32c6/src/plic_ux/uxint_thresh.rs @@ -0,0 +1,48 @@ +#[doc = "Register `UXINT_THRESH` reader"] +pub type R = crate::R; +#[doc = "Register `UXINT_THRESH` writer"] +pub type W = crate::W; +#[doc = "Field `CPU_UXINT_CLAIM` reader - hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag."] +pub type CPU_UXINT_CLAIM_R = crate::FieldReader; +#[doc = "Field `CPU_UXINT_CLAIM` writer - hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag."] +pub type CPU_UXINT_CLAIM_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag."] + #[inline(always)] + pub fn cpu_uxint_claim(&self) -> CPU_UXINT_CLAIM_R { + CPU_UXINT_CLAIM_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UXINT_THRESH") + .field("cpu_uxint_claim", &self.cpu_uxint_claim()) + .finish() + } +} +impl W { + #[doc = "Bits 0:31 - hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag."] + #[inline(always)] + #[must_use] + pub fn cpu_uxint_claim(&mut self) -> CPU_UXINT_CLAIM_W { + CPU_UXINT_CLAIM_W::new(self, 0) + } +} +#[doc = "PLIC UX Interrupt Claim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uxint_thresh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uxint_thresh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UXINT_THRESH_SPEC; +impl crate::RegisterSpec for UXINT_THRESH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uxint_thresh::R`](R) reader structure"] +impl crate::Readable for UXINT_THRESH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uxint_thresh::W`](W) writer structure"] +impl crate::Writable for UXINT_THRESH_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UXINT_THRESH to value 0"] +impl crate::Resettable for UXINT_THRESH_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/src/plic_ux/uxint_type.rs b/esp32c6/src/plic_ux/uxint_type.rs new file mode 100644 index 0000000000..36f4d6fd11 --- /dev/null +++ b/esp32c6/src/plic_ux/uxint_type.rs @@ -0,0 +1,48 @@ +#[doc = "Register `UXINT_TYPE` reader"] +pub type R = crate::R; +#[doc = "Register `UXINT_TYPE` writer"] +pub type W = crate::W; +#[doc = "Field `CPU_UXINT_TYPE` reader - "] +pub type CPU_UXINT_TYPE_R = crate::FieldReader; +#[doc = "Field `CPU_UXINT_TYPE` writer - "] +pub type CPU_UXINT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn cpu_uxint_type(&self) -> CPU_UXINT_TYPE_R { + CPU_UXINT_TYPE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UXINT_TYPE") + .field("cpu_uxint_type", &self.cpu_uxint_type()) + .finish() + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn cpu_uxint_type(&mut self) -> CPU_UXINT_TYPE_W { + CPU_UXINT_TYPE_W::new(self, 0) + } +} +#[doc = "PLIC UX Interrupt Type Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uxint_type::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uxint_type::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UXINT_TYPE_SPEC; +impl crate::RegisterSpec for UXINT_TYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uxint_type::R`](R) reader structure"] +impl crate::Readable for UXINT_TYPE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uxint_type::W`](W) writer structure"] +impl crate::Writable for UXINT_TYPE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UXINT_TYPE to value 0"] +impl crate::Resettable for UXINT_TYPE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32c6/svd/patches/esp32c6.yaml b/esp32c6/svd/patches/esp32c6.yaml index c9c70754b0..98c8724b7f 100644 --- a/esp32c6/svd/patches/esp32c6.yaml +++ b/esp32c6/svd/patches/esp32c6.yaml @@ -1,5 +1,183 @@ _svd: "../esp32c6.base.svd" +_add: + PLIC_MX: + description: PLIC Peripheral + baseAddress: 0x20001000 + groupName: PLIC + addressBlock: + offset: 0x0 + size: 0x98 + usage: registers + registers: + MXINT_ENABLE: + description: "PLIC MX Interrupt Enable Register" + addressOffset: 0x0000 + size: 32 + access: read-write + fields: + CPU_MXINT_ENABLE: + description: "" + bitOffset: 0 + bitWidth: 32 + access: read-write + MXINT_TYPE: + description: "PLIC MX Interrupt Type Register" + addressOffset: 0x0004 + size: 32 + access: read-write + fields: + CPU_MXINT_TYPE: + description: "" + bitOffset: 0 + bitWidth: 32 + access: read-write + MXINT_CLEAR: + description: "PLIC MX Interrupt Clear Register" + addressOffset: 0x0008 + size: 32 + access: read-write + fields: + CPU_MXINT_CLEAR: + description: "" + bitOffset: 0 + bitWidth: 32 + access: read-write + EMIP_STATUS: + description: "PLIC EMIP Status Register" + addressOffset: 0x000C + size: 32 + access: read-only + fields: + CPU_EIP_STATUS: + description: "" + bitOffset: 0 + bitWidth: 32 + access: read-only + MXINT%s_PRI: + dim: 32 + dimIncrement: 0x20 + description: "PLIC MX Interrupt %s Priority Register" + addressOffset: 0x0010 + size: 32 + access: read-write + fields: + CPU_MXINT_PRI: + description: "" + bitOffset: 0 + bitWidth: 4 + access: read-write + MXINT_THRESH: + description: "PLIC MX Interrupt Threshold Register" + addressOffset: 0x0090 + size: 32 + access: read-write + fields: + CPU_MXINT_THRESH: + description: "" + bitOffset: 0 + bitWidth: 8 + access: read-write + MXINT_CLAIM: + description: "PLIC MX Interrupt Claim Register" + addressOffset: 0x0094 + size: 32 + access: read-write + fields: + CPU_MXINT_CLAIM: + description: "hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag." + bitOffset: 0 + bitWidth: 32 + access: read-write + PLIC_UX: + description: PLIC Peripheral + baseAddress: 0x20001400 + groupName: PLIC + addressBlock: + offset: 0x0 + size: 0x98 + usage: registers + registers: + UXINT_ENABLE: + description: "PLIC UX Interrupt Enable Register" + addressOffset: 0x0000 + size: 32 + access: read-write + fields: + CPU_UXINT_ENABLE: + description: "" + bitOffset: 0 + bitWidth: 32 + access: read-write + UXINT_TYPE: + description: "PLIC UX Interrupt Type Register" + addressOffset: 0x0004 + size: 32 + access: read-write + fields: + CPU_UXINT_TYPE: + description: "" + bitOffset: 0 + bitWidth: 32 + access: read-write + UXINT_CLEAR: + description: "PLIC UX Interrupt Clear Register" + addressOffset: 0x0008 + size: 32 + access: read-write + fields: + CPU_UXINT_CLEAR: + description: "" + bitOffset: 0 + bitWidth: 32 + access: read-write + EUIP_STATUS: + description: "PLIC EMIP Status Register" + addressOffset: 0x000C + size: 32 + access: read-only + fields: + CPU_EIP_STATUS: + description: "" + bitOffset: 0 + bitWidth: 32 + access: read-only + UXINT%s_PRI: + dim: 32 + dimIncrement: 0x20 + description: "PLIC UX Interrupt %s Priority Register" + addressOffset: 0x0010 + size: 32 + access: read-write + fields: + CPU_UXINT0_PRI: + description: "" + bitOffset: 0 + bitWidth: 4 + access: read-write + UXINT_THRESH: + description: "PLIC UX Interrupt Threshold Register" + addressOffset: 0x0090 + size: 32 + access: read-write + fields: + CPU_UXINT_THRESH: + description: "" + bitOffset: 0 + bitWidth: 8 + access: read-write + UXINT_CLAIM: + description: "PLIC UX Interrupt Claim Register" + addressOffset: 0x0094 + size: 32 + access: read-write + fields: + CPU_UXINT_CLAIM: + description: "hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag." + bitOffset: 0 + bitWidth: 32 + access: read-write + _modify: SPI?: groupName: SPI diff --git a/esp32s3/src/fe.rs b/esp32s3/src/fe.rs new file mode 100644 index 0000000000..7249177834 --- /dev/null +++ b/esp32s3/src/fe.rs @@ -0,0 +1,18 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved0: [u8; 0x90], + gen_ctrl: GEN_CTRL, +} +impl RegisterBlock { + #[doc = "0x90 - FE General Control Register"] + #[inline(always)] + pub const fn gen_ctrl(&self) -> &GEN_CTRL { + &self.gen_ctrl + } +} +#[doc = "GEN_CTRL (rw) register accessor: FE General Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`gen_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gen_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gen_ctrl`] module"] +pub type GEN_CTRL = crate::Reg; +#[doc = "FE General Control Register"] +pub mod gen_ctrl; diff --git a/esp32s3/src/fe/gen_ctrl.rs b/esp32s3/src/fe/gen_ctrl.rs new file mode 100644 index 0000000000..b0d00836ae --- /dev/null +++ b/esp32s3/src/fe/gen_ctrl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `GEN_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `GEN_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `IQ_EST_FORCE_PD` reader - Force Power Down for IQ Estimation"] +pub type IQ_EST_FORCE_PD_R = crate::BitReader; +#[doc = "Field `IQ_EST_FORCE_PD` writer - Force Power Down for IQ Estimation"] +pub type IQ_EST_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IQ_EST_FORCE_PU` reader - Force Power Up for IQ Estimation"] +pub type IQ_EST_FORCE_PU_R = crate::BitReader; +#[doc = "Field `IQ_EST_FORCE_PU` writer - Force Power Up for IQ Estimation"] +pub type IQ_EST_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 4 - Force Power Down for IQ Estimation"] + #[inline(always)] + pub fn iq_est_force_pd(&self) -> IQ_EST_FORCE_PD_R { + IQ_EST_FORCE_PD_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Force Power Up for IQ Estimation"] + #[inline(always)] + pub fn iq_est_force_pu(&self) -> IQ_EST_FORCE_PU_R { + IQ_EST_FORCE_PU_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GEN_CTRL") + .field("iq_est_force_pu", &self.iq_est_force_pu()) + .field("iq_est_force_pd", &self.iq_est_force_pd()) + .finish() + } +} +impl W { + #[doc = "Bit 4 - Force Power Down for IQ Estimation"] + #[inline(always)] + #[must_use] + pub fn iq_est_force_pd(&mut self) -> IQ_EST_FORCE_PD_W { + IQ_EST_FORCE_PD_W::new(self, 4) + } + #[doc = "Bit 5 - Force Power Up for IQ Estimation"] + #[inline(always)] + #[must_use] + pub fn iq_est_force_pu(&mut self) -> IQ_EST_FORCE_PU_W { + IQ_EST_FORCE_PU_W::new(self, 5) + } +} +#[doc = "FE General Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`gen_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gen_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GEN_CTRL_SPEC; +impl crate::RegisterSpec for GEN_CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`gen_ctrl::R`](R) reader structure"] +impl crate::Readable for GEN_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gen_ctrl::W`](W) writer structure"] +impl crate::Writable for GEN_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0; +} +#[doc = "`reset()` method sets GEN_CTRL to value 0"] +impl crate::Resettable for GEN_CTRL_SPEC { + const RESET_VALUE: u8 = 0; +} diff --git a/esp32s3/src/fe2.rs b/esp32s3/src/fe2.rs new file mode 100644 index 0000000000..d45b5ddad5 --- /dev/null +++ b/esp32s3/src/fe2.rs @@ -0,0 +1,18 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved0: [u8; 0xf0], + tx_interp_ctrl: TX_INTERP_CTRL, +} +impl RegisterBlock { + #[doc = "0xf0 - FE2 TX Interpolation Control Register"] + #[inline(always)] + pub const fn tx_interp_ctrl(&self) -> &TX_INTERP_CTRL { + &self.tx_interp_ctrl + } +} +#[doc = "TX_INTERP_CTRL (rw) register accessor: FE2 TX Interpolation Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_interp_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_interp_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_interp_ctrl`] module"] +pub type TX_INTERP_CTRL = crate::Reg; +#[doc = "FE2 TX Interpolation Control Register"] +pub mod tx_interp_ctrl; diff --git a/esp32s3/src/fe2/tx_interp_ctrl.rs b/esp32s3/src/fe2/tx_interp_ctrl.rs new file mode 100644 index 0000000000..c019b49ecc --- /dev/null +++ b/esp32s3/src/fe2/tx_interp_ctrl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `TX_INTERP_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `TX_INTERP_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `TX_INF_FORCE_PD` reader - Force Power Down field"] +pub type TX_INF_FORCE_PD_R = crate::BitReader; +#[doc = "Field `TX_INF_FORCE_PD` writer - Force Power Down field"] +pub type TX_INF_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_INF_FORCE_PU` reader - Force Power Up field"] +pub type TX_INF_FORCE_PU_R = crate::BitReader; +#[doc = "Field `TX_INF_FORCE_PU` writer - Force Power Up field"] +pub type TX_INF_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 9 - Force Power Down field"] + #[inline(always)] + pub fn tx_inf_force_pd(&self) -> TX_INF_FORCE_PD_R { + TX_INF_FORCE_PD_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Force Power Up field"] + #[inline(always)] + pub fn tx_inf_force_pu(&self) -> TX_INF_FORCE_PU_R { + TX_INF_FORCE_PU_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_INTERP_CTRL") + .field("tx_inf_force_pu", &self.tx_inf_force_pu()) + .field("tx_inf_force_pd", &self.tx_inf_force_pd()) + .finish() + } +} +impl W { + #[doc = "Bit 9 - Force Power Down field"] + #[inline(always)] + #[must_use] + pub fn tx_inf_force_pd(&mut self) -> TX_INF_FORCE_PD_W { + TX_INF_FORCE_PD_W::new(self, 9) + } + #[doc = "Bit 10 - Force Power Up field"] + #[inline(always)] + #[must_use] + pub fn tx_inf_force_pu(&mut self) -> TX_INF_FORCE_PU_W { + TX_INF_FORCE_PU_W::new(self, 10) + } +} +#[doc = "FE2 TX Interpolation Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_interp_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_interp_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_INTERP_CTRL_SPEC; +impl crate::RegisterSpec for TX_INTERP_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_interp_ctrl::R`](R) reader structure"] +impl crate::Readable for TX_INTERP_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_interp_ctrl::W`](W) writer structure"] +impl crate::Writable for TX_INTERP_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TX_INTERP_CTRL to value 0"] +impl crate::Resettable for TX_INTERP_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s3/src/lib.rs b/esp32s3/src/lib.rs index 6289a88d9f..ef50fa3b38 100644 --- a/esp32s3/src/lib.rs +++ b/esp32s3/src/lib.rs @@ -3108,6 +3108,144 @@ impl core::fmt::Debug for XTS_AES { } #[doc = "XTS-AES-128 Flash Encryption"] pub mod xts_aes; +#[doc = "NRX Peripheral"] +pub struct NRX { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for NRX {} +impl NRX { + #[doc = r"Pointer to the register block"] + pub const PTR: *const nrx::RegisterBlock = 0x6001_cc00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const nrx::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for NRX { + type Target = nrx::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for NRX { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("NRX").finish() + } +} +#[doc = "NRX Peripheral"] +pub mod nrx; +#[doc = "need des"] +pub struct FE { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for FE {} +impl FE { + #[doc = r"Pointer to the register block"] + pub const PTR: *const fe::RegisterBlock = 0x6000_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const fe::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for FE { + type Target = fe::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for FE { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FE").finish() + } +} +#[doc = "need des"] +pub mod fe; +#[doc = "need des"] +pub struct FE2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for FE2 {} +impl FE2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const fe2::RegisterBlock = 0x6000_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const fe2::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for FE2 { + type Target = fe2::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for FE2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FE2").finish() + } +} +#[doc = "need des"] +pub mod fe2; #[no_mangle] static mut DEVICE_PERIPHERALS: bool = false; #[doc = r" All the peripherals."] @@ -3221,6 +3359,12 @@ pub struct Peripherals { pub WCL: WCL, #[doc = "XTS_AES"] pub XTS_AES: XTS_AES, + #[doc = "NRX"] + pub NRX: NRX, + #[doc = "FE"] + pub FE: FE, + #[doc = "FE2"] + pub FE2: FE2, } impl Peripherals { #[doc = r" Returns all the peripherals *once*."] @@ -3297,6 +3441,9 @@ impl Peripherals { USB_WRAP: USB_WRAP::steal(), WCL: WCL::steal(), XTS_AES: XTS_AES::steal(), + NRX: NRX::steal(), + FE: FE::steal(), + FE2: FE2::steal(), } } } diff --git a/esp32s3/src/nrx.rs b/esp32s3/src/nrx.rs new file mode 100644 index 0000000000..e027171e30 --- /dev/null +++ b/esp32s3/src/nrx.rs @@ -0,0 +1,18 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved0: [u8; 0xd4], + nrxpd_ctrl: NRXPD_CTRL, +} +impl RegisterBlock { + #[doc = "0xd4 - NRX Power Down Control Register"] + #[inline(always)] + pub const fn nrxpd_ctrl(&self) -> &NRXPD_CTRL { + &self.nrxpd_ctrl + } +} +#[doc = "NRXPD_CTRL (rw) register accessor: NRX Power Down Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`nrxpd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nrxpd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nrxpd_ctrl`] module"] +pub type NRXPD_CTRL = crate::Reg; +#[doc = "NRX Power Down Control Register"] +pub mod nrxpd_ctrl; diff --git a/esp32s3/src/nrx/nrxpd_ctrl.rs b/esp32s3/src/nrx/nrxpd_ctrl.rs new file mode 100644 index 0000000000..4de238a244 --- /dev/null +++ b/esp32s3/src/nrx/nrxpd_ctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `NRXPD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `NRXPD_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `DEMAP_FORCE_PD` reader - Force Power Down for Demapper"] +pub type DEMAP_FORCE_PD_R = crate::BitReader; +#[doc = "Field `DEMAP_FORCE_PD` writer - Force Power Down for Demapper"] +pub type DEMAP_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEMAP_FORCE_PU` reader - Force Power Up for Demapper"] +pub type DEMAP_FORCE_PU_R = crate::BitReader; +#[doc = "Field `DEMAP_FORCE_PU` writer - Force Power Up for Demapper"] +pub type DEMAP_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VIT_FORCE_PD` reader - Force Power Down for Viterbi Decoder"] +pub type VIT_FORCE_PD_R = crate::BitReader; +#[doc = "Field `VIT_FORCE_PD` writer - Force Power Down for Viterbi Decoder"] +pub type VIT_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VIT_FORCE_PU` reader - Force Power Up for Viterbi Decoder"] +pub type VIT_FORCE_PU_R = crate::BitReader; +#[doc = "Field `VIT_FORCE_PU` writer - Force Power Up for Viterbi Decoder"] +pub type VIT_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_ROT_FORCE_PD` reader - Force Power Down for RX Rotation"] +pub type RX_ROT_FORCE_PD_R = crate::BitReader; +#[doc = "Field `RX_ROT_FORCE_PD` writer - Force Power Down for RX Rotation"] +pub type RX_ROT_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_ROT_FORCE_PU` reader - Force Power Up for RX Rotation"] +pub type RX_ROT_FORCE_PU_R = crate::BitReader; +#[doc = "Field `RX_ROT_FORCE_PU` writer - Force Power Up for RX Rotation"] +pub type RX_ROT_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CHAN_EST_FORCE_PD` reader - Force Power Down for Channel Estimation"] +pub type CHAN_EST_FORCE_PD_R = crate::BitReader; +#[doc = "Field `CHAN_EST_FORCE_PD` writer - Force Power Down for Channel Estimation"] +pub type CHAN_EST_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CHAN_EST_FORCE_PU` reader - Force Power Up for Channel Estimation"] +pub type CHAN_EST_FORCE_PU_R = crate::BitReader; +#[doc = "Field `CHAN_EST_FORCE_PU` writer - Force Power Up for Channel Estimation"] +pub type CHAN_EST_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Force Power Down for Demapper"] + #[inline(always)] + pub fn demap_force_pd(&self) -> DEMAP_FORCE_PD_R { + DEMAP_FORCE_PD_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Force Power Up for Demapper"] + #[inline(always)] + pub fn demap_force_pu(&self) -> DEMAP_FORCE_PU_R { + DEMAP_FORCE_PU_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Force Power Down for Viterbi Decoder"] + #[inline(always)] + pub fn vit_force_pd(&self) -> VIT_FORCE_PD_R { + VIT_FORCE_PD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Force Power Up for Viterbi Decoder"] + #[inline(always)] + pub fn vit_force_pu(&self) -> VIT_FORCE_PU_R { + VIT_FORCE_PU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Force Power Down for RX Rotation"] + #[inline(always)] + pub fn rx_rot_force_pd(&self) -> RX_ROT_FORCE_PD_R { + RX_ROT_FORCE_PD_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Force Power Up for RX Rotation"] + #[inline(always)] + pub fn rx_rot_force_pu(&self) -> RX_ROT_FORCE_PU_R { + RX_ROT_FORCE_PU_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Force Power Down for Channel Estimation"] + #[inline(always)] + pub fn chan_est_force_pd(&self) -> CHAN_EST_FORCE_PD_R { + CHAN_EST_FORCE_PD_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Force Power Up for Channel Estimation"] + #[inline(always)] + pub fn chan_est_force_pu(&self) -> CHAN_EST_FORCE_PU_R { + CHAN_EST_FORCE_PU_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("NRXPD_CTRL") + .field("chan_est_force_pu", &self.chan_est_force_pu()) + .field("chan_est_force_pd", &self.chan_est_force_pd()) + .field("rx_rot_force_pu", &self.rx_rot_force_pu()) + .field("rx_rot_force_pd", &self.rx_rot_force_pd()) + .field("vit_force_pu", &self.vit_force_pu()) + .field("vit_force_pd", &self.vit_force_pd()) + .field("demap_force_pu", &self.demap_force_pu()) + .field("demap_force_pd", &self.demap_force_pd()) + .finish() + } +} +impl W { + #[doc = "Bit 0 - Force Power Down for Demapper"] + #[inline(always)] + #[must_use] + pub fn demap_force_pd(&mut self) -> DEMAP_FORCE_PD_W { + DEMAP_FORCE_PD_W::new(self, 0) + } + #[doc = "Bit 1 - Force Power Up for Demapper"] + #[inline(always)] + #[must_use] + pub fn demap_force_pu(&mut self) -> DEMAP_FORCE_PU_W { + DEMAP_FORCE_PU_W::new(self, 1) + } + #[doc = "Bit 2 - Force Power Down for Viterbi Decoder"] + #[inline(always)] + #[must_use] + pub fn vit_force_pd(&mut self) -> VIT_FORCE_PD_W { + VIT_FORCE_PD_W::new(self, 2) + } + #[doc = "Bit 3 - Force Power Up for Viterbi Decoder"] + #[inline(always)] + #[must_use] + pub fn vit_force_pu(&mut self) -> VIT_FORCE_PU_W { + VIT_FORCE_PU_W::new(self, 3) + } + #[doc = "Bit 4 - Force Power Down for RX Rotation"] + #[inline(always)] + #[must_use] + pub fn rx_rot_force_pd(&mut self) -> RX_ROT_FORCE_PD_W { + RX_ROT_FORCE_PD_W::new(self, 4) + } + #[doc = "Bit 5 - Force Power Up for RX Rotation"] + #[inline(always)] + #[must_use] + pub fn rx_rot_force_pu(&mut self) -> RX_ROT_FORCE_PU_W { + RX_ROT_FORCE_PU_W::new(self, 5) + } + #[doc = "Bit 6 - Force Power Down for Channel Estimation"] + #[inline(always)] + #[must_use] + pub fn chan_est_force_pd(&mut self) -> CHAN_EST_FORCE_PD_W { + CHAN_EST_FORCE_PD_W::new(self, 6) + } + #[doc = "Bit 7 - Force Power Up for Channel Estimation"] + #[inline(always)] + #[must_use] + pub fn chan_est_force_pu(&mut self) -> CHAN_EST_FORCE_PU_W { + CHAN_EST_FORCE_PU_W::new(self, 7) + } +} +#[doc = "NRX Power Down Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`nrxpd_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nrxpd_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NRXPD_CTRL_SPEC; +impl crate::RegisterSpec for NRXPD_CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`nrxpd_ctrl::R`](R) reader structure"] +impl crate::Readable for NRXPD_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nrxpd_ctrl::W`](W) writer structure"] +impl crate::Writable for NRXPD_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0; +} +#[doc = "`reset()` method sets NRXPD_CTRL to value 0"] +impl crate::Resettable for NRXPD_CTRL_SPEC { + const RESET_VALUE: u8 = 0; +} diff --git a/esp32s3/svd/patches/esp32s3.yaml b/esp32s3/svd/patches/esp32s3.yaml index 9a3178d890..8ff0f7026b 100644 --- a/esp32s3/svd/patches/esp32s3.yaml +++ b/esp32s3/svd/patches/esp32s3.yaml @@ -1,5 +1,112 @@ _svd: ../esp32s3.base.svd +_add: + NRX: + description: NRX Peripheral + baseAddress: 0x6001CC00 + groupName: NRX + addressBlock: + offset: 0x0 + size: 0x4 + usage: registers + registers: + NRXPD_CTRL: + description: "NRX Power Down Control Register" + addressOffset: 0xD4 + size: 0x4 + access: read-write + fields: + CHAN_EST_FORCE_PU: + description: "Force Power Up for Channel Estimation" + bitOffset: 7 + bitWidth: 1 + access: read-write + CHAN_EST_FORCE_PD: + description: "Force Power Down for Channel Estimation" + bitOffset: 6 + bitWidth: 1 + access: read-write + RX_ROT_FORCE_PU: + description: "Force Power Up for RX Rotation" + bitOffset: 5 + bitWidth: 1 + access: read-write + RX_ROT_FORCE_PD: + description: "Force Power Down for RX Rotation" + bitOffset: 4 + bitWidth: 1 + access: read-write + VIT_FORCE_PU: + description: "Force Power Up for Viterbi Decoder" + bitOffset: 3 + bitWidth: 1 + access: read-write + VIT_FORCE_PD: + description: "Force Power Down for Viterbi Decoder" + bitOffset: 2 + bitWidth: 1 + access: read-write + DEMAP_FORCE_PU: + description: "Force Power Up for Demapper" + bitOffset: 1 + bitWidth: 1 + access: read-write + DEMAP_FORCE_PD: + description: "Force Power Down for Demapper" + bitOffset: 0 + bitWidth: 1 + access: read-write + FE: + description: need des + baseAddress: 0x60006000 + groupName: FE + addressBlock: + offset: 0x0 + size: 0x4 + usage: registers + registers: + GEN_CTRL: + description: "FE General Control Register" + addressOffset: 0x0090 + size: 0x2 + access: read-write + fields: + IQ_EST_FORCE_PU: + description: "Force Power Up for IQ Estimation" + bitOffset: 5 + bitWidth: 1 + access: read-write + IQ_EST_FORCE_PD: + description: "Force Power Down for IQ Estimation" + bitOffset: 4 + bitWidth: 1 + access: read-write + FE2: + description: need des + baseAddress: 0x60005000 + groupName: FE + addressBlock: + offset: 0x0 + size: 0x4 + usage: registers + registers: + TX_INTERP_CTRL: + description: "FE2 TX Interpolation Control Register" + addressOffset: 0x00f0 + size: 0x20 + access: read-write + fields: + TX_INF_FORCE_PU: + description: "Force Power Up field" + bitOffset: 10 + bitWidth: 1 + access: read-write + TX_INF_FORCE_PD: + description: "Force Power Down field" + bitOffset: 9 + bitWidth: 1 + access: read-write + _modify: SPI?: groupName: SPI