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base repository: alexforencich/verilog-ethernet
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base: master
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head repository: etlsystems/verilog-ethernet
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compare: master
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  • 6 commits
  • 38 files changed
  • 2 contributors

Commits on Jan 3, 2025

  1. Update to compile (#1)

    @ollie-etl
    ollie-etl authored Jan 3, 2025
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  2. Allow manual test run (#2)

    @ollie-etl
    ollie-etl authored Jan 3, 2025
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Commits on Feb 3, 2025

  1. gmii to rgmii converter (#3)

    @kavitha-etl
    kavitha-etl authored Feb 3, 2025
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Commits on May 14, 2025

  1. Interface tidyup (#5)

    @ollie-etl
    ollie-etl authored May 14, 2025
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Commits on Jul 15, 2025

  1. IDELAYE3 integration (#7)

    @kavitha-etl
    kavitha-etl authored Jul 15, 2025
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Commits on Jul 21, 2025

  1. DELAY_VALUE as parameter (#8)

    @kavitha-etl
    kavitha-etl authored Jul 21, 2025
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