From 5b25ac2bc4c2953e3a2ee377fd3b892d348a89b4 Mon Sep 17 00:00:00 2001 From: BennehBoy Date: Sat, 5 Jan 2019 16:40:56 +0000 Subject: [PATCH] Correct PLL Freq from 25 to 8 to fix USB --- variants/DIYMROE_F407VGT/variant.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/variants/DIYMROE_F407VGT/variant.cpp b/variants/DIYMROE_F407VGT/variant.cpp index 1bd7c0e629..231e8f5859 100644 --- a/variants/DIYMROE_F407VGT/variant.cpp +++ b/variants/DIYMROE_F407VGT/variant.cpp @@ -184,7 +184,7 @@ WEAK void SystemClock_Config(void) RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 25; + RCC_OscInitStruct.PLL.PLLM = 8; RCC_OscInitStruct.PLL.PLLN = 336; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = 7;