Support IEEE 1800-2023 language keywords. (No other 2023 support yet.)

Author: wsnyder

Changes

@@ -6,6 +6,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 * Verilog-Perl 3.481 devel
 
+***   Support IEEE 1800-2023 language keywords. (No other 2023 support yet.)
+
 ****  Fix t/03_spaces.t test for Debian (#1675). [Gregor Herrmann]
 
 ****  Fix GCC 11 false free-nonheap-obj warning.

Language.pm

@@ -35,7 +35,7 @@ General functions will be added as needed.
 Return true if the given symbol string is a Verilog reserved keyword.
 Value indicates the language standard as per the `begin_keywords macro,
 '1364-1995', '1364-2001', '1364-2005', '1800-2005', '1800-2009',
-'1800-2012', '1800-2017' or 'VAMS'.
+'1800-2012', '1800-2017', '1800-2023', or 'VAMS'.
 
 =item Verilog::Language::is_compdirect($symbol_string)
 
@@ -56,12 +56,12 @@ value of the hash is the standard in which it was defined.
 Sets the language standard to indicate what are keywords.  If undef, all
 standards apply.  The year is indicates the language standard as per the
 `begin_keywords macro, '1364-1995', '1364-2001', '1364-2005', '1800-2005'
-'1800-2009', '1800-2012' or '1800-2017'.
+'1800-2009', '1800-2012', '1800-2017', or '1800-2023'.
 
 =item Verilog::Language::language_maximum
 
 Returns the greatest language currently standardized, presently
-'1800-2017'.
+'1800-2023'.
 
 =item Verilog::Language::number_bigint($number_string)
 
@@ -219,6 +219,9 @@ foreach my $kwd (qw(
 foreach my $kwd (qw(
 		    )) { $Keywords{'1800-2017'}{$kwd} = '1800-2017'; }
 
+foreach my $kwd (qw(
+		    )) { $Keywords{'1800-2023'}{$kwd} = '1800-2023'; }
+
 foreach my $kwd (qw(
 		    above abs absdelay abstol ac_stim access acos acosh
 		    aliasparam analog analysis asin asinh assert atan atan2
@@ -304,7 +307,7 @@ foreach my $kwd (qw(
 #### Keyword utilities
 
 sub language_maximum {
-    return "1800-2017";
+    return "1800-2023";
 }
 
 sub _language_kwd_hash {
@@ -333,10 +336,14 @@ sub _language_kwd_hash {
 	$Standard = '1800-2012';
 	@subsets = ('1800-2012', '1800-2009', '1800-2005',
 		    '1364-2005', '1364-2001', '1364-1995');
-    } elsif ($standard eq 'latest' || $standard eq '1800-2017') {
+    } elsif ($standard eq '1800-2017') {
 	$Standard = '1800-2017';
 	@subsets = ('1800-2017', '1800-2012', '1800-2009', '1800-2005',
 		    '1364-2005', '1364-2001', '1364-1995');
+    } elsif ($standard eq 'latest' || $standard eq '1800-2023') {
+	$Standard = '1800-2023';
+	@subsets = ('1800-2023', '1800-2017', '1800-2012', '1800-2009', '1800-2005',
+		    '1364-2005', '1364-2001', '1364-1995');
     } elsif ($standard =~ /^V?AMS/) {
 	$Standard = 'VAMS';
 	@subsets = ('VAMS',

Parser/VParseLex.l

@@ -40,7 +40,7 @@
 
 #define YY_SKIP_YYWRAP
 
-#define STATE_VERILOG_RECENT  S17		// State name for most recent Verilog Version
+#define STATE_VERILOG_RECENT  S23		// State name for most recent Verilog Version
 
 // Flex 2.5.35 has compile warning in ECHO, so we'll default our own rule
 #define ECHO yyerrorf("Missing VParseLex.l rule: ECHO rule invoked in state %d: %s", YY_START, yytext);
@@ -88,7 +88,7 @@ void yyerrorf(const char* format, ...) {
 /**********************************************************************/
 %}
 
-%s V95 V01 V05 S05 S09 S12 S17
+%s V95 V01 V05 S05 S09 S12 S17 S23
 %s STRING ATTRMODE
 %s CMTMODE PROTMODE
 %s DUMMY_TO_AVOID_WARNING
@@ -114,7 +114,7 @@ vnum	{vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
 <INITIAL>.|\n 		{BEGIN STATE_VERILOG_RECENT; yyless(0); }
 
   /* Verilog 1995 */
-<V95,V01,V05,S05,S09,S12,S17>{
+<V95,V01,V05,S05,S09,S12,S17,S23>{
   {ws}			{ StashPrefix; }	/* otherwise ignore white-space */
   {crnl}		{ StashPrefix; NEXTLINE(); }		/* Count line numbers */
   /*     Keywords */
@@ -224,7 +224,7 @@ vnum	{vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
 }
 
   /* Verilog 2001 */
-<V01,V05,S05,S09,S12,S17>{
+<V01,V05,S05,S09,S12,S17,S23>{
   /*     Keywords*/
   "automatic"		{ FL; VALTEXT; CALLBACK(keywordCb); return yAUTOMATIC; }
   "endgenerate"		{ FL; VALTEXT; CALLBACK(keywordCb); return yENDGENERATE; }
@@ -252,13 +252,13 @@ vnum	{vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
 }
 
   /* Verilog 2005 */
-<V05,S05,S09,S12,S17>{
+<V05,S05,S09,S12,S17,S23>{
   /*     Keywords */
   "uwire"		{ FL; VALTEXT; CALLBACK(keywordCb); return yWIRE; }
 }
 
   /* System Verilog 2005 */
-<S05,S09,S12,S17>{
+<S05,S09,S12,S17,S23>{
   /*     System Tasks */
   "$error"		{ FL; VALTEXT; CALLBACK(keywordCb); return yD_ERROR; }
   "$fatal"		{ FL; VALTEXT; CALLBACK(keywordCb); return yD_FATAL; }
@@ -367,7 +367,7 @@ vnum	{vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
 }
 
   /* System Verilog 2009 */
-<S09,S12,S17>{
+<S09,S12,S17,S23>{
   /*     Keywords */
   "accept_on"	 	{ FL; VALTEXT; CALLBACK(keywordCb); return yACCEPT_ON; }
   "checker"	 	{ FL; VALTEXT; CALLBACK(keywordCb); return yCHECKER; }
@@ -395,7 +395,7 @@ vnum	{vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
 }
 
   /* System Verilog 2012 */
-<S12,S17>{
+<S12,S17,S23>{
   /*     Keywords */
   "implements"	 	{ FL; VALTEXT; CALLBACK(keywordCb); return yIMPLEMENTS; }
   "interconnect" 	{ FL; VALTEXT; CALLBACK(keywordCb); return yINTERCONNECT; }
@@ -407,18 +407,18 @@ vnum	{vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   /* No new keywords */
 
   /* Default PLI rule */
-<V95,V01,V05,S05,S09,S12,S17>{
+<V95,V01,V05,S05,S09,S12,S17,S23>{
     "$"[a-zA-Z_$][a-zA-Z0-9_$]*	{ FL; VALTEXT; CALLBACK(sysfuncCb); return ygenSYSCALL; }
 }
 
   /************************************************************************/
 
   /* Single character operator thingies */
-<V95,V01,V05,S05,S09,S12,S17>{
+<V95,V01,V05,S05,S09,S12,S17,S23>{
   "{"			{ FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; }
   "}"			{ FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; }
 }
-<V95,V01,V05,S05,S09,S12,S17>{
+<V95,V01,V05,S05,S09,S12,S17,S23>{
   "!"			{ FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; }
   "#"			{ FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; }
   "$"			{ FL; VALTEXT; CALLBACK(operatorCb); return yytext[0]; }
@@ -450,7 +450,7 @@ vnum	{vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   /* Operators and multi-character symbols */
 
   /* Verilog 1995 Operators */
-<V95,V01,V05,S05,S09,S12,S17>{
+<V95,V01,V05,S05,S09,S12,S17,S23>{
   "&&"			{ FL; VALTEXT; CALLBACK(operatorCb); return yP_ANDAND; }
   "||"			{ FL; VALTEXT; CALLBACK(operatorCb); return yP_OROR; }
   "<="			{ FL; VALTEXT; CALLBACK(operatorCb); return yP_LTE; }
@@ -472,7 +472,7 @@ vnum	{vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
 }
 
   /* Verilog 2001 Operators */
-<V01,V05,S05,S09,S12,S17>{
+<V01,V05,S05,S09,S12,S17,S23>{
   "<<<"			{ FL; VALTEXT; CALLBACK(operatorCb); return yP_SLEFT; }
   ">>>"			{ FL; VALTEXT; CALLBACK(operatorCb); return yP_SSRIGHT; }
   "**"			{ FL; VALTEXT; CALLBACK(operatorCb); return yP_POW; }
@@ -482,7 +482,7 @@ vnum	{vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
 }
 
   /* SystemVerilog 2005 Operators */
-<S05,S09,S12,S17>{
+<S05,S09,S12,S17,S23>{
   "'"			{ FL; VALTEXT; CALLBACK(operatorCb); return yP_TICK; }
   "'{"			{ FL; VALTEXT; CALLBACK(operatorCb); return yP_TICKBRA; }
   "==?"			{ FL; VALTEXT; CALLBACK(operatorCb); return yP_WILDEQUAL; }
@@ -517,12 +517,12 @@ vnum	{vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
 }
 
   /* SystemVerilog 2009 Operators */
-<S09,S12,S17>{
+<S09,S12,S17,S23>{
   "<->"			{ FL; VALTEXT; CALLBACK(operatorCb); return yP_LTMINUSGT; }
 }
 
   /* Identifiers and numbers */
-<V95,V01,V05,S05,S09,S12,S17>{
+<V95,V01,V05,S05,S09,S12,S17,S23>{
   /* Consume a following space, as we're going to add one to the symbol, we'd like to avoid inserting an extra */
   {escid}{space}	{ if (VParseLex::symEscapeless(yytext+1,yyleng-1-1)) {
 			      string sym = string(yytext+1,yyleng-1-1);
@@ -619,13 +619,13 @@ vnum	{vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   /************************************************************************/
   /* Attributes */
   /* Note simulators vary in support for "(* /_*something*_/ foo*)" where _ doesn't exist */
-<V95,V01,V05,S05,S09,S12,S17>{
+<V95,V01,V05,S05,S09,S12,S17,S23>{
     "(*"({ws}|{crnl})*({id}|{escid})	{ yymore(); yy_push_state(ATTRMODE); }	/* Doesn't match (*), but (* attr_spec */
 }
 
   /************************************************************************/
   /* Preprocessor */
-<V95,V01,V05,S05,S09,S12,S17>{
+<V95,V01,V05,S05,S09,S12,S17,S23>{
   "`accelerate"				{ FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility
   "`autoexpand_vectornets"		{ FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility
   "`celldefine"				{ FL; VALTEXT; CALLBACK(preprocCb); LEXP->m_inCellDefine=true; }
@@ -669,13 +669,14 @@ vnum	{vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   "`begin_keywords"[ \t]*\"1800-2009\"		{ yy_push_state(S09); CALLBACK(preprocCb); }
   "`begin_keywords"[ \t]*\"1800-2012\"		{ yy_push_state(S12); CALLBACK(preprocCb); }
   "`begin_keywords"[ \t]*\"1800-2017\"		{ yy_push_state(S17); CALLBACK(preprocCb); }
+  "`begin_keywords"[ \t]*\"1800-2023\"		{ yy_push_state(S23); CALLBACK(preprocCb); }
   "`end_keywords"				{ yy_pop_state();     CALLBACK(preprocCb); }
 }
 
   /************************************************************************/
   /* Default rules - leave last */
 
-<V95,V01,V05,S05,S09,S12,S17>{
+<V95,V01,V05,S05,S09,S12,S17,S23>{
   "`"[a-zA-Z_0-9]+	{ FL; VALTEXT;
 			  if (LPARSEP->sigParser()) { yyerrorf("Define or directive not defined: %s",yytext); }
 			  else { CALLBACK(preprocCb); } }
@@ -882,6 +883,7 @@ void VParseLex::language(const char* value) {
     else if (0==strcmp(value,"1800-2009"))	{ BEGIN S09; }
     else if (0==strcmp(value,"1800-2012"))	{ BEGIN S12; }
     else if (0==strcmp(value,"1800-2017"))	{ BEGIN S17; }
+    else if (0==strcmp(value,"1800-2023"))	{ BEGIN S23; }
     else yyerrorf("Unknown setLanguage code: %s", value);
 }
 

README.pod

@@ -154,7 +154,7 @@ It understands and implements all preprocessor features of SystemVerilog
 Verilog::Parser is useful when you need to tokenize or write source filters
 (where you need everything including whitespace).  It can take raw files,
 or preprocessed input, and generates callbacks.  It understands all
-SystemVerilog 2017 keywords.
+SystemVerilog 2023 keywords.
 
 =item Abstract Syntax Tree
 

t/10_keywords.t

@@ -8,7 +8,7 @@
 use strict;
 use Test::More;
 
-BEGIN { plan tests => 26 }
+BEGIN { plan tests => 27 }
 BEGIN { require "./t/test_utils.pl"; }
 
 use Verilog::Language;
@@ -18,7 +18,8 @@ ok (Verilog::Language::is_keyword("input"));
 ok (!Verilog::Language::is_keyword("not_input"));
 ok (Verilog::Language::is_compdirect("`define"));
 
-is (Verilog::Language::language_standard(), '1800-2017');
+is (Verilog::Language::language_standard(), '1800-2023');
+is (Verilog::Language::language_standard('1800-2023'), '1800-2023');
 is (Verilog::Language::language_standard('1800-2017'), '1800-2017');
 is (Verilog::Language::language_standard('1800-2012'), '1800-2012');
 is (Verilog::Language::language_standard('1800-2009'), '1800-2009');
@@ -34,7 +35,7 @@ ok (Verilog::Language::is_keyword("generate"));
 is (Verilog::Language::language_standard(1995), '1364-1995');
 ok (!Verilog::Language::is_keyword("generate"));
 
-is (Verilog::Language::language_maximum(), '1800-2017', 'language_maximum');
+is (Verilog::Language::language_maximum(), '1800-2023', 'language_maximum');
 
 is (Verilog::Language::strip_comments("he/**/l/**/lo"), "hello");
 is (Verilog::Language::strip_comments("he//xx/*\nllo"), "he\nllo");

vhier

@@ -63,7 +63,7 @@ if (! GetOptions (
 		  "input-files!"	=> \$Opt_InFiles,
 		  "resolve-files!"	=> \$Opt_ResolveFiles,
 		  "skiplist=s"		=> \$opt_skiplist,
-		  "sv!"			=> sub { shift; Verilog::Language::language_standard("1800-2017"); },
+		  "sv!"			=> sub { shift; Verilog::Language::language_standard("1800-2023"); },
 		  "language=s"		=> sub { shift; Verilog::Language::language_standard(shift); },
 		  "missing!"		=> \$Opt_Missing,
 		  "missing-modules!"	=> \$Opt_Missing_Modules,
@@ -468,7 +468,7 @@ example module I<x> is referenced, look in I<x>.I<ext>.
 =item -sv
 
 Specifies SystemVerilog language features should be enabled; equivalent to
-"--language 1800-2017".  This option is selected by default, it exists for
+"--language 1800-2023".  This option is selected by default, it exists for
 compatibility with other simulators.
 
 =item -y I<dir>
@@ -513,7 +513,7 @@ necessary to resolve it into an absolute path for further processing.
 
 With --cells or --forest, show module instance names.
 
-=item --language <1364-1995|1364-2001|1364-2005|1800-2005|1800-2009|1800-2012|1800-2017>
+=item --language <1364-1995|1364-2001|1364-2005|1800-2005|1800-2009|1800-2012|1800-2017|1800-2023>
 
 Set the language standard for the files.  This determines which tokens are
 signals versus keywords, such as the ever-common "do" (data-out signal,

vpassert

@@ -1495,7 +1495,7 @@ Exclude processing any files which begin with the specified prefix.
 
 Displays this message and program version and exits.
 
-=item --language <1364-1995|1364-2001|1364-2005|1800-2005|1800-2009|1800-2012|1800-2017>
+=item --language <1364-1995|1364-2001|1364-2005|1800-2005|1800-2009|1800-2012|1800-2017|1800-2023>
 
 Set the language standard for the files.  This determines which tokens are
 signals versus keywords, such as the ever-common "do" (data-out signal,

vrename

@@ -677,7 +677,7 @@ changing a keyword will probably result in unrunnable code, however,
 occasionally it may be necessary to rename signals which happen to match
 the name of keywords recently added to the language (such as 'bit').
 
-=item --language <1364-1995|1364-2001|1364-2005|1800-2005|1800-2009|1800-2012|1800-2017>
+=item --language <1364-1995|1364-2001|1364-2005|1800-2005|1800-2009|1800-2012|1800-2017|1800-2023>
 
 Set the language standard for the files.  This determines which tokens are
 signals versus keywords, such as the ever-common "do" (data-out signal,