Initial commit

ultraembedded · web-flow · commit ddf7746a1b9a · 2020-07-14T23:30:43.000+01:00
diff --git a/README.md b/README.md
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+# core_ddr3_controller
+A DDR3 memory controller in Verilog for various FPGAs

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	`1`	`+# core_ddr3_controller`
	`2`	`+A DDR3 memory controller in Verilog for various FPGAs`