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smeenaismeenai
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clang-format
1 parent 4d269e8 commit 4041cb9

32 files changed

+841
-880
lines changed

‎clang/lib/CIR/CodeGen/CIRAsm.cpp‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -227,8 +227,8 @@ std::pair<mlir::Value, mlir::Type> CIRGenFunction::emitAsmInputLValue(
227227

228228
std::pair<mlir::Value, mlir::Type>
229229
CIRGenFunction::emitAsmInput(const TargetInfo::ConstraintInfo &Info,
230-
const Expr *InputExpr,
231-
std::string &ConstraintStr) {
230+
const Expr *InputExpr,
231+
std::string &ConstraintStr) {
232232
auto loc = getLoc(InputExpr->getExprLoc());
233233

234234
// If this can't be a register or memory, i.e., has to be a constant
@@ -257,17 +257,17 @@ CIRGenFunction::emitAsmInput(const TargetInfo::ConstraintInfo &Info,
257257
InputExpr = InputExpr->IgnoreParenNoopCasts(getContext());
258258
LValue Dest = emitLValue(InputExpr);
259259
return emitAsmInputLValue(Info, Dest, InputExpr->getType(), ConstraintStr,
260-
InputExpr->getExprLoc());
260+
InputExpr->getExprLoc());
261261
}
262262

263263
static void emitAsmStores(CIRGenFunction &CGF, const AsmStmt &S,
264-
const llvm::ArrayRef<mlir::Value> RegResults,
265-
const llvm::ArrayRef<mlir::Type> ResultRegTypes,
266-
const llvm::ArrayRef<mlir::Type> ResultTruncRegTypes,
267-
const llvm::ArrayRef<LValue> ResultRegDests,
268-
const llvm::ArrayRef<QualType> ResultRegQualTys,
269-
const llvm::BitVector &ResultTypeRequiresCast,
270-
const llvm::BitVector &ResultRegIsFlagReg) {
264+
const llvm::ArrayRef<mlir::Value> RegResults,
265+
const llvm::ArrayRef<mlir::Type> ResultRegTypes,
266+
const llvm::ArrayRef<mlir::Type> ResultTruncRegTypes,
267+
const llvm::ArrayRef<LValue> ResultRegDests,
268+
const llvm::ArrayRef<QualType> ResultRegQualTys,
269+
const llvm::BitVector &ResultTypeRequiresCast,
270+
const llvm::BitVector &ResultRegIsFlagReg) {
271271
CIRGenBuilderTy &Builder = CGF.getBuilder();
272272
CIRGenModule &CGM = CGF.CGM;
273273
auto CTX = Builder.getContext();
@@ -496,8 +496,8 @@ mlir::LogicalResult CIRGenFunction::emitAsmStmt(const AsmStmt &S) {
496496
mlir::Value Arg;
497497
mlir::Type ArgElemType;
498498
std::tie(Arg, ArgElemType) =
499-
emitAsmInputLValue(Info, Dest, InputExpr->getType(),
500-
InOutConstraints, InputExpr->getExprLoc());
499+
emitAsmInputLValue(Info, Dest, InputExpr->getType(), InOutConstraints,
500+
InputExpr->getExprLoc());
501501

502502
if (mlir::Type AdjTy = getTargetHooks().adjustInlineAsmType(
503503
*this, OutputConstraint, Arg.getType()))
@@ -677,7 +677,7 @@ mlir::LogicalResult CIRGenFunction::emitAsmStmt(const AsmStmt &S) {
677677
auto alignment = CharUnits::One();
678678
auto sname = cast<cir::StructType>(ResultType).getName();
679679
auto dest = emitAlloca(sname, ResultType, getLoc(S.getAsmLoc()),
680-
alignment, false);
680+
alignment, false);
681681
auto addr = Address(dest, alignment);
682682
builder.createStore(getLoc(S.getAsmLoc()), result, addr);
683683

@@ -693,8 +693,8 @@ mlir::LogicalResult CIRGenFunction::emitAsmStmt(const AsmStmt &S) {
693693
}
694694

695695
emitAsmStores(*this, S, RegResults, ResultRegTypes, ResultTruncRegTypes,
696-
ResultRegDests, ResultRegQualTys, ResultTypeRequiresCast,
697-
ResultRegIsFlagReg);
696+
ResultRegDests, ResultRegQualTys, ResultTypeRequiresCast,
697+
ResultRegIsFlagReg);
698698

699699
return mlir::success();
700700
}

‎clang/lib/CIR/CodeGen/CIRGenAtomic.cpp‎

Lines changed: 52 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -265,7 +265,7 @@ static Address emitValToTemp(CIRGenFunction &CGF, Expr *E) {
265265
Address DeclPtr = CGF.CreateMemTemp(
266266
E->getType(), CGF.getLoc(E->getSourceRange()), ".atomictmp");
267267
CGF.emitAnyExprToMem(E, DeclPtr, E->getType().getQualifiers(),
268-
/*Init*/ true);
268+
/*Init*/ true);
269269
return DeclPtr;
270270
}
271271

@@ -383,9 +383,8 @@ static void emitDefaultCase(CIRGenBuilderTy &builder, mlir::Location loc) {
383383
// Create a single "case" label with the given MemOrder as its value. Add the
384384
// "case" label to the given collection of case labels. Create the region that
385385
// will hold the body of the "case" block.
386-
static void emitSingleMemOrderCase(CIRGenBuilderTy &builder,
387-
mlir::Location loc, mlir::Type Type,
388-
cir::MemOrder Order) {
386+
static void emitSingleMemOrderCase(CIRGenBuilderTy &builder, mlir::Location loc,
387+
mlir::Type Type, cir::MemOrder Order) {
389388
SmallVector<mlir::Attribute, 1> OneOrder{
390389
cir::IntAttr::get(Type, static_cast<int>(Order))};
391390
auto OneAttribute = builder.getArrayAttr(OneOrder);
@@ -398,10 +397,9 @@ static void emitSingleMemOrderCase(CIRGenBuilderTy &builder,
398397
// Create a pair of "case" labels with the given MemOrders as their values.
399398
// Add the combined "case" attribute to the given collection of case labels.
400399
// Create the region that will hold the body of the "case" block.
401-
static void emitDoubleMemOrderCase(CIRGenBuilderTy &builder,
402-
mlir::Location loc, mlir::Type Type,
403-
cir::MemOrder Order1,
404-
cir::MemOrder Order2) {
400+
static void emitDoubleMemOrderCase(CIRGenBuilderTy &builder, mlir::Location loc,
401+
mlir::Type Type, cir::MemOrder Order1,
402+
cir::MemOrder Order2) {
405403
SmallVector<mlir::Attribute, 2> TwoOrders{
406404
cir::IntAttr::get(Type, static_cast<int>(Order1)),
407405
cir::IntAttr::get(Type, static_cast<int>(Order2))};
@@ -413,11 +411,11 @@ static void emitDoubleMemOrderCase(CIRGenBuilderTy &builder,
413411
}
414412

415413
static void emitAtomicCmpXchg(CIRGenFunction &CGF, AtomicExpr *E, bool IsWeak,
416-
Address Dest, Address Ptr, Address Val1,
417-
Address Val2, uint64_t Size,
418-
cir::MemOrder SuccessOrder,
419-
cir::MemOrder FailureOrder,
420-
llvm::SyncScope::ID Scope) {
414+
Address Dest, Address Ptr, Address Val1,
415+
Address Val2, uint64_t Size,
416+
cir::MemOrder SuccessOrder,
417+
cir::MemOrder FailureOrder,
418+
llvm::SyncScope::ID Scope) {
421419
auto &builder = CGF.getBuilder();
422420
auto loc = CGF.getLoc(E->getSourceRange());
423421
auto Expected = builder.createLoad(loc, Val1);
@@ -443,7 +441,7 @@ static void emitAtomicCmpXchg(CIRGenFunction &CGF, AtomicExpr *E, bool IsWeak,
443441

444442
// Update the memory at Dest with Cmp's value.
445443
CGF.emitStoreOfScalar(cmpxchg.getCmp(),
446-
CGF.makeAddrLValue(Dest, E->getType()));
444+
CGF.makeAddrLValue(Dest, E->getType()));
447445
}
448446

449447
/// Given an ordering required on success, emit all possible cmpxchg
@@ -483,8 +481,8 @@ static void emitAtomicCmpXchgFailureSet(
483481
// success argument". This condition has been lifted and the only
484482
// precondition is 31.7.2.18. Effectively treat this as a DR and skip
485483
// language version checks.
486-
emitAtomicCmpXchg(CGF, E, IsWeak, Dest, Ptr, Val1, Val2, Size,
487-
SuccessOrder, FailureOrder, Scope);
484+
emitAtomicCmpXchg(CGF, E, IsWeak, Dest, Ptr, Val1, Val2, Size, SuccessOrder,
485+
FailureOrder, Scope);
488486
return;
489487
}
490488

@@ -504,7 +502,7 @@ static void emitAtomicCmpXchgFailureSet(
504502
// because there is no practical way to report an error at runtime.
505503
emitDefaultCase(builder, loc);
506504
emitAtomicCmpXchg(CGF, E, IsWeak, Dest, Ptr, Val1, Val2, Size,
507-
SuccessOrder, cir::MemOrder::Relaxed, Scope);
505+
SuccessOrder, cir::MemOrder::Relaxed, Scope);
508506
builder.createBreak(loc);
509507

510508
builder.setInsertionPointToEnd(switchBlock);
@@ -514,9 +512,9 @@ static void emitAtomicCmpXchgFailureSet(
514512
// memory_order_consume is not implemented and always falls back to
515513
// memory_order_acquire
516514
emitDoubleMemOrderCase(builder, loc, FailureOrderVal.getType(),
517-
cir::MemOrder::Consume, cir::MemOrder::Acquire);
515+
cir::MemOrder::Consume, cir::MemOrder::Acquire);
518516
emitAtomicCmpXchg(CGF, E, IsWeak, Dest, Ptr, Val1, Val2, Size,
519-
SuccessOrder, cir::MemOrder::Acquire, Scope);
517+
SuccessOrder, cir::MemOrder::Acquire, Scope);
520518
builder.createBreak(loc);
521519

522520
builder.setInsertionPointToEnd(switchBlock);
@@ -527,10 +525,10 @@ static void emitAtomicCmpXchgFailureSet(
527525

528526
// case seq_cst:
529527
emitSingleMemOrderCase(builder, loc, FailureOrderVal.getType(),
530-
cir::MemOrder::SequentiallyConsistent);
528+
cir::MemOrder::SequentiallyConsistent);
531529
emitAtomicCmpXchg(CGF, E, IsWeak, Dest, Ptr, Val1, Val2, Size,
532-
SuccessOrder, cir::MemOrder::SequentiallyConsistent,
533-
Scope);
530+
SuccessOrder, cir::MemOrder::SequentiallyConsistent,
531+
Scope);
534532
builder.createBreak(loc);
535533

536534
builder.setInsertionPointToEnd(switchBlock);
@@ -539,9 +537,9 @@ static void emitAtomicCmpXchgFailureSet(
539537
}
540538

541539
static void emitAtomicOp(CIRGenFunction &CGF, AtomicExpr *E, Address Dest,
542-
Address Ptr, Address Val1, Address Val2,
543-
mlir::Value IsWeak, mlir::Value FailureOrder,
544-
uint64_t Size, cir::MemOrder Order, uint8_t Scope) {
540+
Address Ptr, Address Val1, Address Val2,
541+
mlir::Value IsWeak, mlir::Value FailureOrder,
542+
uint64_t Size, cir::MemOrder Order, uint8_t Scope) {
545543
assert(!cir::MissingFeatures::syncScopeID());
546544
StringRef Op;
547545

@@ -560,7 +558,7 @@ static void emitAtomicOp(CIRGenFunction &CGF, AtomicExpr *E, Address Dest,
560558
case AtomicExpr::AO__hip_atomic_compare_exchange_strong:
561559
case AtomicExpr::AO__opencl_atomic_compare_exchange_strong:
562560
emitAtomicCmpXchgFailureSet(CGF, E, false, Dest, Ptr, Val1, Val2,
563-
FailureOrder, Size, Order, Scope);
561+
FailureOrder, Size, Order, Scope);
564562
return;
565563
case AtomicExpr::AO__c11_atomic_compare_exchange_weak:
566564
case AtomicExpr::AO__opencl_atomic_compare_exchange_weak:
@@ -574,7 +572,7 @@ static void emitAtomicOp(CIRGenFunction &CGF, AtomicExpr *E, Address Dest,
574572
bool weakVal;
575573
if (isCstWeak(IsWeak, weakVal)) {
576574
emitAtomicCmpXchgFailureSet(CGF, E, weakVal, Dest, Ptr, Val1, Val2,
577-
FailureOrder, Size, Order, Scope);
575+
FailureOrder, Size, Order, Scope);
578576
} else {
579577
llvm_unreachable("NYI");
580578
}
@@ -770,26 +768,26 @@ static void emitAtomicOp(CIRGenFunction &CGF, AtomicExpr *E, Address Dest,
770768
}
771769

772770
static RValue emitAtomicLibcall(CIRGenFunction &CGF, StringRef fnName,
773-
QualType resultType, CallArgList &args) {
771+
QualType resultType, CallArgList &args) {
774772
[[maybe_unused]] const CIRGenFunctionInfo &fnInfo =
775773
CGF.CGM.getTypes().arrangeBuiltinFunctionCall(resultType, args);
776774
[[maybe_unused]] auto fnTy = CGF.CGM.getTypes().GetFunctionType(fnInfo);
777775
llvm_unreachable("NYI");
778776
}
779777

780778
static void emitAtomicOp(CIRGenFunction &CGF, AtomicExpr *Expr, Address Dest,
781-
Address Ptr, Address Val1, Address Val2,
782-
mlir::Value IsWeak, mlir::Value FailureOrder,
783-
uint64_t Size, cir::MemOrder Order,
784-
mlir::Value Scope) {
779+
Address Ptr, Address Val1, Address Val2,
780+
mlir::Value IsWeak, mlir::Value FailureOrder,
781+
uint64_t Size, cir::MemOrder Order,
782+
mlir::Value Scope) {
785783
auto ScopeModel = Expr->getScopeModel();
786784

787785
// LLVM atomic instructions always have synch scope. If clang atomic
788786
// expression has no scope operand, use default LLVM synch scope.
789787
if (!ScopeModel) {
790788
assert(!cir::MissingFeatures::syncScopeID());
791789
emitAtomicOp(CGF, Expr, Dest, Ptr, Val1, Val2, IsWeak, FailureOrder, Size,
792-
Order, /*FIXME(cir): LLVM default scope*/ 1);
790+
Order, /*FIXME(cir): LLVM default scope*/ 1);
793791
return;
794792
}
795793

@@ -1202,30 +1200,30 @@ RValue CIRGenFunction::emitAtomicExpr(AtomicExpr *E) {
12021200
switch ((cir::MemOrder)ord) {
12031201
case cir::MemOrder::Relaxed:
12041202
emitAtomicOp(*this, E, Dest, Ptr, Val1, Val2, IsWeak, OrderFail, Size,
1205-
cir::MemOrder::Relaxed, Scope);
1203+
cir::MemOrder::Relaxed, Scope);
12061204
break;
12071205
case cir::MemOrder::Consume:
12081206
case cir::MemOrder::Acquire:
12091207
if (IsStore)
12101208
break; // Avoid crashing on code with undefined behavior
12111209
emitAtomicOp(*this, E, Dest, Ptr, Val1, Val2, IsWeak, OrderFail, Size,
1212-
cir::MemOrder::Acquire, Scope);
1210+
cir::MemOrder::Acquire, Scope);
12131211
break;
12141212
case cir::MemOrder::Release:
12151213
if (IsLoad)
12161214
break; // Avoid crashing on code with undefined behavior
12171215
emitAtomicOp(*this, E, Dest, Ptr, Val1, Val2, IsWeak, OrderFail, Size,
1218-
cir::MemOrder::Release, Scope);
1216+
cir::MemOrder::Release, Scope);
12191217
break;
12201218
case cir::MemOrder::AcquireRelease:
12211219
if (IsLoad || IsStore)
12221220
break; // Avoid crashing on code with undefined behavior
12231221
emitAtomicOp(*this, E, Dest, Ptr, Val1, Val2, IsWeak, OrderFail, Size,
1224-
cir::MemOrder::AcquireRelease, Scope);
1222+
cir::MemOrder::AcquireRelease, Scope);
12251223
break;
12261224
case cir::MemOrder::SequentiallyConsistent:
12271225
emitAtomicOp(*this, E, Dest, Ptr, Val1, Val2, IsWeak, OrderFail, Size,
1228-
cir::MemOrder::SequentiallyConsistent, Scope);
1226+
cir::MemOrder::SequentiallyConsistent, Scope);
12291227
break;
12301228
}
12311229
}
@@ -1252,7 +1250,7 @@ RValue CIRGenFunction::emitAtomicExpr(AtomicExpr *E) {
12521250
// memory_order_relaxed.
12531251
emitDefaultCase(builder, loc);
12541252
emitAtomicOp(*this, E, Dest, Ptr, Val1, Val2, IsWeak, OrderFail, Size,
1255-
cir::MemOrder::Relaxed, Scope);
1253+
cir::MemOrder::Relaxed, Scope);
12561254
builder.createBreak(loc);
12571255

12581256
builder.setInsertionPointToEnd(switchBlock);
@@ -1264,10 +1262,10 @@ RValue CIRGenFunction::emitAtomicExpr(AtomicExpr *E) {
12641262
// memory_order_acquire. These memory orders are not valid for
12651263
// write-only operations.
12661264
emitDoubleMemOrderCase(builder, loc, Order.getType(),
1267-
cir::MemOrder::Consume,
1268-
cir::MemOrder::Acquire);
1269-
emitAtomicOp(*this, E, Dest, Ptr, Val1, Val2, IsWeak, OrderFail,
1270-
Size, cir::MemOrder::Acquire, Scope);
1265+
cir::MemOrder::Consume,
1266+
cir::MemOrder::Acquire);
1267+
emitAtomicOp(*this, E, Dest, Ptr, Val1, Val2, IsWeak, OrderFail, Size,
1268+
cir::MemOrder::Acquire, Scope);
12711269
builder.createBreak(loc);
12721270
}
12731271

@@ -1277,9 +1275,9 @@ RValue CIRGenFunction::emitAtomicExpr(AtomicExpr *E) {
12771275
// case release:
12781276
// memory_order_release is not valid for read-only operations.
12791277
emitSingleMemOrderCase(builder, loc, Order.getType(),
1280-
cir::MemOrder::Release);
1281-
emitAtomicOp(*this, E, Dest, Ptr, Val1, Val2, IsWeak, OrderFail,
1282-
Size, cir::MemOrder::Release, Scope);
1278+
cir::MemOrder::Release);
1279+
emitAtomicOp(*this, E, Dest, Ptr, Val1, Val2, IsWeak, OrderFail, Size,
1280+
cir::MemOrder::Release, Scope);
12831281
builder.createBreak(loc);
12841282
}
12851283

@@ -1289,19 +1287,19 @@ RValue CIRGenFunction::emitAtomicExpr(AtomicExpr *E) {
12891287
// case acq_rel:
12901288
// memory_order_acq_rel is only valid for read-write operations.
12911289
emitSingleMemOrderCase(builder, loc, Order.getType(),
1292-
cir::MemOrder::AcquireRelease);
1293-
emitAtomicOp(*this, E, Dest, Ptr, Val1, Val2, IsWeak, OrderFail,
1294-
Size, cir::MemOrder::AcquireRelease, Scope);
1290+
cir::MemOrder::AcquireRelease);
1291+
emitAtomicOp(*this, E, Dest, Ptr, Val1, Val2, IsWeak, OrderFail, Size,
1292+
cir::MemOrder::AcquireRelease, Scope);
12951293
builder.createBreak(loc);
12961294
}
12971295

12981296
builder.setInsertionPointToEnd(switchBlock);
12991297

13001298
// case seq_cst:
13011299
emitSingleMemOrderCase(builder, loc, Order.getType(),
1302-
cir::MemOrder::SequentiallyConsistent);
1300+
cir::MemOrder::SequentiallyConsistent);
13031301
emitAtomicOp(*this, E, Dest, Ptr, Val1, Val2, IsWeak, OrderFail, Size,
1304-
cir::MemOrder::SequentiallyConsistent, Scope);
1302+
cir::MemOrder::SequentiallyConsistent, Scope);
13051303
builder.createBreak(loc);
13061304

13071305
builder.setInsertionPointToEnd(switchBlock);
@@ -1315,7 +1313,7 @@ RValue CIRGenFunction::emitAtomicExpr(AtomicExpr *E) {
13151313
}
13161314

13171315
void CIRGenFunction::emitAtomicStore(RValue rvalue, LValue lvalue,
1318-
bool isInit) {
1316+
bool isInit) {
13191317
bool IsVolatile = lvalue.isVolatileQualified();
13201318
cir::MemOrder MO;
13211319
if (lvalue.getType()->isAtomicType()) {
@@ -1416,8 +1414,8 @@ mlir::Value AtomicInfo::convertRValueToInt(RValue RVal, bool CmpXchg) const {
14161414
/// type*; this means that for aggregate r-values, it should include
14171415
/// storage for any padding that was necessary.
14181416
void CIRGenFunction::emitAtomicStore(RValue rvalue, LValue dest,
1419-
cir::MemOrder MO, bool IsVolatile,
1420-
bool isInit) {
1417+
cir::MemOrder MO, bool IsVolatile,
1418+
bool isInit) {
14211419
// If this is an aggregate r-value, it should agree in type except
14221420
// maybe for address-space qualification.
14231421
auto loc = dest.getPointer().getLoc();

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