diff --git a/clang/lib/CIR/CodeGen/CIRGenBuilder.h b/clang/lib/CIR/CodeGen/CIRGenBuilder.h index 1734f450d303..4c182bbaa036 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuilder.h +++ b/clang/lib/CIR/CodeGen/CIRGenBuilder.h @@ -372,6 +372,28 @@ class CIRGenBuilderTy : public CIRBaseBuilderTy { } bool isInt(mlir::Type i) { return mlir::isa(i); } + mlir::cir::IntType getExtendedIntTy(mlir::cir::IntType ty, bool isSigned) { + if (isInt8Ty(ty)) { + return isSigned ? getSInt16Ty() : getUInt16Ty(); + } + if (isInt16Ty(ty)) { + return isSigned ? getSInt32Ty() : getUInt32Ty(); + } + if (isInt32Ty(ty)) { + return isSigned ? getSInt64Ty() : getUInt64Ty(); + } + llvm_unreachable("NYI"); + } + + mlir::cir::VectorType getExtendedElementVectorType(mlir::cir::VectorType vt, + bool isSigned = false) { + auto elementTy = + mlir::dyn_cast_or_null(vt.getEltType()); + assert(elementTy && "expected int vector"); + return mlir::cir::VectorType::get( + getContext(), getExtendedIntTy(elementTy, isSigned), vt.getSize()); + } + mlir::cir::LongDoubleType getLongDoubleTy(const llvm::fltSemantics &format) const { if (&format == &llvm::APFloat::IEEEdouble()) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index c15ea99584f0..6ab3b8ea6a98 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -693,6 +693,559 @@ static const ARMVectorIntrinsicInfo AArch64SISDIntrinsicMap[] = { NEONMAP1(vrsqrtsh_f16, aarch64_neon_frsqrts, Add1ArgType), }; +/// Get name of intrinsics in the AArch64SIMDIntrinsicMap defined above. +static std::string getAArch64SIMDIntrinsicString(unsigned int intrinsicID) { + switch (intrinsicID) { + default: + return std::string("Unexpected intrinsic id " + + std::to_string(intrinsicID)); + case NEON::BI__builtin_neon___a64_vcvtq_low_bf16_f32: + return "NEON::BI__builtin_neon___a64_vcvtq_low_bf16_f32"; + case NEON::BI__builtin_neon_splat_lane_v: + return "NEON::BI__builtin_neon_splat_lane_v"; + case NEON::BI__builtin_neon_splat_laneq_v: + return "NEON::BI__builtin_neon_splat_laneq_v"; + case NEON::BI__builtin_neon_splatq_lane_v: + return "NEON::BI__builtin_neon_splatq_lane_v"; + case NEON::BI__builtin_neon_splatq_laneq_v: + return "NEON::BI__builtin_neon_splatq_laneq_v"; + case NEON::BI__builtin_neon_vabs_v: + return "NEON::BI__builtin_neon_vabs_v"; + case NEON::BI__builtin_neon_vabsq_v: + return "NEON::BI__builtin_neon_vabsq_v"; + case NEON::BI__builtin_neon_vadd_v: + return "NEON::BI__builtin_neon_vadd_v"; + case NEON::BI__builtin_neon_vaddhn_v: + return "NEON::BI__builtin_neon_vaddhn_v"; + case NEON::BI__builtin_neon_vaddq_p128: + return "NEON::BI__builtin_neon_vaddq_p128"; + case NEON::BI__builtin_neon_vaddq_v: + return "NEON::BI__builtin_neon_vaddq_v"; + case NEON::BI__builtin_neon_vaesdq_u8: + return "NEON::BI__builtin_neon_vaesdq_u8"; + case NEON::BI__builtin_neon_vaeseq_u8: + return "NEON::BI__builtin_neon_vaeseq_u8"; + case NEON::BI__builtin_neon_vaesimcq_u8: + return "NEON::BI__builtin_neon_vaesimcq_u8"; + case NEON::BI__builtin_neon_vaesmcq_u8: + return "NEON::BI__builtin_neon_vaesmcq_u8"; + case NEON::BI__builtin_neon_vbcaxq_s16: + return "NEON::BI__builtin_neon_vbcaxq_s16"; + case NEON::BI__builtin_neon_vbcaxq_s32: + return "NEON::BI__builtin_neon_vbcaxq_s32"; + case NEON::BI__builtin_neon_vbcaxq_s64: + return "NEON::BI__builtin_neon_vbcaxq_s64"; + case NEON::BI__builtin_neon_vbcaxq_s8: + return "NEON::BI__builtin_neon_vbcaxq_s8"; + case NEON::BI__builtin_neon_vbcaxq_u16: + return "NEON::BI__builtin_neon_vbcaxq_u16"; + case NEON::BI__builtin_neon_vbcaxq_u32: + return "NEON::BI__builtin_neon_vbcaxq_u32"; + case NEON::BI__builtin_neon_vbcaxq_u64: + return "NEON::BI__builtin_neon_vbcaxq_u64"; + case NEON::BI__builtin_neon_vbcaxq_u8: + return "NEON::BI__builtin_neon_vbcaxq_u8"; + case NEON::BI__builtin_neon_vbfdot_f32: + return "NEON::BI__builtin_neon_vbfdot_f32"; + case NEON::BI__builtin_neon_vbfdotq_f32: + return "NEON::BI__builtin_neon_vbfdotq_f32"; + case NEON::BI__builtin_neon_vbfmlalbq_f32: + return "NEON::BI__builtin_neon_vbfmlalbq_f32"; + case NEON::BI__builtin_neon_vbfmlaltq_f32: + return "NEON::BI__builtin_neon_vbfmlaltq_f32"; + case NEON::BI__builtin_neon_vbfmmlaq_f32: + return "NEON::BI__builtin_neon_vbfmmlaq_f32"; + case NEON::BI__builtin_neon_vcadd_rot270_f16: + return "NEON::BI__builtin_neon_vcadd_rot270_f16"; + case NEON::BI__builtin_neon_vcadd_rot270_f32: + return "NEON::BI__builtin_neon_vcadd_rot270_f32"; + case NEON::BI__builtin_neon_vcadd_rot90_f16: + return "NEON::BI__builtin_neon_vcadd_rot90_f16"; + case NEON::BI__builtin_neon_vcadd_rot90_f32: + return "NEON::BI__builtin_neon_vcadd_rot90_f32"; + case NEON::BI__builtin_neon_vcaddq_rot270_f16: + return "NEON::BI__builtin_neon_vcaddq_rot270_f16"; + case NEON::BI__builtin_neon_vcaddq_rot270_f32: + return "NEON::BI__builtin_neon_vcaddq_rot270_f32"; + case NEON::BI__builtin_neon_vcaddq_rot270_f64: + return "NEON::BI__builtin_neon_vcaddq_rot270_f64"; + case NEON::BI__builtin_neon_vcaddq_rot90_f16: + return "NEON::BI__builtin_neon_vcaddq_rot90_f16"; + case NEON::BI__builtin_neon_vcaddq_rot90_f32: + return "NEON::BI__builtin_neon_vcaddq_rot90_f32"; + case NEON::BI__builtin_neon_vcaddq_rot90_f64: + return "NEON::BI__builtin_neon_vcaddq_rot90_f64"; + case NEON::BI__builtin_neon_vcage_v: + return "NEON::BI__builtin_neon_vcage_v"; + case NEON::BI__builtin_neon_vcageq_v: + return "NEON::BI__builtin_neon_vcageq_v"; + case NEON::BI__builtin_neon_vcagt_v: + return "NEON::BI__builtin_neon_vcagt_v"; + case NEON::BI__builtin_neon_vcagtq_v: + return "NEON::BI__builtin_neon_vcagtq_v"; + case NEON::BI__builtin_neon_vcale_v: + return "NEON::BI__builtin_neon_vcale_v"; + case NEON::BI__builtin_neon_vcaleq_v: + return "NEON::BI__builtin_neon_vcaleq_v"; + case NEON::BI__builtin_neon_vcalt_v: + return "NEON::BI__builtin_neon_vcalt_v"; + case NEON::BI__builtin_neon_vcaltq_v: + return "NEON::BI__builtin_neon_vcaltq_v"; + case NEON::BI__builtin_neon_vceqz_v: + return "NEON::BI__builtin_neon_vceqz_v"; + case NEON::BI__builtin_neon_vceqzq_v: + return "NEON::BI__builtin_neon_vceqzq_v"; + case NEON::BI__builtin_neon_vcgez_v: + return "NEON::BI__builtin_neon_vcgez_v"; + case NEON::BI__builtin_neon_vcgezq_v: + return "NEON::BI__builtin_neon_vcgezq_v"; + case NEON::BI__builtin_neon_vcgtz_v: + return "NEON::BI__builtin_neon_vcgtz_v"; + case NEON::BI__builtin_neon_vcgtzq_v: + return "NEON::BI__builtin_neon_vcgtzq_v"; + case NEON::BI__builtin_neon_vclez_v: + return "NEON::BI__builtin_neon_vclez_v"; + case NEON::BI__builtin_neon_vclezq_v: + return "NEON::BI__builtin_neon_vclezq_v"; + case NEON::BI__builtin_neon_vcls_v: + return "NEON::BI__builtin_neon_vcls_v"; + case NEON::BI__builtin_neon_vclsq_v: + return "NEON::BI__builtin_neon_vclsq_v"; + case NEON::BI__builtin_neon_vcltz_v: + return "NEON::BI__builtin_neon_vcltz_v"; + case NEON::BI__builtin_neon_vcltzq_v: + return "NEON::BI__builtin_neon_vcltzq_v"; + case NEON::BI__builtin_neon_vclz_v: + return "NEON::BI__builtin_neon_vclz_v"; + case NEON::BI__builtin_neon_vclzq_v: + return "NEON::BI__builtin_neon_vclzq_v"; + case NEON::BI__builtin_neon_vcmla_f16: + return "NEON::BI__builtin_neon_vcmla_f16"; + case NEON::BI__builtin_neon_vcmla_f32: + return "NEON::BI__builtin_neon_vcmla_f32"; + case NEON::BI__builtin_neon_vcmla_rot180_f16: + return "NEON::BI__builtin_neon_vcmla_rot180_f16"; + case NEON::BI__builtin_neon_vcmla_rot180_f32: + return "NEON::BI__builtin_neon_vcmla_rot180_f32"; + case NEON::BI__builtin_neon_vcmla_rot270_f16: + return "NEON::BI__builtin_neon_vcmla_rot270_f16"; + case NEON::BI__builtin_neon_vcmla_rot270_f32: + return "NEON::BI__builtin_neon_vcmla_rot270_f32"; + case NEON::BI__builtin_neon_vcmla_rot90_f16: + return "NEON::BI__builtin_neon_vcmla_rot90_f16"; + case NEON::BI__builtin_neon_vcmla_rot90_f32: + return "NEON::BI__builtin_neon_vcmla_rot90_f32"; + case NEON::BI__builtin_neon_vcmlaq_f16: + return "NEON::BI__builtin_neon_vcmlaq_f16"; + case NEON::BI__builtin_neon_vcmlaq_f32: + return "NEON::BI__builtin_neon_vcmlaq_f32"; + case NEON::BI__builtin_neon_vcmlaq_f64: + return "NEON::BI__builtin_neon_vcmlaq_f64"; + case NEON::BI__builtin_neon_vcmlaq_rot180_f16: + return "NEON::BI__builtin_neon_vcmlaq_rot180_f16"; + case NEON::BI__builtin_neon_vcmlaq_rot180_f32: + return "NEON::BI__builtin_neon_vcmlaq_rot180_f32"; + case NEON::BI__builtin_neon_vcmlaq_rot180_f64: + return "NEON::BI__builtin_neon_vcmlaq_rot180_f64"; + case NEON::BI__builtin_neon_vcmlaq_rot270_f16: + return "NEON::BI__builtin_neon_vcmlaq_rot270_f16"; + case NEON::BI__builtin_neon_vcmlaq_rot270_f32: + return "NEON::BI__builtin_neon_vcmlaq_rot270_f32"; + case NEON::BI__builtin_neon_vcmlaq_rot270_f64: + return "NEON::BI__builtin_neon_vcmlaq_rot270_f64"; + case NEON::BI__builtin_neon_vcmlaq_rot90_f16: + return "NEON::BI__builtin_neon_vcmlaq_rot90_f16"; + case NEON::BI__builtin_neon_vcmlaq_rot90_f32: + return "NEON::BI__builtin_neon_vcmlaq_rot90_f32"; + case NEON::BI__builtin_neon_vcmlaq_rot90_f64: + return "NEON::BI__builtin_neon_vcmlaq_rot90_f64"; + case NEON::BI__builtin_neon_vcnt_v: + return "NEON::BI__builtin_neon_vcnt_v"; + case NEON::BI__builtin_neon_vcntq_v: + return "NEON::BI__builtin_neon_vcntq_v"; + case NEON::BI__builtin_neon_vcvt_f16_f32: + return "NEON::BI__builtin_neon_vcvt_f16_f32"; + case NEON::BI__builtin_neon_vcvt_f16_s16: + return "NEON::BI__builtin_neon_vcvt_f16_s16"; + case NEON::BI__builtin_neon_vcvt_f16_u16: + return "NEON::BI__builtin_neon_vcvt_f16_u16"; + case NEON::BI__builtin_neon_vcvt_f32_f16: + return "NEON::BI__builtin_neon_vcvt_f32_f16"; + case NEON::BI__builtin_neon_vcvt_f32_v: + return "NEON::BI__builtin_neon_vcvt_f32_v"; + case NEON::BI__builtin_neon_vcvt_n_f16_s16: + return "NEON::BI__builtin_neon_vcvt_n_f16_s16"; + case NEON::BI__builtin_neon_vcvt_n_f16_u16: + return "NEON::BI__builtin_neon_vcvt_n_f16_u16"; + case NEON::BI__builtin_neon_vcvt_n_f32_v: + return "NEON::BI__builtin_neon_vcvt_n_f32_v"; + case NEON::BI__builtin_neon_vcvt_n_f64_v: + return "NEON::BI__builtin_neon_vcvt_n_f64_v"; + case NEON::BI__builtin_neon_vcvt_n_s16_f16: + return "NEON::BI__builtin_neon_vcvt_n_s16_f16"; + case NEON::BI__builtin_neon_vcvt_n_s32_v: + return "NEON::BI__builtin_neon_vcvt_n_s32_v"; + case NEON::BI__builtin_neon_vcvt_n_s64_v: + return "NEON::BI__builtin_neon_vcvt_n_s64_v"; + case NEON::BI__builtin_neon_vcvt_n_u16_f16: + return "NEON::BI__builtin_neon_vcvt_n_u16_f16"; + case NEON::BI__builtin_neon_vcvt_n_u32_v: + return "NEON::BI__builtin_neon_vcvt_n_u32_v"; + case NEON::BI__builtin_neon_vcvt_n_u64_v: + return "NEON::BI__builtin_neon_vcvt_n_u64_v"; + case NEON::BI__builtin_neon_vcvtq_f16_s16: + return "NEON::BI__builtin_neon_vcvtq_f16_s16"; + case NEON::BI__builtin_neon_vcvtq_f16_u16: + return "NEON::BI__builtin_neon_vcvtq_f16_u16"; + case NEON::BI__builtin_neon_vcvtq_f32_v: + return "NEON::BI__builtin_neon_vcvtq_f32_v"; + case NEON::BI__builtin_neon_vcvtq_high_bf16_f32: + return "NEON::BI__builtin_neon_vcvtq_high_bf16_f32"; + case NEON::BI__builtin_neon_vcvtq_n_f16_s16: + return "NEON::BI__builtin_neon_vcvtq_n_f16_s16"; + case NEON::BI__builtin_neon_vcvtq_n_f16_u16: + return "NEON::BI__builtin_neon_vcvtq_n_f16_u16"; + case NEON::BI__builtin_neon_vcvtq_n_f32_v: + return "NEON::BI__builtin_neon_vcvtq_n_f32_v"; + case NEON::BI__builtin_neon_vcvtq_n_f64_v: + return "NEON::BI__builtin_neon_vcvtq_n_f64_v"; + case NEON::BI__builtin_neon_vcvtq_n_s16_f16: + return "NEON::BI__builtin_neon_vcvtq_n_s16_f16"; + case NEON::BI__builtin_neon_vcvtq_n_s32_v: + return "NEON::BI__builtin_neon_vcvtq_n_s32_v"; + case NEON::BI__builtin_neon_vcvtq_n_s64_v: + return "NEON::BI__builtin_neon_vcvtq_n_s64_v"; + case NEON::BI__builtin_neon_vcvtq_n_u16_f16: + return "NEON::BI__builtin_neon_vcvtq_n_u16_f16"; + case NEON::BI__builtin_neon_vcvtq_n_u32_v: + return "NEON::BI__builtin_neon_vcvtq_n_u32_v"; + case NEON::BI__builtin_neon_vcvtq_n_u64_v: + return "NEON::BI__builtin_neon_vcvtq_n_u64_v"; + case NEON::BI__builtin_neon_vcvtx_f32_v: + return "NEON::BI__builtin_neon_vcvtx_f32_v"; + case NEON::BI__builtin_neon_vdot_s32: + return "NEON::BI__builtin_neon_vdot_s32"; + case NEON::BI__builtin_neon_vdot_u32: + return "NEON::BI__builtin_neon_vdot_u32"; + case NEON::BI__builtin_neon_vdotq_s32: + return "NEON::BI__builtin_neon_vdotq_s32"; + case NEON::BI__builtin_neon_vdotq_u32: + return "NEON::BI__builtin_neon_vdotq_u32"; + case NEON::BI__builtin_neon_veor3q_s16: + return "NEON::BI__builtin_neon_veor3q_s16"; + case NEON::BI__builtin_neon_veor3q_s32: + return "NEON::BI__builtin_neon_veor3q_s32"; + case NEON::BI__builtin_neon_veor3q_s64: + return "NEON::BI__builtin_neon_veor3q_s64"; + case NEON::BI__builtin_neon_veor3q_s8: + return "NEON::BI__builtin_neon_veor3q_s8"; + case NEON::BI__builtin_neon_veor3q_u16: + return "NEON::BI__builtin_neon_veor3q_u16"; + case NEON::BI__builtin_neon_veor3q_u32: + return "NEON::BI__builtin_neon_veor3q_u32"; + case NEON::BI__builtin_neon_veor3q_u64: + return "NEON::BI__builtin_neon_veor3q_u64"; + case NEON::BI__builtin_neon_veor3q_u8: + return "NEON::BI__builtin_neon_veor3q_u8"; + case NEON::BI__builtin_neon_vext_v: + return "NEON::BI__builtin_neon_vext_v"; + case NEON::BI__builtin_neon_vextq_v: + return "NEON::BI__builtin_neon_vextq_v"; + case NEON::BI__builtin_neon_vfma_v: + return "NEON::BI__builtin_neon_vfma_v"; + case NEON::BI__builtin_neon_vfmaq_v: + return "NEON::BI__builtin_neon_vfmaq_v"; + case NEON::BI__builtin_neon_vfmlal_high_f16: + return "NEON::BI__builtin_neon_vfmlal_high_f16"; + case NEON::BI__builtin_neon_vfmlal_low_f16: + return "NEON::BI__builtin_neon_vfmlal_low_f16"; + case NEON::BI__builtin_neon_vfmlalq_high_f16: + return "NEON::BI__builtin_neon_vfmlalq_high_f16"; + case NEON::BI__builtin_neon_vfmlalq_low_f16: + return "NEON::BI__builtin_neon_vfmlalq_low_f16"; + case NEON::BI__builtin_neon_vfmlsl_high_f16: + return "NEON::BI__builtin_neon_vfmlsl_high_f16"; + case NEON::BI__builtin_neon_vfmlsl_low_f16: + return "NEON::BI__builtin_neon_vfmlsl_low_f16"; + case NEON::BI__builtin_neon_vfmlslq_high_f16: + return "NEON::BI__builtin_neon_vfmlslq_high_f16"; + case NEON::BI__builtin_neon_vfmlslq_low_f16: + return "NEON::BI__builtin_neon_vfmlslq_low_f16"; + case NEON::BI__builtin_neon_vhadd_v: + return "NEON::BI__builtin_neon_vhadd_v"; + case NEON::BI__builtin_neon_vhaddq_v: + return "NEON::BI__builtin_neon_vhaddq_v"; + case NEON::BI__builtin_neon_vhsub_v: + return "NEON::BI__builtin_neon_vhsub_v"; + case NEON::BI__builtin_neon_vhsubq_v: + return "NEON::BI__builtin_neon_vhsubq_v"; + case NEON::BI__builtin_neon_vld1_x2_v: + return "NEON::BI__builtin_neon_vld1_x2_v"; + case NEON::BI__builtin_neon_vld1_x3_v: + return "NEON::BI__builtin_neon_vld1_x3_v"; + case NEON::BI__builtin_neon_vld1_x4_v: + return "NEON::BI__builtin_neon_vld1_x4_v"; + case NEON::BI__builtin_neon_vld1q_x2_v: + return "NEON::BI__builtin_neon_vld1q_x2_v"; + case NEON::BI__builtin_neon_vld1q_x3_v: + return "NEON::BI__builtin_neon_vld1q_x3_v"; + case NEON::BI__builtin_neon_vld1q_x4_v: + return "NEON::BI__builtin_neon_vld1q_x4_v"; + case NEON::BI__builtin_neon_vmmlaq_s32: + return "NEON::BI__builtin_neon_vmmlaq_s32"; + case NEON::BI__builtin_neon_vmmlaq_u32: + return "NEON::BI__builtin_neon_vmmlaq_u32"; + case NEON::BI__builtin_neon_vmovl_v: + return "NEON::BI__builtin_neon_vmovl_v"; + case NEON::BI__builtin_neon_vmovn_v: + return "NEON::BI__builtin_neon_vmovn_v"; + case NEON::BI__builtin_neon_vmul_v: + return "NEON::BI__builtin_neon_vmul_v"; + case NEON::BI__builtin_neon_vmulq_v: + return "NEON::BI__builtin_neon_vmulq_v"; + case NEON::BI__builtin_neon_vpadd_v: + return "NEON::BI__builtin_neon_vpadd_v"; + case NEON::BI__builtin_neon_vpaddl_v: + return "NEON::BI__builtin_neon_vpaddl_v"; + case NEON::BI__builtin_neon_vpaddlq_v: + return "NEON::BI__builtin_neon_vpaddlq_v"; + case NEON::BI__builtin_neon_vpaddq_v: + return "NEON::BI__builtin_neon_vpaddq_v"; + case NEON::BI__builtin_neon_vqabs_v: + return "NEON::BI__builtin_neon_vqabs_v"; + case NEON::BI__builtin_neon_vqabsq_v: + return "NEON::BI__builtin_neon_vqabsq_v"; + case NEON::BI__builtin_neon_vqadd_v: + return "NEON::BI__builtin_neon_vqadd_v"; + case NEON::BI__builtin_neon_vqaddq_v: + return "NEON::BI__builtin_neon_vqaddq_v"; + case NEON::BI__builtin_neon_vqdmlal_v: + return "NEON::BI__builtin_neon_vqdmlal_v"; + case NEON::BI__builtin_neon_vqdmlsl_v: + return "NEON::BI__builtin_neon_vqdmlsl_v"; + case NEON::BI__builtin_neon_vqdmulh_lane_v: + return "NEON::BI__builtin_neon_vqdmulh_lane_v"; + case NEON::BI__builtin_neon_vqdmulh_laneq_v: + return "NEON::BI__builtin_neon_vqdmulh_laneq_v"; + case NEON::BI__builtin_neon_vqdmulh_v: + return "NEON::BI__builtin_neon_vqdmulh_v"; + case NEON::BI__builtin_neon_vqdmulhq_lane_v: + return "NEON::BI__builtin_neon_vqdmulhq_lane_v"; + case NEON::BI__builtin_neon_vqdmulhq_laneq_v: + return "NEON::BI__builtin_neon_vqdmulhq_laneq_v"; + case NEON::BI__builtin_neon_vqdmulhq_v: + return "NEON::BI__builtin_neon_vqdmulhq_v"; + case NEON::BI__builtin_neon_vqdmull_v: + return "NEON::BI__builtin_neon_vqdmull_v"; + case NEON::BI__builtin_neon_vqmovn_v: + return "NEON::BI__builtin_neon_vqmovn_v"; + case NEON::BI__builtin_neon_vqmovun_v: + return "NEON::BI__builtin_neon_vqmovun_v"; + case NEON::BI__builtin_neon_vqneg_v: + return "NEON::BI__builtin_neon_vqneg_v"; + case NEON::BI__builtin_neon_vqnegq_v: + return "NEON::BI__builtin_neon_vqnegq_v"; + case NEON::BI__builtin_neon_vqrdmlah_s16: + return "NEON::BI__builtin_neon_vqrdmlah_s16"; + case NEON::BI__builtin_neon_vqrdmlah_s32: + return "NEON::BI__builtin_neon_vqrdmlah_s32"; + case NEON::BI__builtin_neon_vqrdmlahq_s16: + return "NEON::BI__builtin_neon_vqrdmlahq_s16"; + case NEON::BI__builtin_neon_vqrdmlahq_s32: + return "NEON::BI__builtin_neon_vqrdmlahq_s32"; + case NEON::BI__builtin_neon_vqrdmlsh_s16: + return "NEON::BI__builtin_neon_vqrdmlsh_s16"; + case NEON::BI__builtin_neon_vqrdmlsh_s32: + return "NEON::BI__builtin_neon_vqrdmlsh_s32"; + case NEON::BI__builtin_neon_vqrdmlshq_s16: + return "NEON::BI__builtin_neon_vqrdmlshq_s16"; + case NEON::BI__builtin_neon_vqrdmlshq_s32: + return "NEON::BI__builtin_neon_vqrdmlshq_s32"; + case NEON::BI__builtin_neon_vqrdmulh_lane_v: + return "NEON::BI__builtin_neon_vqrdmulh_lane_v"; + case NEON::BI__builtin_neon_vqrdmulh_laneq_v: + return "NEON::BI__builtin_neon_vqrdmulh_laneq_v"; + case NEON::BI__builtin_neon_vqrdmulh_v: + return "NEON::BI__builtin_neon_vqrdmulh_v"; + case NEON::BI__builtin_neon_vqrdmulhq_lane_v: + return "NEON::BI__builtin_neon_vqrdmulhq_lane_v"; + case NEON::BI__builtin_neon_vqrdmulhq_laneq_v: + return "NEON::BI__builtin_neon_vqrdmulhq_laneq_v"; + case NEON::BI__builtin_neon_vqrdmulhq_v: + return "NEON::BI__builtin_neon_vqrdmulhq_v"; + case NEON::BI__builtin_neon_vqrshl_v: + return "NEON::BI__builtin_neon_vqrshl_v"; + case NEON::BI__builtin_neon_vqrshlq_v: + return "NEON::BI__builtin_neon_vqrshlq_v"; + case NEON::BI__builtin_neon_vqshl_n_v: + return "NEON::BI__builtin_neon_vqshl_n_v"; + case NEON::BI__builtin_neon_vqshl_v: + return "NEON::BI__builtin_neon_vqshl_v"; + case NEON::BI__builtin_neon_vqshlq_n_v: + return "NEON::BI__builtin_neon_vqshlq_n_v"; + case NEON::BI__builtin_neon_vqshlq_v: + return "NEON::BI__builtin_neon_vqshlq_v"; + case NEON::BI__builtin_neon_vqshlu_n_v: + return "NEON::BI__builtin_neon_vqshlu_n_v"; + case NEON::BI__builtin_neon_vqshluq_n_v: + return "NEON::BI__builtin_neon_vqshluq_n_v"; + case NEON::BI__builtin_neon_vqsub_v: + return "NEON::BI__builtin_neon_vqsub_v"; + case NEON::BI__builtin_neon_vqsubq_v: + return "NEON::BI__builtin_neon_vqsubq_v"; + case NEON::BI__builtin_neon_vraddhn_v: + return "NEON::BI__builtin_neon_vraddhn_v"; + case NEON::BI__builtin_neon_vrax1q_u64: + return "NEON::BI__builtin_neon_vrax1q_u64"; + case NEON::BI__builtin_neon_vrecpe_v: + return "NEON::BI__builtin_neon_vrecpe_v"; + case NEON::BI__builtin_neon_vrecpeq_v: + return "NEON::BI__builtin_neon_vrecpeq_v"; + case NEON::BI__builtin_neon_vrecps_v: + return "NEON::BI__builtin_neon_vrecps_v"; + case NEON::BI__builtin_neon_vrecpsq_v: + return "NEON::BI__builtin_neon_vrecpsq_v"; + case NEON::BI__builtin_neon_vrhadd_v: + return "NEON::BI__builtin_neon_vrhadd_v"; + case NEON::BI__builtin_neon_vrhaddq_v: + return "NEON::BI__builtin_neon_vrhaddq_v"; + case NEON::BI__builtin_neon_vrnd32x_f32: + return "NEON::BI__builtin_neon_vrnd32x_f32"; + case NEON::BI__builtin_neon_vrnd32x_f64: + return "NEON::BI__builtin_neon_vrnd32x_f64"; + case NEON::BI__builtin_neon_vrnd32xq_f32: + return "NEON::BI__builtin_neon_vrnd32xq_f32"; + case NEON::BI__builtin_neon_vrnd32xq_f64: + return "NEON::BI__builtin_neon_vrnd32xq_f64"; + case NEON::BI__builtin_neon_vrnd32z_f32: + return "NEON::BI__builtin_neon_vrnd32z_f32"; + case NEON::BI__builtin_neon_vrnd32z_f64: + return "NEON::BI__builtin_neon_vrnd32z_f64"; + case NEON::BI__builtin_neon_vrnd32zq_f32: + return "NEON::BI__builtin_neon_vrnd32zq_f32"; + case NEON::BI__builtin_neon_vrnd32zq_f64: + return "NEON::BI__builtin_neon_vrnd32zq_f64"; + case NEON::BI__builtin_neon_vrnd64x_f32: + return "NEON::BI__builtin_neon_vrnd64x_f32"; + case NEON::BI__builtin_neon_vrnd64x_f64: + return "NEON::BI__builtin_neon_vrnd64x_f64"; + case NEON::BI__builtin_neon_vrnd64xq_f32: + return "NEON::BI__builtin_neon_vrnd64xq_f32"; + case NEON::BI__builtin_neon_vrnd64xq_f64: + return "NEON::BI__builtin_neon_vrnd64xq_f64"; + case NEON::BI__builtin_neon_vrnd64z_f32: + return "NEON::BI__builtin_neon_vrnd64z_f32"; + case NEON::BI__builtin_neon_vrnd64z_f64: + return "NEON::BI__builtin_neon_vrnd64z_f64"; + case NEON::BI__builtin_neon_vrnd64zq_f32: + return "NEON::BI__builtin_neon_vrnd64zq_f32"; + case NEON::BI__builtin_neon_vrnd64zq_f64: + return "NEON::BI__builtin_neon_vrnd64zq_f64"; + case NEON::BI__builtin_neon_vrndi_v: + return "NEON::BI__builtin_neon_vrndi_v"; + case NEON::BI__builtin_neon_vrndiq_v: + return "NEON::BI__builtin_neon_vrndiq_v"; + case NEON::BI__builtin_neon_vrshl_v: + return "NEON::BI__builtin_neon_vrshl_v"; + case NEON::BI__builtin_neon_vrshlq_v: + return "NEON::BI__builtin_neon_vrshlq_v"; + case NEON::BI__builtin_neon_vrshr_n_v: + return "NEON::BI__builtin_neon_vrshr_n_v"; + case NEON::BI__builtin_neon_vrshrq_n_v: + return "NEON::BI__builtin_neon_vrshrq_n_v"; + case NEON::BI__builtin_neon_vrsqrte_v: + return "NEON::BI__builtin_neon_vrsqrte_v"; + case NEON::BI__builtin_neon_vrsqrteq_v: + return "NEON::BI__builtin_neon_vrsqrteq_v"; + case NEON::BI__builtin_neon_vrsqrts_v: + return "NEON::BI__builtin_neon_vrsqrts_v"; + case NEON::BI__builtin_neon_vrsqrtsq_v: + return "NEON::BI__builtin_neon_vrsqrtsq_v"; + case NEON::BI__builtin_neon_vrsubhn_v: + return "NEON::BI__builtin_neon_vrsubhn_v"; + case NEON::BI__builtin_neon_vsha1su0q_u32: + return "NEON::BI__builtin_neon_vsha1su0q_u32"; + case NEON::BI__builtin_neon_vsha1su1q_u32: + return "NEON::BI__builtin_neon_vsha1su1q_u32"; + case NEON::BI__builtin_neon_vsha256h2q_u32: + return "NEON::BI__builtin_neon_vsha256h2q_u32"; + case NEON::BI__builtin_neon_vsha256hq_u32: + return "NEON::BI__builtin_neon_vsha256hq_u32"; + case NEON::BI__builtin_neon_vsha256su0q_u32: + return "NEON::BI__builtin_neon_vsha256su0q_u32"; + case NEON::BI__builtin_neon_vsha256su1q_u32: + return "NEON::BI__builtin_neon_vsha256su1q_u32"; + case NEON::BI__builtin_neon_vsha512h2q_u64: + return "NEON::BI__builtin_neon_vsha512h2q_u64"; + case NEON::BI__builtin_neon_vsha512hq_u64: + return "NEON::BI__builtin_neon_vsha512hq_u64"; + case NEON::BI__builtin_neon_vsha512su0q_u64: + return "NEON::BI__builtin_neon_vsha512su0q_u64"; + case NEON::BI__builtin_neon_vsha512su1q_u64: + return "NEON::BI__builtin_neon_vsha512su1q_u64"; + case NEON::BI__builtin_neon_vshl_n_v: + return "NEON::BI__builtin_neon_vshl_n_v"; + case NEON::BI__builtin_neon_vshl_v: + return "NEON::BI__builtin_neon_vshl_v"; + case NEON::BI__builtin_neon_vshll_n_v: + return "NEON::BI__builtin_neon_vshll_n_v"; + case NEON::BI__builtin_neon_vshlq_n_v: + return "NEON::BI__builtin_neon_vshlq_n_v"; + case NEON::BI__builtin_neon_vshlq_v: + return "NEON::BI__builtin_neon_vshlq_v"; + case NEON::BI__builtin_neon_vshr_n_v: + return "NEON::BI__builtin_neon_vshr_n_v"; + case NEON::BI__builtin_neon_vshrn_n_v: + return "NEON::BI__builtin_neon_vshrn_n_v"; + case NEON::BI__builtin_neon_vshrq_n_v: + return "NEON::BI__builtin_neon_vshrq_n_v"; + case NEON::BI__builtin_neon_vsm3partw1q_u32: + return "NEON::BI__builtin_neon_vsm3partw1q_u32"; + case NEON::BI__builtin_neon_vsm3partw2q_u32: + return "NEON::BI__builtin_neon_vsm3partw2q_u32"; + case NEON::BI__builtin_neon_vsm3ss1q_u32: + return "NEON::BI__builtin_neon_vsm3ss1q_u32"; + case NEON::BI__builtin_neon_vsm3tt1aq_u32: + return "NEON::BI__builtin_neon_vsm3tt1aq_u32"; + case NEON::BI__builtin_neon_vsm3tt1bq_u32: + return "NEON::BI__builtin_neon_vsm3tt1bq_u32"; + case NEON::BI__builtin_neon_vsm3tt2aq_u32: + return "NEON::BI__builtin_neon_vsm3tt2aq_u32"; + case NEON::BI__builtin_neon_vsm3tt2bq_u32: + return "NEON::BI__builtin_neon_vsm3tt2bq_u32"; + case NEON::BI__builtin_neon_vsm4ekeyq_u32: + return "NEON::BI__builtin_neon_vsm4ekeyq_u32"; + case NEON::BI__builtin_neon_vsm4eq_u32: + return "NEON::BI__builtin_neon_vsm4eq_u32"; + case NEON::BI__builtin_neon_vst1_x2_v: + return "NEON::BI__builtin_neon_vst1_x2_v"; + case NEON::BI__builtin_neon_vst1_x3_v: + return "NEON::BI__builtin_neon_vst1_x3_v"; + case NEON::BI__builtin_neon_vst1_x4_v: + return "NEON::BI__builtin_neon_vst1_x4_v"; + case NEON::BI__builtin_neon_vst1q_x2_v: + return "NEON::BI__builtin_neon_vst1q_x2_v"; + case NEON::BI__builtin_neon_vst1q_x3_v: + return "NEON::BI__builtin_neon_vst1q_x3_v"; + case NEON::BI__builtin_neon_vst1q_x4_v: + return "NEON::BI__builtin_neon_vst1q_x4_v"; + case NEON::BI__builtin_neon_vsubhn_v: + return "NEON::BI__builtin_neon_vsubhn_v"; + case NEON::BI__builtin_neon_vtst_v: + return "NEON::BI__builtin_neon_vtst_v"; + case NEON::BI__builtin_neon_vtstq_v: + return "NEON::BI__builtin_neon_vtstq_v"; + case NEON::BI__builtin_neon_vusdot_s32: + return "NEON::BI__builtin_neon_vusdot_s32"; + case NEON::BI__builtin_neon_vusdotq_s32: + return "NEON::BI__builtin_neon_vusdotq_s32"; + case NEON::BI__builtin_neon_vusmmlaq_s32: + return "NEON::BI__builtin_neon_vusmmlaq_s32"; + case NEON::BI__builtin_neon_vxarq_u64: + return "NEON::BI__builtin_neon_vxarq_u64"; + } +} + // Some intrinsics are equivalent for codegen. static const std::pair NEONEquivalentIntrinsicMap[] = { { @@ -1346,9 +1899,11 @@ findARMVectorIntrinsicInMap(ArrayRef IntrinsicMap, return nullptr; } -static mlir::Type GetNeonType(CIRGenFunction *CGF, NeonTypeFlags TypeFlags, - bool HasLegalHalfType = true, bool V1Ty = false, - bool AllowBFloatArgsAndRet = true) { +static mlir::cir::VectorType GetNeonType(CIRGenFunction *CGF, + NeonTypeFlags TypeFlags, + bool HasLegalHalfType = true, + bool V1Ty = false, + bool AllowBFloatArgsAndRet = true) { int IsQuad = TypeFlags.isQuad(); switch (TypeFlags.getEltType()) { case NeonTypeFlags::Int8: @@ -1449,7 +2004,7 @@ static mlir::Value buildAArch64TblBuiltinExpr(CIRGenFunction &CGF, // Determine the type of this overloaded NEON intrinsic. NeonTypeFlags Type = Result->getZExtValue(); - auto Ty = GetNeonType(&CGF, Type); + mlir::cir::VectorType Ty = GetNeonType(&CGF, Type); if (!Ty) return nullptr; @@ -1662,8 +2217,8 @@ mlir::Value CIRGenFunction::buildCommonNeonBuiltinExpr( const bool allowBFloatArgsAndRet = getTargetHooks().getABIInfo().allowBFloatArgsAndRet(); - mlir::Type vTy = GetNeonType(this, neonType, hasLegalHalfType, false, - allowBFloatArgsAndRet); + mlir::cir::VectorType vTy = GetNeonType(this, neonType, hasLegalHalfType, + false, allowBFloatArgsAndRet); if (!vTy) return nullptr; @@ -1673,6 +2228,7 @@ mlir::Value CIRGenFunction::buildCommonNeonBuiltinExpr( switch (builtinID) { default: + llvm::errs() << getAArch64SIMDIntrinsicString(builtinID) << " "; llvm_unreachable("NYI"); case NEON::BI__builtin_neon_vqadd_v: mlir::Value res = buildNeonCall(builtinID, *this, {vTy, vTy}, ops, @@ -2393,7 +2949,7 @@ CIRGenFunction::buildAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E, } } - auto Ty = GetNeonType(this, Type); + mlir::cir::VectorType Ty = GetNeonType(this, Type); if (!Ty) return nullptr; @@ -2487,7 +3043,12 @@ CIRGenFunction::buildAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E, case NEON::BI__builtin_neon_vqshrun_n_v: llvm_unreachable("NYI"); case NEON::BI__builtin_neon_vqrshrun_n_v: - llvm_unreachable("NYI"); + // The prototype of builtin_neon_vqrshrun_n can be found at + // https://developer.arm.com/architectures/instruction-sets/intrinsics/ + return buildNeonCall( + BuiltinID, *this, + {builder.getExtendedElementVectorType(Ty, true), SInt32Ty}, Ops, + "llvm.aarch64.neon.sqrshrun", Ty, getLoc(E->getExprLoc())); case NEON::BI__builtin_neon_vqshrn_n_v: llvm_unreachable("NYI"); case NEON::BI__builtin_neon_vrshrn_n_v: diff --git a/clang/test/CIR/CodeGen/aarch64-neon-simd-shift.c b/clang/test/CIR/CodeGen/aarch64-neon-simd-shift.c new file mode 100644 index 000000000000..8619ad0c78d6 --- /dev/null +++ b/clang/test/CIR/CodeGen/aarch64-neon-simd-shift.c @@ -0,0 +1,69 @@ +// RUN: %clang_cc1 -triple aarch64-none-linux-android24 -fclangir \ +// RUN: -ffreestanding -emit-cir -target-feature +neon %s -o %t.cir +// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s +// RUN: %clang_cc1 -triple aarch64-none-linux-android24 -fclangir \ +// RUN: -ffreestanding -emit-llvm -target-feature +neon %s -o %t.ll +// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s + +// REQUIRES: aarch64-registered-target || arm-registered-target +#include + +uint8x8_t test_vqrshrun_n_s16(int16x8_t a) { + return vqrshrun_n_s16(a, 3); +} + +// CIR-LABEL: test_vqrshrun_n_s16 +// CIR: [[INTRN_ARG1:%.*]] = cir.const #cir.int<3> : !s32i +// CIR: [[INTRN_ARG0:%.*]] = cir.cast(bitcast, {{%.*}} : !cir.vector), !cir.vector +// CIR: {{%.*}} = cir.llvm.intrinsic "llvm.aarch64.neon.sqrshrun" [[INTRN_ARG0]], [[INTRN_ARG1]] : +// CIR-SAME: (!cir.vector, !s32i) -> !cir.vector + +// LLVM: {{.*}}test_vqrshrun_n_s16(<8 x i16>{{.*}} [[A:%.*]]) +// LLVM: store <8 x i16> [[A]], ptr [[A_ADDR:%.*]], align 16 +// LLVM: [[A_VAL:%.*]] = load <8 x i16>, ptr [[A_ADDR]], align 16 +// LLVM: store <8 x i16> [[A_VAL]], ptr [[S0:%.*]], align 16 +// LLVM: [[S0_VAL:%.*]] = load <8 x i16>, ptr [[S0]], align 16 +// LLVM: [[S0_VAL_CAST:%.*]] = bitcast <8 x i16> [[S0_VAL]] to <16 x i8> +// LLVM: [[INTRN_ARG:%.*]] = bitcast <16 x i8> [[S0_VAL_CAST]] to <8 x i16> +// LLVM: {{%.*}} = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> [[INTRN_ARG]], i32 3) +// LLVM: ret <8 x i8> {{%.*}} + +uint16x4_t test_vqrshrun_n_s32(int32x4_t a) { + return vqrshrun_n_s32(a, 7); +} + +// CIR-LABEL: test_vqrshrun_n_s32 +// CIR: [[INTRN_ARG1:%.*]] = cir.const #cir.int<7> : !s32i +// CIR: [[INTRN_ARG0:%.*]] = cir.cast(bitcast, {{%.*}} : !cir.vector), !cir.vector +// CIR: {{%.*}} = cir.llvm.intrinsic "llvm.aarch64.neon.sqrshrun" [[INTRN_ARG0]], [[INTRN_ARG1]] : +// CIR-SAME: (!cir.vector, !s32i) -> !cir.vector + +// LLVM: {{.*}}test_vqrshrun_n_s32(<4 x i32>{{.*}} [[A:%.*]]) +// LLVM: store <4 x i32> [[A]], ptr [[A_ADDR:%.*]], align 16 +// LLVM: [[A_VAL:%.*]] = load <4 x i32>, ptr [[A_ADDR]], align 16 +// LLVM: store <4 x i32> [[A_VAL]], ptr [[S0:%.*]], align 16 +// LLVM: [[S0_VAL:%.*]] = load <4 x i32>, ptr [[S0]], align 16 +// LLVM: [[S0_VAL_CAST:%.*]] = bitcast <4 x i32> [[S0_VAL]] to <16 x i8> +// LLVM: [[INTRN_ARG:%.*]] = bitcast <16 x i8> [[S0_VAL_CAST]] to <4 x i32> +// LLVM: {{%.*}} = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> [[INTRN_ARG]], i32 7) +// LLVM: ret <4 x i16> {{%.*}} + +uint32x2_t test_vqrshrun_n_s64(int64x2_t a) { + return vqrshrun_n_s64(a, 15); +} + +// CIR-LABEL: test_vqrshrun_n_s64 +// CIR: [[INTRN_ARG1:%.*]] = cir.const #cir.int<15> : !s32i +// CIR: [[INTRN_ARG0:%.*]] = cir.cast(bitcast, {{%.*}} : !cir.vector), !cir.vector +// CIR: {{%.*}} = cir.llvm.intrinsic "llvm.aarch64.neon.sqrshrun" [[INTRN_ARG0]], [[INTRN_ARG1]] : +// CIR-SAME: (!cir.vector, !s32i) -> !cir.vector + +// LLVM: {{.*}}test_vqrshrun_n_s64(<2 x i64>{{.*}} [[A:%.*]]) +// LLVM: store <2 x i64> [[A]], ptr [[A_ADDR:%.*]], align 16 +// LLVM: [[A_VAL:%.*]] = load <2 x i64>, ptr [[A_ADDR]], align 16 +// LLVM: store <2 x i64> [[A_VAL]], ptr [[S0:%.*]], align 16 +// LLVM: [[S0_VAL:%.*]] = load <2 x i64>, ptr [[S0]], align 16 +// LLVM: [[S0_VAL_CAST:%.*]] = bitcast <2 x i64> [[S0_VAL]] to <16 x i8> +// LLVM: [[INTRN_ARG:%.*]] = bitcast <16 x i8> [[S0_VAL_CAST]] to <2 x i64> +// LLVM: {{%.*}} = call <2 x i32> @llvm.aarch64.neon.sqrshrun.v2i32(<2 x i64> [[INTRN_ARG]], i32 15) +// LLVM: ret <2 x i32> {{%.*}}