@@ -66,67 +66,67 @@ TARGET_BUILTIN(__builtin_wasm_trunc_saturate_s_i64_f64, "LLid", "nc", "nontrappi
66
66
TARGET_BUILTIN(__builtin_wasm_trunc_saturate_u_i64_f64, " LLid" , " nc" , " nontrapping-fptoint" )
67
67
68
68
// SIMD builtins
69
- TARGET_BUILTIN(__builtin_wasm_swizzle_v8x16, " V16cV16cV16c " , " nc" , " simd128" )
69
+ TARGET_BUILTIN(__builtin_wasm_swizzle_v8x16, " V16ScV16ScV16Sc " , " nc" , " simd128" )
70
70
71
- TARGET_BUILTIN(__builtin_wasm_extract_lane_s_i8x16, " iV16cIi " , " nc" , " simd128" )
72
- TARGET_BUILTIN(__builtin_wasm_extract_lane_u_i8x16, " iV16cIi " , " nc" , " simd128" )
71
+ TARGET_BUILTIN(__builtin_wasm_extract_lane_s_i8x16, " iV16ScIi " , " nc" , " simd128" )
72
+ TARGET_BUILTIN(__builtin_wasm_extract_lane_u_i8x16, " iV16UcIUi " , " nc" , " simd128" )
73
73
TARGET_BUILTIN(__builtin_wasm_extract_lane_s_i16x8, " iV8sIi" , " nc" , " simd128" )
74
- TARGET_BUILTIN(__builtin_wasm_extract_lane_u_i16x8, " iV8sIi " , " nc" , " simd128" )
74
+ TARGET_BUILTIN(__builtin_wasm_extract_lane_u_i16x8, " iV8UsIUi " , " nc" , " simd128" )
75
75
TARGET_BUILTIN(__builtin_wasm_extract_lane_i32x4, " iV4iIi" , " nc" , " simd128" )
76
76
TARGET_BUILTIN(__builtin_wasm_extract_lane_i64x2, " LLiV2LLiIi" , " nc" , " simd128" )
77
77
TARGET_BUILTIN(__builtin_wasm_extract_lane_f32x4, " fV4fIi" , " nc" , " simd128" )
78
78
TARGET_BUILTIN(__builtin_wasm_extract_lane_f64x2, " dV2dIi" , " nc" , " simd128" )
79
79
80
- TARGET_BUILTIN(__builtin_wasm_replace_lane_i8x16, " V16cV16cIii " , " nc" , " simd128" )
80
+ TARGET_BUILTIN(__builtin_wasm_replace_lane_i8x16, " V16ScV16ScIii " , " nc" , " simd128" )
81
81
TARGET_BUILTIN(__builtin_wasm_replace_lane_i16x8, " V8sV8sIii" , " nc" , " simd128" )
82
82
TARGET_BUILTIN(__builtin_wasm_replace_lane_i32x4, " V4iV4iIii" , " nc" , " simd128" )
83
83
TARGET_BUILTIN(__builtin_wasm_replace_lane_i64x2, " V2LLiV2LLiIiLLi" , " nc" , " simd128" )
84
84
TARGET_BUILTIN(__builtin_wasm_replace_lane_f32x4, " V4fV4fIif" , " nc" , " simd128" )
85
85
TARGET_BUILTIN(__builtin_wasm_replace_lane_f64x2, " V2dV2dIid" , " nc" , " simd128" )
86
86
87
- TARGET_BUILTIN(__builtin_wasm_add_saturate_s_i8x16, " V16cV16cV16c " , " nc" , " simd128" )
88
- TARGET_BUILTIN(__builtin_wasm_add_saturate_u_i8x16, " V16cV16cV16c " , " nc" , " simd128" )
87
+ TARGET_BUILTIN(__builtin_wasm_add_saturate_s_i8x16, " V16ScV16ScV16Sc " , " nc" , " simd128" )
88
+ TARGET_BUILTIN(__builtin_wasm_add_saturate_u_i8x16, " V16UcV16UcV16Uc " , " nc" , " simd128" )
89
89
TARGET_BUILTIN(__builtin_wasm_add_saturate_s_i16x8, " V8sV8sV8s" , " nc" , " simd128" )
90
- TARGET_BUILTIN(__builtin_wasm_add_saturate_u_i16x8, " V8sV8sV8s " , " nc" , " simd128" )
90
+ TARGET_BUILTIN(__builtin_wasm_add_saturate_u_i16x8, " V8UsV8UsV8Us " , " nc" , " simd128" )
91
91
92
- TARGET_BUILTIN(__builtin_wasm_sub_saturate_s_i8x16, " V16cV16cV16c " , " nc" , " simd128" )
93
- TARGET_BUILTIN(__builtin_wasm_sub_saturate_u_i8x16, " V16cV16cV16c " , " nc" , " simd128" )
92
+ TARGET_BUILTIN(__builtin_wasm_sub_saturate_s_i8x16, " V16ScV16ScV16Sc " , " nc" , " simd128" )
93
+ TARGET_BUILTIN(__builtin_wasm_sub_saturate_u_i8x16, " V16UcV16UcV16Uc " , " nc" , " simd128" )
94
94
TARGET_BUILTIN(__builtin_wasm_sub_saturate_s_i16x8, " V8sV8sV8s" , " nc" , " simd128" )
95
- TARGET_BUILTIN(__builtin_wasm_sub_saturate_u_i16x8, " V8sV8sV8s " , " nc" , " simd128" )
95
+ TARGET_BUILTIN(__builtin_wasm_sub_saturate_u_i16x8, " V8UsV8UsV8Us " , " nc" , " simd128" )
96
96
97
- TARGET_BUILTIN(__builtin_wasm_abs_i8x16, " V16cV16c " , " nc" , " simd128" )
97
+ TARGET_BUILTIN(__builtin_wasm_abs_i8x16, " V16ScV16Sc " , " nc" , " simd128" )
98
98
TARGET_BUILTIN(__builtin_wasm_abs_i16x8, " V8sV8s" , " nc" , " simd128" )
99
99
TARGET_BUILTIN(__builtin_wasm_abs_i32x4, " V4iV4i" , " nc" , " simd128" )
100
100
101
- TARGET_BUILTIN(__builtin_wasm_min_s_i8x16, " V16cV16cV16c " , " nc" , " simd128" )
102
- TARGET_BUILTIN(__builtin_wasm_min_u_i8x16, " V16cV16cV16c " , " nc" , " simd128" )
103
- TARGET_BUILTIN(__builtin_wasm_max_s_i8x16, " V16cV16cV16c " , " nc" , " simd128" )
104
- TARGET_BUILTIN(__builtin_wasm_max_u_i8x16, " V16cV16cV16c " , " nc" , " simd128" )
101
+ TARGET_BUILTIN(__builtin_wasm_min_s_i8x16, " V16ScV16ScV16Sc " , " nc" , " simd128" )
102
+ TARGET_BUILTIN(__builtin_wasm_min_u_i8x16, " V16UcV16UcV16Uc " , " nc" , " simd128" )
103
+ TARGET_BUILTIN(__builtin_wasm_max_s_i8x16, " V16ScV16ScV16Sc " , " nc" , " simd128" )
104
+ TARGET_BUILTIN(__builtin_wasm_max_u_i8x16, " V16UcV16UcV16Uc " , " nc" , " simd128" )
105
105
TARGET_BUILTIN(__builtin_wasm_min_s_i16x8, " V8sV8sV8s" , " nc" , " simd128" )
106
- TARGET_BUILTIN(__builtin_wasm_min_u_i16x8, " V8sV8sV8s " , " nc" , " simd128" )
106
+ TARGET_BUILTIN(__builtin_wasm_min_u_i16x8, " V8UsV8UsV8Us " , " nc" , " simd128" )
107
107
TARGET_BUILTIN(__builtin_wasm_max_s_i16x8, " V8sV8sV8s" , " nc" , " simd128" )
108
- TARGET_BUILTIN(__builtin_wasm_max_u_i16x8, " V8sV8sV8s " , " nc" , " simd128" )
108
+ TARGET_BUILTIN(__builtin_wasm_max_u_i16x8, " V8UsV8UsV8Us " , " nc" , " simd128" )
109
109
TARGET_BUILTIN(__builtin_wasm_min_s_i32x4, " V4iV4iV4i" , " nc" , " simd128" )
110
- TARGET_BUILTIN(__builtin_wasm_min_u_i32x4, " V4iV4iV4i " , " nc" , " simd128" )
110
+ TARGET_BUILTIN(__builtin_wasm_min_u_i32x4, " V4UiV4UiV4Ui " , " nc" , " simd128" )
111
111
TARGET_BUILTIN(__builtin_wasm_max_s_i32x4, " V4iV4iV4i" , " nc" , " simd128" )
112
- TARGET_BUILTIN(__builtin_wasm_max_u_i32x4, " V4iV4iV4i " , " nc" , " simd128" )
112
+ TARGET_BUILTIN(__builtin_wasm_max_u_i32x4, " V4UiV4UiV4Ui " , " nc" , " simd128" )
113
113
114
- TARGET_BUILTIN(__builtin_wasm_avgr_u_i8x16, " V16cV16cV16c " , " nc" , " simd128" )
115
- TARGET_BUILTIN(__builtin_wasm_avgr_u_i16x8, " V8sV8sV8s " , " nc" , " simd128" )
114
+ TARGET_BUILTIN(__builtin_wasm_avgr_u_i8x16, " V16UcV16UcV16Uc " , " nc" , " simd128" )
115
+ TARGET_BUILTIN(__builtin_wasm_avgr_u_i16x8, " V8UsV8UsV8Us " , " nc" , " simd128" )
116
116
117
117
TARGET_BUILTIN(__builtin_wasm_bitselect, " V4iV4iV4iV4i" , " nc" , " simd128" )
118
- TARGET_BUILTIN(__builtin_wasm_shuffle_v8x16, " V16cV16cV16cIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIi " , " nc" , " simd128" )
118
+ TARGET_BUILTIN(__builtin_wasm_shuffle_v8x16, " V16ScV16ScV16ScIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIi " , " nc" , " simd128" )
119
119
120
- TARGET_BUILTIN(__builtin_wasm_any_true_i8x16, " iV16c " , " nc" , " simd128" )
120
+ TARGET_BUILTIN(__builtin_wasm_any_true_i8x16, " iV16Sc " , " nc" , " simd128" )
121
121
TARGET_BUILTIN(__builtin_wasm_any_true_i16x8, " iV8s" , " nc" , " simd128" )
122
122
TARGET_BUILTIN(__builtin_wasm_any_true_i32x4, " iV4i" , " nc" , " simd128" )
123
123
TARGET_BUILTIN(__builtin_wasm_any_true_i64x2, " iV2LLi" , " nc" , " unimplemented-simd128" )
124
- TARGET_BUILTIN(__builtin_wasm_all_true_i8x16, " iV16c " , " nc" , " simd128" )
124
+ TARGET_BUILTIN(__builtin_wasm_all_true_i8x16, " iV16Sc " , " nc" , " simd128" )
125
125
TARGET_BUILTIN(__builtin_wasm_all_true_i16x8, " iV8s" , " nc" , " simd128" )
126
126
TARGET_BUILTIN(__builtin_wasm_all_true_i32x4, " iV4i" , " nc" , " simd128" )
127
127
TARGET_BUILTIN(__builtin_wasm_all_true_i64x2, " iV2LLi" , " nc" , " unimplemented-simd128" )
128
128
129
- TARGET_BUILTIN(__builtin_wasm_bitmask_i8x16, " iV16c " , " nc" , " simd128" )
129
+ TARGET_BUILTIN(__builtin_wasm_bitmask_i8x16, " iV16Sc " , " nc" , " simd128" )
130
130
TARGET_BUILTIN(__builtin_wasm_bitmask_i16x8, " iV8s" , " nc" , " simd128" )
131
131
TARGET_BUILTIN(__builtin_wasm_bitmask_i32x4, " iV4i" , " nc" , " simd128" )
132
132
@@ -164,10 +164,10 @@ TARGET_BUILTIN(__builtin_wasm_qfms_f64x2, "V2dV2dV2dV2d", "nc", "unimplemented-s
164
164
TARGET_BUILTIN(__builtin_wasm_trunc_saturate_s_i32x4_f32x4, " V4iV4f" , " nc" , " simd128" )
165
165
TARGET_BUILTIN(__builtin_wasm_trunc_saturate_u_i32x4_f32x4, " V4iV4f" , " nc" , " simd128" )
166
166
167
- TARGET_BUILTIN(__builtin_wasm_narrow_s_i8x16_i16x8, " V16cV8sV8s " , " nc" , " simd128" )
168
- TARGET_BUILTIN(__builtin_wasm_narrow_u_i8x16_i16x8, " V16cV8sV8s " , " nc" , " simd128" )
167
+ TARGET_BUILTIN(__builtin_wasm_narrow_s_i8x16_i16x8, " V16ScV8sV8s " , " nc" , " simd128" )
168
+ TARGET_BUILTIN(__builtin_wasm_narrow_u_i8x16_i16x8, " V16UcV8UsV8Us " , " nc" , " simd128" )
169
169
TARGET_BUILTIN(__builtin_wasm_narrow_s_i16x8_i32x4, " V8sV4iV4i" , " nc" , " simd128" )
170
- TARGET_BUILTIN(__builtin_wasm_narrow_u_i16x8_i32x4, " V8sV4iV4i " , " nc" , " simd128" )
170
+ TARGET_BUILTIN(__builtin_wasm_narrow_u_i16x8_i32x4, " V8UsV4UiV4Ui " , " nc" , " simd128" )
171
171
172
172
TARGET_BUILTIN(__builtin_wasm_load32_zero, " V4ii*" , " nU" , " simd128" )
173
173
TARGET_BUILTIN(__builtin_wasm_load64_zero, " V2LLiLLi*" , " nU" , " simd128" )
0 commit comments