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Remove extraneous parens on asUInt.
1 parent 83640e3 commit 2ef51b8

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5 files changed

+12
-12
lines changed

5 files changed

+12
-12
lines changed

src/main/scala/chisel3/iotesters/OrderedDecoupledHWIOTester.scala

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -320,7 +320,7 @@ abstract class OrderedDecoupledHWIOTester extends HWIOTester {
320320
)
321321
when(port.asInstanceOf[UInt] != port_vector_events(port)(counter_for_this_decoupled.value)) {
322322
printf(s"Error: event %d ${name(port)} was %d should be %d\n",
323-
event_counter.value, port.asUInt(), port_vector_events(port)(counter_for_this_decoupled.value))
323+
event_counter.value, port.asUInt, port_vector_events(port)(counter_for_this_decoupled.value))
324324
assert(false.B)
325325
stop()
326326
}
@@ -359,7 +359,7 @@ abstract class OrderedDecoupledHWIOTester extends HWIOTester {
359359
)
360360
when(port.asInstanceOf[UInt] =/= port_vector_events(port)(counter_for_this_valid.value)) {
361361
printf(s"Error: event %d ${name(port)} was %x should be %x",
362-
event_counter.value, port.asUInt(), port_vector_events(port)(counter_for_this_valid.value))
362+
event_counter.value, port.asUInt, port_vector_events(port)(counter_for_this_valid.value))
363363
assert(false.B)
364364
}
365365
}

src/main/scala/chisel3/iotesters/SteppedHWIOTester.scala

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -142,16 +142,16 @@ abstract class SteppedHWIOTester extends HWIOTester {
142142
)
143143

144144
when(ok_to_test_output_values(counter.value)) {
145-
when(output_port.asUInt() === output_values(counter.value).asUInt()) {
145+
when(output_port.asUInt === output_values(counter.value).asUInt) {
146146
logPrintfDebug(" passed step %d -- " + name(output_port) + ": %d\n",
147147
counter.value,
148-
output_port.asUInt()
148+
output_port.asUInt
149149
)
150150
}.otherwise {
151151
printf(" failed on step %d -- port " + name(output_port) + ": %d expected %d\n",
152152
counter.value,
153-
output_port.asUInt(),
154-
output_values(counter.value).asUInt()
153+
output_port.asUInt,
154+
output_values(counter.value).asUInt
155155
)
156156
// TODO: Use the following line instead of the unadorned assert when firrtl parsing error issue #111 is fixed
157157
// assert(false.B, "Failed test")

src/test/scala/examples/Adder.scala

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -45,13 +45,13 @@ class AdderExerciser extends Exerciser {
4545
val count = 20 // this forces ranges to all be the same size
4646
Range(start, start + count)
4747
}
48-
val in0_vec = Vec(range(x_range_start).map((_).asUInt()))
49-
val in1_vec = Vec(range(y_range_start).map((_).asUInt()))
48+
val in0_vec = Vec(range(x_range_start).map((_).asUInt))
49+
val in1_vec = Vec(range(y_range_start).map((_).asUInt))
5050

5151
val expected_out_vec = Vec(in0_vec.zip(in1_vec).map { case (i,j) => i + j })
5252
val test_number = Reg(init=0.U(internal_counter_width.W))
5353

54-
buildState("check adder")(StopCondition(test_number > (range(0).size).asUInt())) { () =>
54+
buildState("check adder")(StopCondition(test_number > (range(0).size).asUInt)) { () =>
5555
printf(
5656
"%d ticker %d test# %d : %d + %d => %d expected %d\n",
5757
state_number, ticker, test_number,

src/test/scala/examples/DecoupledAdder.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ class SlowDecoupledAdder extends Module {
4444
wait_counter := 0.U
4545
}
4646
when(busy) {
47-
when(wait_counter > delay_value.asUInt()) {
47+
when(wait_counter > delay_value.asUInt) {
4848
io.out.bits.c := a_reg + b_reg
4949
}.otherwise {
5050
wait_counter := wait_counter + 1.U

src/test/scala/examples/RealGCD.scala

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -115,7 +115,7 @@ class DecoupledRealGCDTestHandCodedExample extends OrderedDecoupledHWIOTester {
115115
c.io.in.bits.b := b_values(pc)
116116
c.io.in.valid := true.B
117117
pc := pc + 1.U
118-
when(pc >= (a_values.length).asUInt()) {
118+
when(pc >= (a_values.length).asUInt) {
119119
in_done := true.B
120120
}
121121
}
@@ -128,7 +128,7 @@ class DecoupledRealGCDTestHandCodedExample extends OrderedDecoupledHWIOTester {
128128
assert(c.io.out.bits === c_values(oc))
129129
// c.io.out.ready := true.B
130130
oc := oc + 1.U
131-
when(oc >= (c_values.length).asUInt()) {
131+
when(oc >= (c_values.length).asUInt) {
132132
out_done := true.B
133133
}
134134
}

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