Fix verilator custom transforms not being run (freechipsproject#127)

* Custom transforms were not being run when using verilator backend

* Fix custom transforms not being passed to compileAndEmit correctly
Brings VCSBackend more in line with VerilatorBackend
Some nit cleanup on VCSBackend
Fixed broken VecFillSpec

Author: chick

src/main/scala/chisel3/iotesters/VCSBackend.scala

@@ -1,13 +1,12 @@
 // See LICENSE for license details.
 package chisel3.iotesters
 
-import scala.collection.mutable.HashMap
-import scala.util.Random
-import java.io.{File, FileWriter, IOException, PrintStream, Writer}
+import java.io.{File, FileWriter, IOException, Writer}
 import java.nio.file.{FileAlreadyExistsException, Files, Paths}
 import java.nio.file.StandardCopyOption.REPLACE_EXISTING
 
 import chisel3.{ChiselExecutionFailure, ChiselExecutionSuccess}
+import firrtl.{ChirrtlForm, CircuitState, Transform}
 import firrtl.annotations.CircuitName
 import firrtl.transforms.{BlackBoxSourceHelper, BlackBoxTargetDir}
 
@@ -27,11 +26,10 @@ object copyVpiFiles {
       Files.createFile(vpiCppFilePath)
       Files.createFile(vpiTabFilePath)
     } catch {
-      case x: FileAlreadyExistsException =>
+      case _: FileAlreadyExistsException =>
         System.out.format("")
-      case x: IOException => {
+      case x: IOException =>
         System.err.format("createFile error: %s%n", x)
-      }
     }
 
     Files.copy(getClass.getResourceAsStream("/sim_api.h"), simApiHFilePath, REPLACE_EXISTING)
@@ -70,10 +68,10 @@ object genVCSVerilogHarness {
     writer write "  reg [1023:0] vpdfile = 0;\n"
 
     writer write "\n  /*** DUT instantiation ***/\n"
-    writer write s"  ${dutName} ${dutName}(\n"
+    writer write s"  $dutName $dutName(\n"
     writer write "    .clock(clock),\n"
     writer write "    .reset(reset),\n"
-    writer write ((inputs ++ outputs).unzip._2 map (name => s"    .${name}(${name}_delay)") mkString ",\n")
+    writer write ((inputs ++ outputs).unzip._2 map (name => s"    .$name(${name}_delay)") mkString ",\n")
     writer write "  );\n\n"
 
     writer write "  initial begin\n"
@@ -112,7 +110,7 @@ object genVCSVerilogHarness {
     writer write "    $vcdplusflush;\n"
     writer write "  end\n\n"
     writer write "endmodule\n"
-    writer.close
+    writer.close()
   }
 }
 
@@ -130,24 +128,31 @@ private[iotesters] object setupVCSBackend {
 
         val chirrtl = firrtl.Parser.parse(emitted)
         val dut = getTopModule(circuit).asInstanceOf[T]
-        val nodes = getChiselNodes(circuit)
-        val annotations = firrtl.AnnotationMap(optionsManager.firrtlOptions.annotations ++ List(
+
+        /*
+        The following block adds an annotation that tells the black box helper where the
+        current build directory is, so that it can copy verilog resource files into the right place
+         */
+        val annotationMap = firrtl.AnnotationMap(optionsManager.firrtlOptions.annotations ++ List(
           firrtl.annotations.Annotation(
             CircuitName(circuit.name),
             classOf[BlackBoxSourceHelper],
             BlackBoxTargetDir(optionsManager.targetDirName).serialize
           )
         ))
 
+        val transforms = optionsManager.firrtlOptions.customTransforms
+
         // Generate Verilog
         val verilogFile = new File(dir, s"${circuit.name}.v")
         val verilogWriter = new FileWriter(verilogFile)
-        val verilogCompiler = new firrtl.VerilogCompiler
-        verilogCompiler.compile(
-          firrtl.CircuitState(chirrtl, firrtl.ChirrtlForm, Some(annotations)),
-          verilogWriter,
-          optionsManager.firrtlOptions.customTransforms
+
+        val compileResult = (new firrtl.VerilogCompiler).compileAndEmit(
+          CircuitState(chirrtl, ChirrtlForm, Some(annotationMap)),
+          customTransforms = transforms
         )
+        val compiledStuff = compileResult.getEmittedCircuit
+        verilogWriter.write(compiledStuff.value)
         verilogWriter.close()
 
         // Generate Harness
@@ -160,8 +165,9 @@ private[iotesters] object setupVCSBackend {
 
         val command = if(optionsManager.testerOptions.testCmd.nonEmpty) {
           optionsManager.testerOptions.testCmd
-        } else {
-          Seq(new File(dir, circuit.name).toString)
+        }
+        else {
+          Seq(new File(dir, s"V${circuit.name}").toString)
         }
 
         (dut, new VCSBackend(dut, command))

src/main/scala/chisel3/iotesters/VerilatorBackend.scala

@@ -204,6 +204,10 @@ private[iotesters] object setupVerilatorBackend {
         val chirrtl = firrtl.Parser.parse(emitted)
         val dut = getTopModule(circuit).asInstanceOf[T]
 
+        /*
+        The following block adds an annotation that tells the black box helper where the
+        current build directory is, so that it can copy verilog resource files into the right place
+         */
         val annotationMap = firrtl.AnnotationMap(optionsManager.firrtlOptions.annotations ++ List(
           firrtl.annotations.Annotation(
             CircuitName(circuit.name),
@@ -212,19 +216,23 @@ private[iotesters] object setupVerilatorBackend {
           )
         ))
 
+        val transforms = optionsManager.firrtlOptions.customTransforms
+
         copyVerilatorHeaderFiles(optionsManager.targetDirName)
 
         // Generate Verilog
         val verilogFile = new File(dir, s"${circuit.name}.v")
         val verilogWriter = new FileWriter(verilogFile)
 
         val compileResult = (new firrtl.VerilogCompiler).compileAndEmit(
-          CircuitState(chirrtl, ChirrtlForm, Some(annotationMap))
+          CircuitState(chirrtl, ChirrtlForm, Some(annotationMap)),
+          customTransforms = transforms
         )
         val compiledStuff = compileResult.getEmittedCircuit
         verilogWriter.write(compiledStuff.value)
         verilogWriter.close()
 
+        // Generate Harness
         val cppHarnessFileName = s"${circuit.name}-harness.cpp"
         val cppHarnessFile = new File(dir, cppHarnessFileName)
         val cppHarnessWriter = new FileWriter(cppHarnessFile)

src/test/scala/chisel3/iotesters/VecFillSpec.scala

@@ -24,11 +24,7 @@ class VFTester(c: VF) extends PeekPokeTester(c) {
     expect(c.io.value, i)
     step(1)
   }
-  for(i <- 11 until 111) {
-    poke(c.io.addr, i)
-    expect(c.io.value, i % 11)
-    step(1)
-  }
+  // behavior of indexing past end of vec is undefined
 }
 
 class VecFillSpec extends FreeSpec with Matchers {