Ensure all output signals are driven - prep for InvalidateAPI. (freechipsproject#175)

* support for InvalidateAPI pending FIRRTL .when ... .otherwise fix

* Ensure all output signals are driven - prep for InvalidateAPI.

* Revert hacks to deal with InvalidateAPI (except for Router.scala).

* Eliminate when(reset.toBool) so all outputs are initialized.

Author: ucbjrl

src/test/scala/examples/BundleInitSpec.scala

@@ -35,6 +35,8 @@ object MyBundle {
     */
   def setYTo5(): MyBundle = {
     val wire = Wire(new MyBundle)
+    // Initialize all elements. We don't want firrtl complaining about "not fully initialized" connections.
+    wire.x := 0.U
     wire.y := 5.U
     wire
   }

src/test/scala/examples/DecoupledAdder.scala

@@ -26,9 +26,11 @@ class SlowDecoupledAdder extends Module {
     val in  = Flipped(Decoupled(new SlowDecoupledAdderIn))
     val out = Decoupled(new SlowDecoupledAdderOut)
   })
+  // Initialize all elements. We don't want firrtl complaining about "not fully initialized" connections.
   val busy    = RegInit(false.B)
   val a_reg   = RegInit(0.U(16.W))
   val b_reg   = RegInit(0.U(16.W))
+  val o_reg   = RegInit(0.U(16.W))
   val wait_counter = RegInit(0.U(16.W))
 
   io.in.ready := !busy
@@ -45,11 +47,12 @@ class SlowDecoupledAdder extends Module {
   }
   when(busy) {
     when(wait_counter > delay_value.asUInt) {
-      io.out.bits.c := a_reg + b_reg
+      o_reg := a_reg + b_reg
     }.otherwise {
       wait_counter := wait_counter + 1.U
     }
   }
+  io.out.bits.c := o_reg
 
   io.out.valid := (io.out.bits.c === a_reg + b_reg ) && busy
 

src/test/scala/examples/InterpreterVerilatorConsistencySpec.scala

@@ -2,12 +2,9 @@
 
 package examples
 
-import chisel3._
-import chisel3.util._
 import chisel3._
 import chisel3.util._
 import chisel3.iotesters._
-import org.scalatest.{Matchers, FlatSpec}
 
 class ExampleModule extends Module {
   val io = IO(new Bundle {
@@ -39,6 +36,8 @@ class ExampleModule extends Module {
       io.out.bits := 0.U
       wait_counter := wait_counter + 1.U
     }
+  }.otherwise {
+    io.out.bits := 0.U
   }
 
   io.out.valid := (io.out.bits === in_reg) && (wait_counter === delay_value) && busy

src/test/scala/examples/Router.scala

@@ -3,7 +3,7 @@
 package examples
 
 import chisel3._
-import chisel3.util.{EnqIO, DeqIO, log2Ceil}
+import chisel3.util.{DeqIO, EnqIO, log2Ceil}
 import chisel3.iotesters.{ChiselFlatSpec, OrderedDecoupledHWIOTester}
 
 object Router {
@@ -53,12 +53,14 @@ class Router extends Module {
   val io    = IO(new RouterIO(n))
   val tbl   = Mem(depth, UInt(BigInt(n).bitLength.W))
 
-  when(reset.toBool) {
-    io.read_routing_table_request.nodeq()
-    io.load_routing_table_request.nodeq()
-    io.read_routing_table_response.noenq()
-    io.in.nodeq()
-    io.outs.foreach { out => out.noenq() }
+  io.read_routing_table_request.nodeq()
+  io.load_routing_table_request.nodeq()
+  io.read_routing_table_response.noenq()
+  io.read_routing_table_response.bits := 0.U
+  io.in.nodeq()
+  io.outs.foreach { out =>
+    out.bits := 0.U.asTypeOf(out.bits)
+    out.noenq()
   }
 
   when(io.read_routing_table_request.valid && io.read_routing_table_response.ready) {