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Add error on misused define. (veripool#1659)
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8 files changed

+107
-77
lines changed

8 files changed

+107
-77
lines changed

‎Changes‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,10 +6,12 @@ indicates the contributor was also the author of the fix; Thanks!
66

77
* Verilog-Perl 3.471 devel
88

9-
**** Add error on misused define, #1659. [Topa Tota]
9+
**** Add error on misused define (#1659). [Topa Tota]
1010

1111
**** Fix packages as enum base types, Verilator bug 2202. [Driss Hafdi]
1212

13+
**** Fix preprocessor stringify of undefined macro (#1668). [Martin Whitaker]
14+
1315

1416
* Verilog-Perl 3.470 2020-01-06
1517

‎Preproc/VPreProc.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1190,8 +1190,8 @@ int VPreProcImp::getStateToken(string& buf) {
11901190
if (m_off) {
11911191
goto next_tok;
11921192
} else {
1193-
buf = string(yyourtext(), yyourleng());
1194-
return (VP_TEXT);
1193+
unputDefrefString(string("`\032") + name);
1194+
goto next_tok;
11951195
}
11961196
}
11971197
else if (params=="0") { // Found, as simple substitution

‎t/30_preproc.out‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -884,6 +884,11 @@ verilog/inc1.v: endgenerate
884884
verilog/inc1.v: endmodule
885885
verilog/inc1.v:
886886
verilog/inc1.v: //======================================================================
887+
verilog/inc1.v: // Verilog-Perl bug1668
888+
verilog/inc1.v:
889+
verilog/inc1.v: "`NOT_DEFINED_STR"
890+
verilog/inc1.v:
891+
verilog/inc1.v: //======================================================================
887892
verilog/inc1.v: // IEEE mandated predefines
888893
verilog/inc1.v: // undefineall should have no effect on these
889894
verilog/inc1.v: predef 0 0

‎t/30_preproc_nows.out‎

Lines changed: 17 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -343,19 +343,20 @@ verilog/inc1.v:668: `line 668 "verilog/inc1.v" 0
343343
verilog/inc1.v:668: initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0);
344344
verilog/inc1.v:669: endgenerate
345345
verilog/inc1.v:670: endmodule
346-
verilog/inc1.v:675: predef 0 0
347-
verilog/inc1.v:676: predef 1 1
348-
verilog/inc1.v:677: predef 2 2
349-
verilog/inc1.v:678: predef 3 3
350-
verilog/inc1.v:679: predef 10 10
351-
verilog/inc1.v:680: predef 11 11
352-
verilog/inc1.v:681: predef 20 20
353-
verilog/inc1.v:682: predef 21 21
354-
verilog/inc1.v:683: predef 22 22
355-
verilog/inc1.v:684: predef 23 23
356-
verilog/inc1.v:685: predef -2 -2
357-
verilog/inc1.v:686: predef -1 -1
358-
verilog/inc1.v:687: predef 0 0
359-
verilog/inc1.v:688: predef 1 1
360-
verilog/inc1.v:689: predef 2 2
361-
verilog/inc1.v:691: `line 691 "verilog/inc1.v" 2
346+
verilog/inc1.v:675: "`NOT_DEFINED_STR"
347+
verilog/inc1.v:680: predef 0 0
348+
verilog/inc1.v:681: predef 1 1
349+
verilog/inc1.v:682: predef 2 2
350+
verilog/inc1.v:683: predef 3 3
351+
verilog/inc1.v:684: predef 10 10
352+
verilog/inc1.v:685: predef 11 11
353+
verilog/inc1.v:686: predef 20 20
354+
verilog/inc1.v:687: predef 21 21
355+
verilog/inc1.v:688: predef 22 22
356+
verilog/inc1.v:689: predef 23 23
357+
verilog/inc1.v:690: predef -2 -2
358+
verilog/inc1.v:691: predef -1 -1
359+
verilog/inc1.v:692: predef 0 0
360+
verilog/inc1.v:693: predef 1 1
361+
verilog/inc1.v:694: predef 2 2
362+
verilog/inc1.v:696: `line 696 "verilog/inc1.v" 2

‎t/30_preproc_on.out‎

Lines changed: 24 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -980,22 +980,27 @@ verilog/inc1.v:669: endgenerate
980980
verilog/inc1.v:670: endmodule
981981
verilog/inc1.v:671:
982982
verilog/inc1.v:672: //======================================================================
983-
verilog/inc1.v:673: // IEEE mandated predefines
984-
verilog/inc1.v:674: // undefineall should have no effect on these
985-
verilog/inc1.v:675: predef 0 0
986-
verilog/inc1.v:676: predef 1 1
987-
verilog/inc1.v:677: predef 2 2
988-
verilog/inc1.v:678: predef 3 3
989-
verilog/inc1.v:679: predef 10 10
990-
verilog/inc1.v:680: predef 11 11
991-
verilog/inc1.v:681: predef 20 20
992-
verilog/inc1.v:682: predef 21 21
993-
verilog/inc1.v:683: predef 22 22
994-
verilog/inc1.v:684: predef 23 23
995-
verilog/inc1.v:685: predef -2 -2
996-
verilog/inc1.v:686: predef -1 -1
997-
verilog/inc1.v:687: predef 0 0
998-
verilog/inc1.v:688: predef 1 1
999-
verilog/inc1.v:689: predef 2 2
1000-
verilog/inc1.v:690:
1001-
verilog/inc1.v:691: `line 691 "verilog/inc1.v" 2
983+
verilog/inc1.v:673: // Verilog-Perl bug1668
984+
verilog/inc1.v:674:
985+
verilog/inc1.v:675: "`NOT_DEFINED_STR"
986+
verilog/inc1.v:676:
987+
verilog/inc1.v:677: //======================================================================
988+
verilog/inc1.v:678: // IEEE mandated predefines
989+
verilog/inc1.v:679: // undefineall should have no effect on these
990+
verilog/inc1.v:680: predef 0 0
991+
verilog/inc1.v:681: predef 1 1
992+
verilog/inc1.v:682: predef 2 2
993+
verilog/inc1.v:683: predef 3 3
994+
verilog/inc1.v:684: predef 10 10
995+
verilog/inc1.v:685: predef 11 11
996+
verilog/inc1.v:686: predef 20 20
997+
verilog/inc1.v:687: predef 21 21
998+
verilog/inc1.v:688: predef 22 22
999+
verilog/inc1.v:689: predef 23 23
1000+
verilog/inc1.v:690: predef -2 -2
1001+
verilog/inc1.v:691: predef -1 -1
1002+
verilog/inc1.v:692: predef 0 0
1003+
verilog/inc1.v:693: predef 1 1
1004+
verilog/inc1.v:694: predef 2 2
1005+
verilog/inc1.v:695:
1006+
verilog/inc1.v:696: `line 696 "verilog/inc1.v" 2

‎t/30_preproc_sub.out‎

Lines changed: 27 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1171,24 +1171,31 @@ verilog/inc1.v:670: endmodule
11711171
verilog/inc1.v:671:
11721172
verilog/inc1.v:672: COMMENT: //======================================================================
11731173
verilog/inc1.v:672: /*CMT*/
1174-
verilog/inc1.v:673: COMMENT: // IEEE mandated predefines
1174+
verilog/inc1.v:673: COMMENT: // Verilog-Perl bug1668
11751175
verilog/inc1.v:673: /*CMT*/
1176-
verilog/inc1.v:674: COMMENT: // undefineall should have no effect on these
1177-
verilog/inc1.v:674: /*CMT*/
1178-
verilog/inc1.v:675: predef DS_0 0
1179-
verilog/inc1.v:676: predef DS_1 1
1180-
verilog/inc1.v:677: predef DS_2 2
1181-
verilog/inc1.v:678: predef DS_3 3
1182-
verilog/inc1.v:679: predef DS_10 10
1183-
verilog/inc1.v:680: predef DS_11 11
1184-
verilog/inc1.v:681: predef DS_20 20
1185-
verilog/inc1.v:682: predef DS_21 21
1186-
verilog/inc1.v:683: predef DS_22 22
1187-
verilog/inc1.v:684: predef DS_23 23
1188-
verilog/inc1.v:685: predef DS_-2 -2
1189-
verilog/inc1.v:686: predef DS_-1 -1
1190-
verilog/inc1.v:687: predef DS_0 0
1191-
verilog/inc1.v:688: predef DS_1 1
1192-
verilog/inc1.v:689: predef DS_2 2
1193-
verilog/inc1.v:690:
1194-
verilog/inc1.v:691: `line 691 "verilog/inc1.v" 2
1176+
verilog/inc1.v:674:
1177+
verilog/inc1.v:675: DS_"`NOT_DEFINED_STR"
1178+
verilog/inc1.v:676:
1179+
verilog/inc1.v:677: COMMENT: //======================================================================
1180+
verilog/inc1.v:677: /*CMT*/
1181+
verilog/inc1.v:678: COMMENT: // IEEE mandated predefines
1182+
verilog/inc1.v:678: /*CMT*/
1183+
verilog/inc1.v:679: COMMENT: // undefineall should have no effect on these
1184+
verilog/inc1.v:679: /*CMT*/
1185+
verilog/inc1.v:680: predef DS_0 0
1186+
verilog/inc1.v:681: predef DS_1 1
1187+
verilog/inc1.v:682: predef DS_2 2
1188+
verilog/inc1.v:683: predef DS_3 3
1189+
verilog/inc1.v:684: predef DS_10 10
1190+
verilog/inc1.v:685: predef DS_11 11
1191+
verilog/inc1.v:686: predef DS_20 20
1192+
verilog/inc1.v:687: predef DS_21 21
1193+
verilog/inc1.v:688: predef DS_22 22
1194+
verilog/inc1.v:689: predef DS_23 23
1195+
verilog/inc1.v:690: predef DS_-2 -2
1196+
verilog/inc1.v:691: predef DS_-1 -1
1197+
verilog/inc1.v:692: predef DS_0 0
1198+
verilog/inc1.v:693: predef DS_1 1
1199+
verilog/inc1.v:694: predef DS_2 2
1200+
verilog/inc1.v:695:
1201+
verilog/inc1.v:696: `line 696 "verilog/inc1.v" 2

‎t/30_preproc_syn.out‎

Lines changed: 24 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -964,22 +964,27 @@ verilog/inc1.v:669: endgenerate
964964
verilog/inc1.v:670: endmodule
965965
verilog/inc1.v:671:
966966
verilog/inc1.v:672: //======================================================================
967-
verilog/inc1.v:673: // IEEE mandated predefines
968-
verilog/inc1.v:674: // undefineall should have no effect on these
969-
verilog/inc1.v:675: predef 0 0
970-
verilog/inc1.v:676: predef 1 1
971-
verilog/inc1.v:677: predef 2 2
972-
verilog/inc1.v:678: predef 3 3
973-
verilog/inc1.v:679: predef 10 10
974-
verilog/inc1.v:680: predef 11 11
975-
verilog/inc1.v:681: predef 20 20
976-
verilog/inc1.v:682: predef 21 21
977-
verilog/inc1.v:683: predef 22 22
978-
verilog/inc1.v:684: predef 23 23
979-
verilog/inc1.v:685: predef -2 -2
980-
verilog/inc1.v:686: predef -1 -1
981-
verilog/inc1.v:687: predef 0 0
982-
verilog/inc1.v:688: predef 1 1
983-
verilog/inc1.v:689: predef 2 2
984-
verilog/inc1.v:690:
985-
verilog/inc1.v:691: `line 691 "verilog/inc1.v" 2
967+
verilog/inc1.v:673: // Verilog-Perl bug1668
968+
verilog/inc1.v:674:
969+
verilog/inc1.v:675: "`NOT_DEFINED_STR"
970+
verilog/inc1.v:676:
971+
verilog/inc1.v:677: //======================================================================
972+
verilog/inc1.v:678: // IEEE mandated predefines
973+
verilog/inc1.v:679: // undefineall should have no effect on these
974+
verilog/inc1.v:680: predef 0 0
975+
verilog/inc1.v:681: predef 1 1
976+
verilog/inc1.v:682: predef 2 2
977+
verilog/inc1.v:683: predef 3 3
978+
verilog/inc1.v:684: predef 10 10
979+
verilog/inc1.v:685: predef 11 11
980+
verilog/inc1.v:686: predef 20 20
981+
verilog/inc1.v:687: predef 21 21
982+
verilog/inc1.v:688: predef 22 22
983+
verilog/inc1.v:689: predef 23 23
984+
verilog/inc1.v:690: predef -2 -2
985+
verilog/inc1.v:691: predef -1 -1
986+
verilog/inc1.v:692: predef 0 0
987+
verilog/inc1.v:693: predef 1 1
988+
verilog/inc1.v:694: predef 2 2
989+
verilog/inc1.v:695:
990+
verilog/inc1.v:696: `line 696 "verilog/inc1.v" 2

‎verilog/inc1.v‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -669,6 +669,11 @@ module pcc2_cfg;
669669
endgenerate
670670
endmodule
671671

672+
//======================================================================
673+
// Verilog-Perl bug1668
674+
`define stringify(text) `"text`"
675+
`stringify(`NOT_DEFINED_STR)
676+
672677
//======================================================================
673678
// IEEE mandated predefines
674679
`undefineall // undefineall should have no effect on these

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