deps: V8: cherry-pick 516b5d3f9cfe

Original commit message:

    Merged: [wasm-simd][x64] Check for register when emitting shuffles

    Some shuffles take have either register or memory operand for second
    input, but the codegen incorrectly assumes that it is always a register.

    Bug: v8:10824
    (cherry picked from commit ddf30bea13902829eeb71aa0ec747155e27e5a68)

    Change-Id: I897c4290a8b91ff2ab839e98b16a9696c0bae511
    No-Try: true
    No-Presubmit: true
    No-Tree-Checks: true
    Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2391280
    Reviewed-by: Bill Budge <[email protected]>
    Commit-Queue: Zhi An Ng <[email protected]>
    Cr-Commit-Position: refs/branch-heads/8.6@{#6}
    Cr-Branched-From: a64aed2333abf49e494d2a5ce24bbd14fff19f60-refs/heads/8.6.395@{#1}
    Cr-Branched-From: a626bc036236c9bf92ac7b87dc40c9e538b087e3-refs/heads/master@{#69472}

Refs: v8/v8@516b5d3

PR-URL: #38275
Reviewed-By: Matteo Collina <[email protected]>
Reviewed-By: Jiawen Geng <[email protected]>
Reviewed-By: Shelley Vohr <[email protected]>

Author: targos

common.gypi

@@ -36,7 +36,7 @@
 
     # Reset this number to 0 on major V8 upgrades.
     # Increment by one for each non-official patch applied to deps/v8.
-    'v8_embedder_string': '-node.29',
+    'v8_embedder_string': '-node.30',
 
     ##### V8 defaults for Node.js #####
 

deps/v8/src/codegen/x64/assembler-x64.h

@@ -1562,6 +1562,10 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
     vinstr(0x0F, dst, src1, src2, k66, k0F3A, kWIG);
     emit(imm8);
   }
+  void vpalignr(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8) {
+    vinstr(0x0F, dst, src1, src2, k66, k0F3A, kWIG);
+    emit(imm8);
+  }
 
   void vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
   void vps(byte op, XMMRegister dst, XMMRegister src1, Operand src2);

deps/v8/src/compiler/backend/x64/code-generator-x64.cc

@@ -579,10 +579,14 @@ void EmitWordLoadPoisoningIfNeeded(CodeGenerator* codegen,
     ASSEMBLE_SIMD_INSTR(opcode, dst, input_index);       \
   } while (false)
 
-#define ASSEMBLE_SIMD_IMM_SHUFFLE(opcode, imm)                            \
-  do {                                                                    \
-    DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));      \
-    __ opcode(i.OutputSimd128Register(), i.InputSimd128Register(1), imm); \
+#define ASSEMBLE_SIMD_IMM_SHUFFLE(opcode, imm)                              \
+  do {                                                                      \
+    DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));        \
+    if (instr->InputAt(1)->IsSimd128Register()) {                           \
+      __ opcode(i.OutputSimd128Register(), i.InputSimd128Register(1), imm); \
+    } else {                                                                \
+      __ opcode(i.OutputSimd128Register(), i.InputOperand(1), imm);         \
+    }                                                                       \
   } while (false)
 
 #define ASSEMBLE_SIMD_ALL_TRUE(opcode)          \

deps/v8/test/cctest/test-disasm-x64.cc

@@ -813,6 +813,7 @@ TEST(DisasmX64) {
       __ vpblendw(xmm1, xmm2, xmm3, 23);
       __ vpblendw(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 23);
       __ vpalignr(xmm1, xmm2, xmm3, 4);
+      __ vpalignr(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 4);
 
       __ vblendvpd(xmm1, xmm2, xmm3, xmm4);