Add start packet strobe timing outputs to MAC modules

Author: alexforencich

rtl/axis_gmii_rx.v

@@ -58,6 +58,7 @@ module axis_gmii_rx
     /*
      * Status
      */
+    output wire        start_packet,
     output wire        error_bad_frame,
     output wire        error_bad_fcs
 );
@@ -103,6 +104,7 @@ reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
 reg m_axis_tlast_reg = 1'b0, m_axis_tlast_next;
 reg m_axis_tuser_reg = 1'b0, m_axis_tuser_next;
 
+reg start_packet_reg = 1'b0, start_packet_next;
 reg error_bad_frame_reg = 1'b0, error_bad_frame_next;
 reg error_bad_fcs_reg = 1'b0, error_bad_fcs_next;
 
@@ -114,6 +116,7 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
+assign start_packet = start_packet_reg;
 assign error_bad_frame = error_bad_frame_reg;
 assign error_bad_fcs = error_bad_fcs_reg;
 
@@ -144,6 +147,7 @@ always @* begin
     m_axis_tlast_next = 1'b0;
     m_axis_tuser_next = 1'b0;
 
+    start_packet_next = 1'b0;
     error_bad_frame_next = 1'b0;
     error_bad_fcs_next = 1'b0;
 
@@ -160,6 +164,7 @@ always @* begin
                 reset_crc = 1'b1;
 
                 if (gmii_rx_dv_d4 && !gmii_rx_er_d4 && gmii_rxd_d4 == ETH_SFD) begin
+                    start_packet_next = 1'b1;
                     state_next = STATE_PAYLOAD;
                 end else begin
                     state_next = STATE_IDLE;
@@ -218,6 +223,7 @@ always @(posedge clk) begin
 
         m_axis_tvalid_reg <= 1'b0;
 
+        start_packet_reg <= 1'b0;
         error_bad_frame_reg <= 1'b0;
         error_bad_fcs_reg <= 1'b0;
 
@@ -236,6 +242,7 @@ always @(posedge clk) begin
 
         m_axis_tvalid_reg <= m_axis_tvalid_next;
 
+        start_packet_reg <= start_packet_next;
         error_bad_frame_reg <= error_bad_frame_next;
         error_bad_fcs_reg <= error_bad_fcs_next;
 

rtl/axis_gmii_tx.v

@@ -63,7 +63,12 @@ module axis_gmii_tx #
     /*
      * Configuration
      */
-    input  wire [7:0]  ifg_delay
+    input  wire [7:0]  ifg_delay,
+
+    /*
+     * Status
+     */
+    output wire        start_packet
 );
 
 localparam [7:0]
@@ -99,6 +104,8 @@ reg gmii_tx_er_reg = 1'b0, gmii_tx_er_next;
 
 reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
 
+reg start_packet_reg = 1'b0, start_packet_next;
+
 reg [31:0] crc_state = 32'hFFFFFFFF;
 wire [31:0] crc_next;
 
@@ -108,6 +115,8 @@ assign gmii_txd = gmii_txd_reg;
 assign gmii_tx_en = gmii_tx_en_reg;
 assign gmii_tx_er = gmii_tx_er_reg;
 
+assign start_packet = start_packet_reg;
+
 lfsr #(
     .LFSR_WIDTH(32),
     .LFSR_POLY(32'h4c11db7),
@@ -143,6 +152,8 @@ always @* begin
     gmii_tx_en_next = 1'b0;
     gmii_tx_er_next = 1'b0;
 
+    start_packet_next = 1'b0;
+
     if (!clk_enable) begin
         // clock disabled - hold state and outputs
         gmii_txd_next = gmii_txd_reg;
@@ -195,6 +206,7 @@ always @* begin
                         s_tdata_next = s_axis_tdata;
                     end
                     gmii_txd_next = ETH_SFD;
+                    start_packet_next = 1'b1;
                     state_next = STATE_PAYLOAD;
                 end else begin
                     state_next = STATE_PREAMBLE;
@@ -351,6 +363,8 @@ always @(posedge clk) begin
         gmii_tx_en_reg <= 1'b0;
         gmii_tx_er_reg <= 1'b0;
 
+        start_packet_reg <= 1'b0;
+
         crc_state <= 32'hFFFFFFFF;
     end else begin
         state_reg <= state_next;
@@ -362,6 +376,8 @@ always @(posedge clk) begin
         gmii_tx_en_reg <= gmii_tx_en_next;
         gmii_tx_er_reg <= gmii_tx_er_next;
 
+        start_packet_reg <= start_packet_next;
+
         // datapath
         if (reset_crc) begin
             crc_state <= 32'hFFFFFFFF;

rtl/axis_xgmii_rx_32.v

@@ -52,6 +52,7 @@ module axis_xgmii_rx_32
     /*
      * Status
      */
+    output wire        start_packet,
     output wire        error_bad_frame,
     output wire        error_bad_fcs
 );
@@ -94,6 +95,7 @@ reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
 reg m_axis_tlast_reg = 1'b0, m_axis_tlast_next;
 reg m_axis_tuser_reg = 1'b0, m_axis_tuser_next;
 
+reg start_packet_reg = 1'b0, start_packet_next;
 reg error_bad_frame_reg = 1'b0, error_bad_frame_next;
 reg error_bad_fcs_reg = 1'b0, error_bad_fcs_next;
 
@@ -120,6 +122,7 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
+assign start_packet = start_packet_reg;
 assign error_bad_frame = error_bad_frame_reg;
 assign error_bad_fcs = error_bad_fcs_reg;
 
@@ -260,6 +263,7 @@ always @* begin
     m_axis_tlast_next = 1'b0;
     m_axis_tuser_next = 1'b0;
 
+    start_packet_next = 1'b0;
     error_bad_frame_next = 1'b0;
     error_bad_fcs_next = 1'b0;
 
@@ -291,6 +295,7 @@ always @* begin
         STATE_PREAMBLE: begin
             // drop preamble
             update_crc = 1'b1;
+            start_packet_next = 1'b1;
             state_next = STATE_PAYLOAD;
         end
         STATE_PAYLOAD: begin
@@ -364,6 +369,7 @@ always @(posedge clk) begin
 
         m_axis_tvalid_reg <= 1'b0;
 
+        start_packet_reg <= 1'b0;
         error_bad_frame_reg <= 1'b0;
         error_bad_fcs_reg <= 1'b0;
 
@@ -380,6 +386,7 @@ always @(posedge clk) begin
 
         m_axis_tvalid_reg <= m_axis_tvalid_next;
 
+        start_packet_reg <= start_packet_next;
         error_bad_frame_reg <= error_bad_frame_next;
         error_bad_fcs_reg <= error_bad_fcs_next;
 

rtl/axis_xgmii_rx_64.v

@@ -52,6 +52,8 @@ module axis_xgmii_rx_64
     /*
      * Status
      */
+    output wire        start_packet_0,
+    output wire        start_packet_4,
     output wire        error_bad_frame,
     output wire        error_bad_fcs
 );
@@ -96,6 +98,8 @@ reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
 reg m_axis_tlast_reg = 1'b0, m_axis_tlast_next;
 reg m_axis_tuser_reg = 1'b0, m_axis_tuser_next;
 
+reg start_packet_0_reg = 1'b0;
+reg start_packet_4_reg = 1'b0;
 reg error_bad_frame_reg = 1'b0, error_bad_frame_next;
 reg error_bad_fcs_reg = 1'b0, error_bad_fcs_next;
 
@@ -122,6 +126,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
+assign start_packet_0 = start_packet_0_reg;
+assign start_packet_4 = start_packet_4_reg;
 assign error_bad_frame = error_bad_frame_reg;
 assign error_bad_fcs = error_bad_fcs_reg;
 
@@ -419,6 +425,8 @@ always @(posedge clk) begin
 
         m_axis_tvalid_reg <= 1'b0;
 
+        start_packet_0_reg <= 1'b0;
+        start_packet_4_reg <= 1'b0;
         error_bad_frame_reg <= 1'b0;
         error_bad_fcs_reg <= 1'b0;
 
@@ -435,14 +443,18 @@ always @(posedge clk) begin
 
         m_axis_tvalid_reg <= m_axis_tvalid_next;
 
+        start_packet_0_reg <= 1'b0;
+        start_packet_4_reg <= 1'b0;
         error_bad_frame_reg <= error_bad_frame_next;
         error_bad_fcs_reg <= error_bad_fcs_next;
 
         if (xgmii_rxc[0] && xgmii_rxd[7:0] == XGMII_START) begin
             lanes_swapped <= 1'b0;
+            start_packet_0_reg <= 1'b1;
             xgmii_rxc_d0 <= xgmii_rxc;
         end else if (xgmii_rxc[4] && xgmii_rxd[39:32] == XGMII_START) begin
             lanes_swapped <= 1'b1;
+            start_packet_4_reg <= 1'b1;
             xgmii_rxc_d0 <= {xgmii_rxc[3:0], swap_rxc};
         end else if (lanes_swapped) begin
             xgmii_rxc_d0 <= {xgmii_rxc[3:0], swap_rxc};

rtl/axis_xgmii_tx_32.v

@@ -58,7 +58,12 @@ module axis_xgmii_tx_32 #
     /*
      * Configuration
      */
-    input  wire [7:0]  ifg_delay
+    input  wire [7:0]  ifg_delay,
+
+    /*
+     * Status
+     */
+    output wire        start_packet
 );
 
 localparam MIN_FL_NOCRC = MIN_FRAME_LENGTH-4;
@@ -123,11 +128,15 @@ wire [31:0] crc_next3;
 reg [31:0] xgmii_txd_reg = {4{XGMII_IDLE}}, xgmii_txd_next;
 reg [3:0] xgmii_txc_reg = 4'b1111, xgmii_txc_next;
 
+reg start_packet_reg = 1'b0, start_packet_next;
+
 assign s_axis_tready = s_axis_tready_reg;
 
 assign xgmii_txd = xgmii_txd_reg;
 assign xgmii_txc = xgmii_txc_reg;
 
+assign start_packet = start_packet_reg;
+
 lfsr #(
     .LFSR_WIDTH(32),
     .LFSR_POLY(32'h4c11db7),
@@ -278,6 +287,8 @@ always @* begin
     xgmii_txd_next = {4{XGMII_IDLE}};
     xgmii_txc_next = 4'b1111;
 
+    start_packet_next = 1'b0;
+
     case (state_reg)
         STATE_IDLE: begin
             // idle state - wait for data
@@ -312,6 +323,7 @@ always @* begin
             xgmii_txd_next = {ETH_SFD, {3{ETH_PRE}}};
             xgmii_txc_next = 4'b0000;
             s_axis_tready_next = 1'b1;
+            start_packet_next = 1'b1;
             state_next = STATE_PAYLOAD;
         end
         STATE_PAYLOAD: begin
@@ -519,6 +531,8 @@ always @(posedge clk) begin
         xgmii_txd_reg <= {4{XGMII_IDLE}};
         xgmii_txc_reg <= 4'b1111;
 
+        start_packet_reg <= 1'b0;
+
         crc_state <= 32'hFFFFFFFF;
     end else begin
         state_reg <= state_next;
@@ -533,6 +547,8 @@ always @(posedge clk) begin
         xgmii_txd_reg <= xgmii_txd_next;
         xgmii_txc_reg <= xgmii_txc_next;
 
+        start_packet_reg <= start_packet_next;
+
         // datapath
         if (reset_crc) begin
             crc_state <= 32'hFFFFFFFF;

rtl/axis_xgmii_tx_64.v

@@ -58,7 +58,13 @@ module axis_xgmii_tx_64 #
     /*
      * Configuration
      */
-    input  wire [7:0]  ifg_delay
+    input  wire [7:0]  ifg_delay,
+
+    /*
+     * Status
+     */
+    output wire        start_packet_0,
+    output wire        start_packet_4
 );
 
 localparam MIN_FL_NOCRC = MIN_FRAME_LENGTH-4;
@@ -132,11 +138,17 @@ wire [31:0] crc_next7;
 reg [63:0] xgmii_txd_reg = {8{XGMII_IDLE}}, xgmii_txd_next;
 reg [7:0] xgmii_txc_reg = 8'b11111111, xgmii_txc_next;
 
+reg start_packet_0_reg = 1'b0, start_packet_0_next;
+reg start_packet_4_reg = 1'b0, start_packet_4_next;
+
 assign s_axis_tready = s_axis_tready_reg;
 
 assign xgmii_txd = xgmii_txd_reg;
 assign xgmii_txc = xgmii_txc_reg;
 
+assign start_packet_0 = start_packet_0_reg;
+assign start_packet_4 = start_packet_4_reg;
+
 lfsr #(
     .LFSR_WIDTH(32),
     .LFSR_POLY(32'h4c11db7),
@@ -390,6 +402,9 @@ always @* begin
     xgmii_txd_next = {8{XGMII_IDLE}};
     xgmii_txc_next = 8'b11111111;
 
+    start_packet_0_next = 1'b0;
+    start_packet_4_next = 1'b0;
+
     case (state_reg)
         STATE_IDLE: begin
             // idle state - wait for data
@@ -409,9 +424,11 @@ always @* begin
                 if (ifg_count_reg > 8'd0) begin
                     // need to send more idles - swap lanes
                     swap_lanes = 1'b1;
+                    start_packet_4_next = 1'b1;
                 end else begin
                     // no more idles - unswap
                     unswap_lanes = 1'b1;
+                    start_packet_0_next = 1'b1;
                 end
                 xgmii_txd_next = {ETH_SFD, {6{ETH_PRE}}, XGMII_START};
                 xgmii_txc_next = 8'b00000001;
@@ -635,6 +652,9 @@ always @(posedge clk) begin
         xgmii_txd_reg <= {8{XGMII_IDLE}};
         xgmii_txc_reg <= 8'b11111111;
 
+        start_packet_0_reg <= 1'b0;
+        start_packet_4_reg <= 1'b0;
+
         crc_state <= 32'hFFFFFFFF;
 
         lanes_swapped <= 1'b0;
@@ -648,6 +668,9 @@ always @(posedge clk) begin
 
         s_axis_tready_reg <= s_axis_tready_next;
 
+        start_packet_0_reg <= start_packet_0_next;
+        start_packet_4_reg <= start_packet_4_next;
+
         if (swap_lanes || (lanes_swapped && !unswap_lanes)) begin
             lanes_swapped <= 1'b1;
             xgmii_txd_reg <= {xgmii_txd_next[31:0], swap_txd};