Add vhier --includes.

Author: wsnyder

Changes

@@ -6,6 +6,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 * Verilog-Perl 3.471 devel
 
+***   Add vhier --includes. [Gregory Pierce]
+
 ****  Add error on misused define (#1659). [Topa Tota]
 
 ****  Fix packages as enum base types, Verilator bug 2202. [Driss Hafdi]

Getopt.pm

@@ -40,6 +40,7 @@ sub new {
 
     my $self = {defines => {},
 		incdir => ['.', ],
+		includes => {},
 		module_dir => ['.', ],
 		libext => ['.v', ],
 		library => [ ],
@@ -335,6 +336,17 @@ sub write_parameters_file {
     $fh->close;
 }
 
+sub includes {
+    my $self = shift;
+    if (@_) {
+	my $from_filename = shift;
+	my $inc_filename = shift;
+	$self->{includes}{$from_filename} ||= [];
+	push @{$self->{includes}{$from_filename}}, $inc_filename;
+    }
+    return $self->{includes};
+}
+
 #######################################################################
 # Utility functions
 
@@ -756,6 +768,13 @@ undefined variables are not substituted nor cause errors.
 Returns reference to list of include directories.  With argument, adds that
 directory.
 
+=item $self->includes
+
+Returns reference to hash of files that included some file, and for each
+hash value a list of files included.  Only relevant after Verilog::Netlist
+processing.  With two arguments, adds an include for the given referencing
+filename to the given include filename.
+
 =item $self->libext
 
 Returns reference to list of library extensions.  With argument, adds that

MANIFEST

@@ -137,6 +137,7 @@ t/80_vppreproc_simple.out
 t/85_vhier.t
 t/85_vhier_cells.out
 t/85_vhier_forest.out
+t/85_vhier_includes.out
 t/85_vhier_inpfiles.out
 t/85_vhier_modfiles.out
 t/85_vhier_resolvefiles.out
@@ -172,6 +173,7 @@ verilog/test.v
 verilog/test.vrename
 verilog/v_comments.v
 verilog/v_gate.v
+verilog/v_hier_inc.vh
 verilog/v_hier_noport.v
 verilog/v_hier_sub.v
 verilog/v_hier_subprim.v

Preproc/Preproc.pm

@@ -171,6 +171,7 @@ sub def_substitute {
 sub include {
     my ($self,$filename)=@_;
     print "INCLUDE $filename\n" if $self->{debug};
+    $self->{options}->includes($self->filename, $filename);
     $self->open(filename => $filename,
 		open_nonfatal => $self->{include_open_nonfatal},
 		);

t/85_vhier.t

@@ -9,19 +9,20 @@ use IO::File;
 use strict;
 use Test::More;
 
-BEGIN { plan tests => 17 }
+BEGIN { plan tests => 19 }
 BEGIN { require "./t/test_utils.pl"; }
 
 print "Checking vhier...\n";
 
 vhier ("t/85_vhier_cells.out",	    "--cells");
+vhier ("t/85_vhier_includes.out",   "--includes");
 vhier ("t/85_vhier_inpfiles.out",   "--input-files");
 vhier ("t/85_vhier_resolvefiles.out","--resolve-files");
 vhier ("t/85_vhier_modfiles.out",   "--module-files --language 2001");
 vhier ("t/85_vhier_topmodule.out",  "--module-files --top-module v_hier_sub");
 vhier ("t/85_vhier_forest.out",	    "--forest --instance");
 vhier ("t/85_vhier_skiplist.out",   "--forest --instance --skiplist t/85_vhier_skiplist.dat");
-vhier ("t/85_vhier_xml.out",	    "--xml --cells --input-files --module-files --missing-modules");
+vhier ("t/85_vhier_xml.out",	    "--xml --cells --includes --input-files --module-files --missing-modules");
 check_valid_xml("test_dir/vhier.out");
 
 sub vhier {

t/85_vhier_includes.out

@@ -0,0 +1,2 @@
+  verilog/v_hier_top.v
+    v_hier_inc.vh

t/85_vhier_inpfiles.out

@@ -1,3 +1,4 @@
+  verilog/v_hier_inc.vh
   verilog/v_hier_sub.v
   verilog/v_hier_subsub.v
   verilog/v_hier_top.v

t/85_vhier_xml.out

@@ -18,11 +18,16 @@
      <file>verilog/v_hier_subsub.v</file>
  </module_files>
  <input_files>
+  <file>verilog/v_hier_inc.vh</file>
   <file>verilog/v_hier_sub.v</file>
   <file>verilog/v_hier_subsub.v</file>
   <file>verilog/v_hier_top.v</file>
   <file>verilog/v_recursive.v</file>
  </input_files>
+ <includes>
+  <file>verilog/v_hier_top.v</file>
+    <inc>v_hier_inc.vh</inc>
+ </includes>
  <missing_modules>
   <module name="missing" />
  </missing_modules>

verilog/v_hier_inc.vh

@@ -0,0 +1,10 @@
+// DESCRIPTION: Verilog-Perl: Example Verilog for testing package
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2000-2012 by Wilson Snyder.
+
+`ifndef V_HIER_INC_VH
+`define V_HIER_INC_VH  // Guard
+
+`define hsub v_hier_sub
+
+`endif  // Guard

verilog/v_hier_top.v

@@ -2,7 +2,7 @@
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2000-2012 by Wilson Snyder.
 
-`define hsub v_hier_sub
+`include "v_hier_inc.vh"
 
 module v_hier_top (/*AUTOARG*/
    // Inputs