Fix multidimensional cell/interfaces, bug1505.

Author: wsnyder

Changes

@@ -8,6 +8,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****    Support ${} for env vars in file lists, msg3065.
 
+****    Fix multidimensional cell/interfaces, bug1505. [Anderson Ignacio Da Silva]
+
 
 * Verilog::Language 3.466 2019-05-04
 

Parser/VParseBison.y

@@ -2210,7 +2210,7 @@ mpInstnameParen:		// Similar to instnameParen, but for modport instantiations wh
 
 mpInstname:			// Similar to instname, but for modport instantiations which have no parenthesis
 	//			// id is-a: interface_port_identifier   (interface.modport)
-		id instRangeE	 			{ PARSEP->instantCb($<fl>1, GRAMMARP->m_cellMod, $1, $2); }
+		id instRangeListE			{ PARSEP->instantCb($<fl>1, GRAMMARP->m_cellMod, $1, $2); }
 	;
 
 instnameList:
@@ -2227,13 +2227,22 @@ instname:
 	//			// 	 or instance_identifier   (module)
 	//			// 	 or instance_identifier   (program)
 	//			// 	 or udp_instance	  (udp)
-		id instRangeE '(' 			{ PARSEP->instantCb($<fl>1, GRAMMARP->m_cellMod, $1, $2); PINPARAMS(); }
-	|	instRangeE '(' 				{ PARSEP->instantCb($<fl>2, GRAMMARP->m_cellMod, "", $1); PINPARAMS(); } // UDP
+		id instRangeListE '(' 			{ PARSEP->instantCb($<fl>1, GRAMMARP->m_cellMod, $1, $2); PINPARAMS(); }
+	|	instRangeListE '(' 			{ PARSEP->instantCb($<fl>2, GRAMMARP->m_cellMod, "", $1); PINPARAMS(); } // UDP
 	;
 
-instRangeE<str>:
+instRangeListE<str>:
 		/* empty */				{ $$ = ""; }
-	|	'[' constExpr ']'			{ $<fl>$=$<fl>1; $$ = "["+$2+"]"; }
+	|	instRangeList				{ $<fl>$=$<fl>1; $$ = $1; }
+	;
+
+instRangeList<str>:
+		instRange				{ $<fl>$=$<fl>1; $$ = $1; }
+	|	instRangeList instRange			{ $<fl>$=$<fl>1; $$ = $1+$2; }
+	;
+
+instRange<str>:
+		'[' constExpr ']'			{ $<fl>$=$<fl>1; $$ = "["+$2+"]"; }
 	|	'[' constExpr ':' constExpr ']'		{ $<fl>$=$<fl>1; $$ = "["+$2+":"+$4+"]"; }
 	;
 

t/35_sigparser.out

@@ -543,6 +543,14 @@ verilog/parser_bugs.v:576: VAR  'var' 'mynet1' 'module' '' 'net1_t' '' ''
 verilog/parser_bugs.v:578: VAR  'var' 'mynet2' 'module' '' 'net2_t' '' ''
 verilog/parser_bugs.v:580: VAR  'var' 'mynet3' 'module' '' 'net3_t' '' ''
 verilog/parser_bugs.v:581: ENDMODULE  'endmodule'
+verilog/parser_bugs.v:583: MODULE  'module' 'bug1505' undef '0'
+verilog/parser_bugs.v:584: INSTANT  'sub' 'i_suba' ''
+verilog/parser_bugs.v:584: ENDCELL  ''
+verilog/parser_bugs.v:585: INSTANT  'sub' 'i_subb' '[1:2]'
+verilog/parser_bugs.v:585: ENDCELL  ''
+verilog/parser_bugs.v:586: INSTANT  'sub' 'i_subc' '[1:2][3:4][5:6]'
+verilog/parser_bugs.v:586: ENDCELL  ''
+verilog/parser_bugs.v:587: ENDMODULE  'endmodule'
 verilog/pinorder.v:001: COMMENT  '// DESCRIPTION: Verilog-Perl: Example Verilog for testing package'
 verilog/pinorder.v:002: COMMENT  '//'
 verilog/pinorder.v:003: COMMENT  '// This file ONLY is placed into the Public Domain, for any use,'

t/35_sigparser_ps.out

@@ -571,6 +571,14 @@ verilog/parser_bugs.v:576: VAR  'var' 'mynet1' 'module' '' 'net1_t' '' ''
 verilog/parser_bugs.v:578: VAR  'var' 'mynet2' 'module' '' 'net2_t' '' ''
 verilog/parser_bugs.v:580: VAR  'var' 'mynet3' 'module' '' 'net3_t' '' ''
 verilog/parser_bugs.v:581: ENDMODULE  'endmodule'
+verilog/parser_bugs.v:583: MODULE  'module' 'bug1505' undef '0'
+verilog/parser_bugs.v:584: INSTANT  'sub' 'i_suba' ''
+verilog/parser_bugs.v:584: ENDCELL  ''
+verilog/parser_bugs.v:585: INSTANT  'sub' 'i_subb' '[1:2]'
+verilog/parser_bugs.v:585: ENDCELL  ''
+verilog/parser_bugs.v:586: INSTANT  'sub' 'i_subc' '[1:2][3:4][5:6]'
+verilog/parser_bugs.v:586: ENDCELL  ''
+verilog/parser_bugs.v:587: ENDMODULE  'endmodule'
 verilog/pinorder.v:001: COMMENT  '// DESCRIPTION: Verilog-Perl: Example Verilog for testing package'
 verilog/pinorder.v:002: COMMENT  '//'
 verilog/pinorder.v:003: COMMENT  '// This file ONLY is placed into the Public Domain, for any use,'

verilog/parser_bugs.v

@@ -579,3 +579,9 @@ module msg2931;
    nettype net_t net3_t;
    net3_t mynet3;
 endmodule
+
+module bug1505;
+   sub i_suba ();
+   sub i_subb[1:2] ();
+   sub i_subc[1:2][3:4][5:6] ();
+endmodule