up_adc_common: Add register data reading/writing functionality

Author: alin724

library/common/up_adc_common.v

@@ -101,6 +101,14 @@ module up_adc_common #(
   input               up_drp_ready,
   input               up_drp_locked,
 
+  // ADC custom read/write interface
+
+  output      [31:0]  adc_custom_wr,
+  output              adc_write_req,
+  input       [31:0]  adc_custom_rd,
+  input               adc_read_valid,
+  output              adc_read_req,
+
   // user channel control
 
   output      [ 7:0]  up_usr_chanmax_out,
@@ -156,11 +164,15 @@ module up_adc_common #(
   reg         [31:0]  up_rdata_int = 'd0;
   reg         [ 7:0]  up_adc_custom_control = 'd0;
   reg                 up_adc_crc_enable = 'd0;
+  reg         [31:0]  up_adc_custom_wr = 'd0;
 
   // internal signals
 
   wire                up_wreq_s;
   wire                up_rreq_s;
+  wire                up_rack_s;
+  wire                up_write_req;
+  wire                up_read_req;
   wire                up_status_s;
   wire                up_sync_status_s;
   wire                up_status_ovf_s;
@@ -169,6 +181,8 @@ module up_adc_common #(
   wire                up_drp_status_s;
   wire                up_drp_rwn_s;
   wire        [31:0]  up_drp_rdata_hold_s;
+  wire                up_adc_read_valid;
+  wire        [31:0]  up_adc_custom_rd;
 
   wire                adc_rst_n;
   wire                adc_rst_s;
@@ -177,6 +191,9 @@ module up_adc_common #(
 
   assign up_wreq_s = (up_waddr[13:7] == {COMMON_ID,1'b0}) ? up_wreq : 1'b0;
   assign up_rreq_s = (up_raddr[13:7] == {COMMON_ID,1'b0}) ? up_rreq : 1'b0;
+  assign up_rack_s = (up_raddr[6:0] == 7'h21) ? up_adc_read_valid : up_rreq_s;
+  assign up_write_req = (up_waddr[6:0] == 7'h20) ? up_wreq : 1'b0;
+  assign up_read_req = (up_raddr[6:0] == 7'h21) ? up_rreq : 1'b0;
 
   // processor write interface
 
@@ -335,6 +352,16 @@ module up_adc_common #(
   end
   endgenerate
 
+  always @(posedge up_clk) begin
+    if (up_rstn == 0) begin
+      up_adc_custom_wr <= 'd0;
+    end else begin
+      if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h20)) begin
+         up_adc_custom_wr <= up_wdata;
+      end
+    end
+  end
+
   always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_status_ovf <= 'd0;
@@ -429,8 +456,8 @@ module up_adc_common #(
       up_rack_int <= 'd0;
       up_rdata_int <= 'd0;
     end else begin
-      up_rack_int <= up_rreq_s;
-      if (up_rreq_s == 1'b1) begin
+      up_rack_int <= up_rack_s;
+      if (up_rack_s == 1'b1) begin
         case (up_raddr[6:0])
           7'h00: up_rdata_int <= VERSION;
           7'h01: up_rdata_int <= ID;
@@ -457,6 +484,8 @@ module up_adc_common #(
           7'h1d: up_rdata_int <= {14'd0, up_drp_locked, up_drp_status_s, 16'b0};
           7'h1e: up_rdata_int <= up_drp_wdata;
           7'h1f: up_rdata_int <= up_drp_rdata_hold_s;
+          7'h20: up_rdata_int <= up_adc_custom_wr;
+          7'h21: up_rdata_int <= up_adc_custom_rd;
           7'h22: up_rdata_int <= {29'd0, up_status_ovf, 2'b0};
           7'h23: up_rdata_int <= 32'd8;
           7'h28: up_rdata_int <= {24'd0, up_usr_chanmax_in};
@@ -491,7 +520,7 @@ module up_adc_common #(
   // adc control & status
 
   up_xfer_cntrl #(
-    .DATA_WIDTH(58)
+    .DATA_WIDTH(92)
   ) i_xfer_cntrl (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
@@ -506,6 +535,9 @@ module up_adc_common #(
                       up_adc_ext_sync_disarm,
                       up_adc_ext_sync_manual_req,
                       up_adc_sync,
+                      up_write_req,
+                      up_read_req,
+                      up_adc_custom_wr,
                       up_adc_start_code,
                       up_adc_r1_mode,
                       up_adc_ddr_edgesel,
@@ -525,6 +557,9 @@ module up_adc_common #(
                       adc_ext_sync_disarm,
                       adc_ext_sync_manual_req,
                       adc_sync,
+                      adc_write_req,
+                      adc_read_req,
+                      adc_custom_wr,
                       adc_start_code,
                       adc_r1_mode,
                       adc_ddr_edgesel,
@@ -538,18 +573,22 @@ module up_adc_common #(
   assign adc_rst = ~adc_rst_n;
 
   up_xfer_status #(
-    .DATA_WIDTH(3)
+    .DATA_WIDTH(36)
   ) i_xfer_status (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_status ({up_sync_status_s,
                       up_status_s,
-                      up_status_ovf_s}),
+                      up_status_ovf_s,
+                      up_adc_read_valid,
+                      up_adc_custom_rd}),
     .d_rst (adc_rst_s),
     .d_clk (adc_clk),
     .d_data_status ({ adc_sync_status,
                       adc_status,
-                      adc_status_ovf}));
+                      adc_status_ovf,
+                      adc_read_valid,
+                      adc_custom_rd}));
 
   // adc clock monitor