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‎projects/ad9083_vna/Makefile‎

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####################################################################################
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## Copyright (c) 2018 - 2021 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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include ../scripts/project-toplevel.mk

‎projects/ad9083_vna/Readme.md‎

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# AD9083-VNA HDL Project
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Here are some pointers to help you:
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* [Board Product Page](https://www.analog.com/eval-ad9083-vna)
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* Part : [AD9083 - 16-Channel, 125 MHz Bandwidth, JESD204B Analog-to-Digital Converter](https://www.analog.com/ad9083)
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* Part : [ADMV8818 - 2 GHz to 18 GHz, Digitally Tunable, High-Pass and Low-Pass Filter](https://www.analog.com/admv8818)
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* Part : [ADRF5021 - 9 kHz to 30 GHz, Silicon SPDT Switch](https://www.analog.com/adrf5021)
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* Part : [ADRF5045 - 9 kHz to 30 GHz, Silicon, SP4T Switch](https://www.analog.com/adrf5045)
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* Part : [ADF4371S - Microwave Wideband Synthesizer with Integrated VCO](https://www.analog.com/adf4371)
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* Part : [ADL5960 - 10 MHz to 20 GHz, Integrated Vector Network Analyzer Front-End](https://www.analog.com/adl5960)
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* Part : [HMC8411 - Low Noise Amplifier, 0.01 GHz to 10 GHz](https://www.analog.com/hmc8411)
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* Part : [HMC994 - 0.5 Watt Power Amplifier, DC - 30 GHz](https://www.analog.com/hmc994)
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* Project Doc: https://wiki.analog.com/resources/eval/ad9083-vna
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* HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad9083_vna/ad9083_vna_reference_hdl
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* Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ad9083

‎projects/ad9083_vna/common/ad9083_vna_bd.tcl‎

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# RX parameters
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set RX_NUM_OF_LANES 1 ; # L
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set RX_NUM_OF_CONVERTERS 32 ; # M
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set RX_SAMPLES_PER_FRAME 1 ; # S
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set RX_SAMPLE_WIDTH 16 ; # N/NP
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source ../../ad9083_evb/common/ad9083_evb_bd.tcl
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# add spi interfaces
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create_bd_port -dir O -from 1 -to 0 spi_bus1_csn_o
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create_bd_port -dir I -from 1 -to 0 spi_bus1_csn_i
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create_bd_port -dir I spi_bus1_clk_i
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create_bd_port -dir O spi_bus1_clk_o
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create_bd_port -dir I spi_bus1_sdo_i
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create_bd_port -dir O spi_bus1_sdo_o
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create_bd_port -dir I spi_bus1_sdi_i
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create_bd_port -dir O -from 3 -to 0 spi_adl5960_1_csn_o
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create_bd_port -dir I -from 3 -to 0 spi_adl5960_1_csn_i
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create_bd_port -dir I spi_adl5960_1_clk_i
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create_bd_port -dir O spi_adl5960_1_clk_o
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create_bd_port -dir I spi_adl5960_1_sdo_i
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create_bd_port -dir O spi_adl5960_1_sdo_o
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create_bd_port -dir I spi_adl5960_1_sdi_i
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create_bd_port -dir O -from 3 -to 0 spi_adl5960_2_csn_o
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create_bd_port -dir I -from 3 -to 0 spi_adl5960_2_csn_i
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create_bd_port -dir I spi_adl5960_2_clk_i
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create_bd_port -dir O spi_adl5960_2_clk_o
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create_bd_port -dir I spi_adl5960_2_sdo_i
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create_bd_port -dir O spi_adl5960_2_sdo_o
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create_bd_port -dir I spi_adl5960_2_sdi_i
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# spi instances
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ad_ip_instance axi_quad_spi axi_spi_bus1
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ad_ip_parameter axi_spi_bus1 CONFIG.C_USE_STARTUP 0
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ad_ip_parameter axi_spi_bus1 CONFIG.C_NUM_SS_BITS 2
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ad_ip_parameter axi_spi_bus1 CONFIG.C_SCK_RATIO 8
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ad_ip_instance axi_quad_spi axi_spi_adl5960_1
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ad_ip_parameter axi_spi_adl5960_1 CONFIG.C_USE_STARTUP 0
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ad_ip_parameter axi_spi_adl5960_1 CONFIG.C_NUM_SS_BITS 4
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ad_ip_parameter axi_spi_adl5960_1 CONFIG.C_SCK_RATIO 16
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ad_ip_parameter axi_spi_adl5960_1 CONFIG.Multiples16 8
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ad_ip_instance axi_quad_spi axi_spi_adl5960_2
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ad_ip_parameter axi_spi_adl5960_2 CONFIG.C_USE_STARTUP 0
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ad_ip_parameter axi_spi_adl5960_2 CONFIG.C_NUM_SS_BITS 4
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ad_ip_parameter axi_spi_adl5960_2 CONFIG.C_SCK_RATIO 16
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ad_ip_parameter axi_spi_adl5960_2 CONFIG.Multiples16 8
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# spi connections
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ad_connect sys_cpu_clk axi_spi_bus1/ext_spi_clk
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ad_connect spi_bus1_csn_i axi_spi_bus1/ss_i
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ad_connect spi_bus1_csn_o axi_spi_bus1/ss_o
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ad_connect spi_bus1_clk_i axi_spi_bus1/sck_i
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ad_connect spi_bus1_clk_o axi_spi_bus1/sck_o
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ad_connect spi_bus1_sdo_i axi_spi_bus1/io0_i
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ad_connect spi_bus1_sdo_o axi_spi_bus1/io0_o
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ad_connect spi_bus1_sdi_i axi_spi_bus1/io1_i
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ad_connect sys_cpu_clk axi_spi_adl5960_1/ext_spi_clk
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ad_connect spi_adl5960_1_csn_i axi_spi_adl5960_1/ss_i
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ad_connect spi_adl5960_1_csn_o axi_spi_adl5960_1/ss_o
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ad_connect spi_adl5960_1_clk_i axi_spi_adl5960_1/sck_i
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ad_connect spi_adl5960_1_clk_o axi_spi_adl5960_1/sck_o
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ad_connect spi_adl5960_1_sdo_i axi_spi_adl5960_1/io0_i
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ad_connect spi_adl5960_1_sdo_o axi_spi_adl5960_1/io0_o
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ad_connect spi_adl5960_1_sdi_i axi_spi_adl5960_1/io1_i
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ad_connect sys_cpu_clk axi_spi_adl5960_2/ext_spi_clk
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ad_connect spi_adl5960_2_csn_i axi_spi_adl5960_2/ss_i
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ad_connect spi_adl5960_2_csn_o axi_spi_adl5960_2/ss_o
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ad_connect spi_adl5960_2_clk_i axi_spi_adl5960_2/sck_i
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ad_connect spi_adl5960_2_clk_o axi_spi_adl5960_2/sck_o
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ad_connect spi_adl5960_2_sdo_i axi_spi_adl5960_2/io0_i
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ad_connect spi_adl5960_2_sdo_o axi_spi_adl5960_2/io0_o
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ad_connect spi_adl5960_2_sdi_i axi_spi_adl5960_2/io1_i
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ad_cpu_interconnect 0x48000000 axi_spi_bus1
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ad_cpu_interconnect 0x48100000 axi_spi_adl5960_1
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ad_cpu_interconnect 0x48200000 axi_spi_adl5960_2
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# interrupts
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ad_cpu_interrupt ps-9 mb-8 axi_spi_bus1/ip2intc_irpt
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ad_cpu_interrupt ps-10 mb-15 axi_spi_adl5960_1/ip2intc_irpt
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ad_cpu_interrupt ps-11 mb-14 axi_spi_adl5960_2/ip2intc_irpt

‎projects/ad9083_vna/zcu102/Makefile‎

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####################################################################################
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## Copyright (c) 2018 - 2021 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := ad9083_vna_zcu102
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M_DEPS += ../common/ad9083_vna_bd.tcl
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M_DEPS += ../../scripts/adi_pd.tcl
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M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
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M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
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M_DEPS += ../../ad9083_evb/common/ad9083_evb_bd.tcl
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M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
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M_DEPS += ../../../library/common/ad_iobuf.v
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M_DEPS += ../../../library/common/ad_3w_spi.v
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_sysid
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LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
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LIB_DEPS += jesd204/axi_jesd204_rx
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LIB_DEPS += jesd204/jesd204_rx
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LIB_DEPS += sysid_rom
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += xilinx/axi_adxcvr
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LIB_DEPS += xilinx/util_adxcvr
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include ../../scripts/project-xilinx.mk

‎projects/ad9083_vna/zcu102/system_bd.tcl‎

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source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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source ../common/ad9083_vna_bd.tcl
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#system ID
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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sysid_gen_sys_init_file
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‎projects/ad9083_vna/zcu102/system_constr.xdc‎

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# ad9083
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set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports glblclk_p] ; ## G6 FMC_HPC0_LA00_CC_P
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set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports glblclk_n] ; ## G7 FMC_HPC0_LA00_CC_N
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set_property -dict {PACKAGE_PIN G8} [get_ports ref_clk0_p] ; ## D4 FMC_HPC0 GBTCLK0 M2C_C_P
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set_property -dict {PACKAGE_PIN G7} [get_ports ref_clk0_n] ; ## D5 FMC_HPC0_GBTCLK0_M2C_C_N
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set_property -dict {PACKAGE_PIN H2} [get_ports rx_data_p[0]] ; ## C6 FMC_HPC0_DP0_M2C_P
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set_property -dict {PACKAGE_PIN H1} [get_ports rx_data_n[0]] ; ## C7 FMC_HPC0_DP0_M2C_N
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set_property -dict {PACKAGE_PIN J4} [get_ports rx_data_p[1]] ; ## A2 FMC_HPC0_DP1_M2C_P
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set_property -dict {PACKAGE_PIN J3} [get_ports rx_data_n[1]] ; ## A3 FMC_HPC0_DP1_M2C_N
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set_property -dict {PACKAGE_PIN F2} [get_ports rx_data_p[2]] ; ## A6 FMC_HPC0_DP2_M2C_P
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set_property -dict {PACKAGE_PIN F1} [get_ports rx_data_n[2]] ; ## A7 FMC_HPC0_DP2_M2C_N
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set_property -dict {PACKAGE_PIN K2} [get_ports rx_data_p[3]] ; ## A10 FMC_HPC0_DP3_M2C_P
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set_property -dict {PACKAGE_PIN K1} [get_ports rx_data_n[3]] ; ## A11 FMC_HPC0_DP3_M2C_N
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set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS18} [get_ports spi_csn_clk] ; ## H14 FMC_HPC0_LA07_N
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set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS18} [get_ports spi_csn_adc] ; ## H7 FMC_HPC0_LA02_P
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set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D8 FMC_HPC0_LA01_CC_P
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set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVCMOS18} [get_ports spi_sdio] ; ## D9 FMC_HPC0_LA01_CC_N
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set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS18} [get_ports spi_sdo] ; ## C26 FMC_HPC0_LA27_P
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set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS18} [get_ports pwdn] ; ## H8 FMC_HPC0_LA02_N
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set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS18} [get_ports rstb] ; ## H13 FMC_HPC0_LA07_P
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set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports adc_lvsft_en] ; ## G9 FMC_HPC0_LA03_P
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set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## H10 FMC_HPC0_LA04_P
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set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## H11 FMC_HPC0_LA04_N
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set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVDS} [get_ports sysref_p] ; ## G12 FMC_HPC0_LA08_P
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set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVDS} [get_ports sysref_n] ; ## G13 FMC_HPC0_LA08_N
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set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports adl5960_temp_1] ; ## H16 FMC_HPC0_LA11_P
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set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports adl5960_temp_2] ; ## H17 FMC_HPC0_LA11_N
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set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports adl5960_temp_3] ; ## H19 FMC_HPC0_LA15_P
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set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports adl5960_temp_4] ; ## H20 FMC_HPC0_LA15_N
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set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports adl5960_temp_5] ; ## H22 FMC_HPC0_LA19_P
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set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports adl5960_temp_6] ; ## H23 FMC_HPC0_LA19_N
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set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports adl5960_temp_7] ; ## H25 FMC_HPC0_LA21_P
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set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports adl5960_temp_8] ; ## H26 FMC_HPC0_LA21_N
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set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS18} [get_ports gpio_sw0 ] ; ## D11 FMC_HPC0_LA05_P
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set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18} [get_ports gpio_sw1 ] ; ## D12 FMC_HPC0_LA05_N
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set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS18} [get_ports gpio_sw2 ] ; ## D14 FMC_HPC0_LA09_P
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set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS18} [get_ports gpio_sw3_v1] ; ## D15 FMC_HPC0_LA09_N
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set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS18} [get_ports gpio_sw3_v2] ; ## D17 FMC_HPC0_LA13_P
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set_property -dict {PACKAGE_PIN AC8 IOSTANDARD LVCMOS18} [get_ports gpio_sw4_v1] ; ## D18 FMC_HPC0_LA13_N
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set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS18} [get_ports gpio_sw4_v2] ; ## D20 FMC_HPC0_LA17_P_CC
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set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVCMOS18} [get_ports adl5960x_sync1] ; ## D21 FMC_HPC0_LA17_N_CC
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set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS18} [get_ports spi_bus0_sck] ; ## G18 FMC_HPC0_LA16_P
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set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS18} [get_ports spi_bus0_sdi] ; ## G15 FMC_HPC0_LA12_P
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set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS18} [get_ports spi_bus0_sdo] ; ## G16 FMC_HPC0_LA12_N
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set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports clkd_lvsft_en] ; ## G19 FMC_HPC0_LA16_N
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set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18} [get_ports spi_bus0_csn_f2] ; ## G21 FMC_HPC0_LA20_P
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set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS18} [get_ports spi_bus0_csn_sen] ; ## G22 FMC_HPC0_LA20_N
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set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS18} [get_ports spi_bus1_sck] ; ## G27 FMC_HPC0_LA25_P
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set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18} [get_ports spi_bus1_sdi] ; ## G24 FMC_HPC0_LA22_P
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set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18} [get_ports spi_bus1_sdo] ; ## G25 FMC_HPC0_LA22_N
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set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVCMOS18} [get_ports spi_bus1_csn_dat1] ; ## G28 FMC_HPC0_LA25_N
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set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS18} [get_ports spi_bus1_csn_dat2] ; ## G30 FMC_HPC0_LA29_P
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set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_1_sck] ; ## D23 FMC_HPC0_LA23_P
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set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_1_sdio] ; ## D24 FMC_HPC0_LA23_N
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set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_1_csn1] ; ## D26 FMC_HPC0_LA26_P
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set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_1_csn2] ; ## D27 FMC_HPC0_LA26_N
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set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_1_csn3] ; ## C10 FMC_HPC0_LA06_P
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set_property -dict {PACKAGE_PIN AC1 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_1_csn4] ; ## C11 FMC_HPC0_LA06_N
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set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_2_sck] ; ## C14 FMC_HPC0_LA10_P
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set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_2_sdio] ; ## C15 FMC_HPC0_LA10_N
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set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_2_csn5] ; ## C18 FMC_HPC0_LA14_P
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set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_2_csn6] ; ## C19 FMC_HPC0_LA14_N
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set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_2_csn7] ; ## C22 FMC_HPC0_LA18_P_CC
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set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports spi_adl5960_2_csn8] ; ## C23 FMC_HPC0_LA18_N_CC
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set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports prten[0]] ; ## H28 FMC_HPC0_LA24_P
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set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports prten[1]] ; ## H29 FMC_HPC0_LA24_N
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set_property -dict {PACKAGE_PIN T7 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports prten[2]] ; ## H31 FMC_HPC0_LA28_P
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set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports prten[3]] ; ## H32 FMC_HPC0_LA28_N
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set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports prten[4]] ; ## H34 FMC_HPC0_LA30_P
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set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports prten[5]] ; ## H35 FMC_HPC0_LA30_N
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set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports prten[6]] ; ## H37 FMC_HPC0_LA32_P
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set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports prten[7]] ; ## H38 FMC_HPC0_LA32_N
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# clocks
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create_clock -period 2 -name rx_ref_clk [get_ports ref_clk0_p]
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create_clock -period 8 -name rx_ref_clk2 [get_ports glblclk_p]
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set_input_delay -clock [get_clocks rx_ref_clk2] [get_property PERIOD [get_clocks rx_ref_clk2]] \
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[get_ports -regexp -filter { NAME =~ ".*sysref.*" && DIRECTION == "IN" }]
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create_generated_clock -name clk_sck0 \
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-source [get_pins i_system_wrapper/system_i/axi_spi_bus1/ext_spi_clk] \
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-divide_by 2 [get_pins i_system_wrapper/system_i/axi_spi_bus1/sck_o]
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create_generated_clock -name clk_sck1 \
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-source [get_pins i_system_wrapper/system_i/axi_spi_adl5960_1/ext_spi_clk] \
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-divide_by 2 [get_pins i_system_wrapper/system_i/axi_spi_adl5960_1/sck_o]
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create_generated_clock -name clk_sck2 \
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-source [get_pins i_system_wrapper/system_i/axi_spi_adl5960_2/ext_spi_clk] \
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-divide_by 2 [get_pins i_system_wrapper/system_i/axi_spi_adl5960_2/sck_o]

‎projects/ad9083_vna/zcu102/system_project.tcl‎

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source ../../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project ad9083_vna_zcu102
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adi_project_files ad9083_fmc_zcu102 [list \
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"system_top.v" \
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"system_constr.xdc" \
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"$ad_hdl_dir/library/common/ad_3w_spi.v" \
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
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adi_project_run ad9083_vna_zcu102

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