library/jesd204/ad_ip_jesd204_tpl_adc: Added support for PN7 and PN15 (analogdevicesinc#1019)

Author: PopPaul2021

library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v

@@ -38,7 +38,9 @@ module ad_ip_jesd204_tpl_adc #(
   parameter OCTETS_PER_BEAT = 4,
   parameter EN_FRAME_ALIGN = 1,
   parameter TWOS_COMPLEMENT = 1,
-  parameter EXT_SYNC = 0
+  parameter EXT_SYNC = 0,
+  parameter PN7_ENABLE = 1,
+  parameter PN15_ENABLE = 1
 ) (
 
   // jesd interface
@@ -193,7 +195,9 @@ module ad_ip_jesd204_tpl_adc #(
     .TWOS_COMPLEMENT (TWOS_COMPLEMENT),
     .DATA_PATH_WIDTH (DATA_PATH_WIDTH),
     .DMA_BITS_PER_SAMPLE (DMA_BITS_PER_SAMPLE),
-    .EXT_SYNC (EXT_SYNC)
+    .EXT_SYNC (EXT_SYNC),
+    .PN7_ENABLE (PN7_ENABLE),
+    .PN15_ENABLE(PN15_ENABLE)
   ) i_core (
     .clk (link_clk),
 

library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v

@@ -27,7 +27,9 @@ module ad_ip_jesd204_tpl_adc_channel #(
   parameter CONVERTER_RESOLUTION = 14,
   parameter DATA_PATH_WIDTH = 2,
   parameter TWOS_COMPLEMENT = 1,
-  parameter BITS_PER_SAMPLE = 16
+  parameter BITS_PER_SAMPLE = 16,
+  parameter PN7_ENABLE = 1,
+  parameter PN15_ENABLE = 1
 ) (
   input clk,
 
@@ -50,7 +52,9 @@ module ad_ip_jesd204_tpl_adc_channel #(
   ad_ip_jesd204_tpl_adc_pnmon #(
     .CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
     .DATA_PATH_WIDTH (DATA_PATH_WIDTH),
-    .TWOS_COMPLEMENT (TWOS_COMPLEMENT)
+    .TWOS_COMPLEMENT (TWOS_COMPLEMENT),
+    .PN7_ENABLE (PN7_ENABLE),
+    .PN15_ENABLE(PN15_ENABLE)
   ) i_pnmon (
     .clk (clk),
     .data (raw_data),

library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v

@@ -36,7 +36,9 @@ module ad_ip_jesd204_tpl_adc_core #(
   parameter LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8,
   parameter DMA_DATA_WIDTH = DATA_PATH_WIDTH * DMA_BITS_PER_SAMPLE * NUM_CHANNELS,
   parameter TWOS_COMPLEMENT = 1,
-  parameter EXT_SYNC = 0
+  parameter EXT_SYNC = 0,
+  parameter PN7_ENABLE = 1,
+  parameter PN15_ENABLE = 1
 ) (
   input clk,
 
@@ -119,7 +121,9 @@ module ad_ip_jesd204_tpl_adc_core #(
       .DATA_PATH_WIDTH (DATA_PATH_WIDTH),
       .CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
       .TWOS_COMPLEMENT (TWOS_COMPLEMENT),
-      .BITS_PER_SAMPLE (DMA_BITS_PER_SAMPLE)
+      .BITS_PER_SAMPLE (DMA_BITS_PER_SAMPLE),
+      .PN7_ENABLE (PN7_ENABLE),
+      .PN15_ENABLE(PN15_ENABLE)
     ) i_channel (
       .clk (clk),
 

library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl

@@ -167,7 +167,14 @@ ad_ip_parameter TWOS_COMPLEMENT boolean 1 true [list \
   DISPLAY_NAME "Twos Complement" \
   GROUP $group \
 ]
-
+ad_ip_parameter PN7_ENABLE boolean 1 true [list \
+  DISPLAY_NAME "Enable PN7" \
+  GROUP $group \
+]
+ad_ip_parameter PN15_ENABLE boolean 1 true [list \
+  DISPLAY_NAME "Enable PN15" \
+  GROUP $group \
+]
 
 # axi4 slave
 

library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl

@@ -25,6 +25,7 @@ source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
 
 adi_ip_create ad_ip_jesd204_tpl_adc
+
 adi_ip_files ad_ip_jesd204_tpl_adc [list \
   "$ad_hdl_dir/library/common/ad_rst.v" \
   "$ad_hdl_dir/library/common/ad_perfect_shuffle.v" \
@@ -134,6 +135,8 @@ set i 0
 foreach {k v w} {
   "TWOS_COMPLEMENT" "Use twos complement" "checkBox" \
   "EXT_SYNC" "Enable external sync" "checkBox" \
+  "PN7_ENABLE" "Enable PN7" "checkBox" \
+  "PN15_ENABLE" "Enable PN15" "checkBox" \
   } { \
   set p [ipgui::get_guiparamspec -name $k -component $cc]
   ipgui::move_param -component $cc -order $i $p -parent $datapath_group

library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v

@@ -26,7 +26,9 @@
 module ad_ip_jesd204_tpl_adc_pnmon #(
   parameter CONVERTER_RESOLUTION = 16,
   parameter DATA_PATH_WIDTH = 1,
-  parameter TWOS_COMPLEMENT = 1
+  parameter TWOS_COMPLEMENT = 1,
+  parameter PN7_ENABLE = 1,
+  parameter PN15_ENABLE = 1
 ) (
   input clk,
 
@@ -37,7 +39,7 @@ module ad_ip_jesd204_tpl_adc_pnmon #(
   output pn_oos,
   output pn_err,
 
-  // processor interface PN9 (0x0), PN23 (0x1)
+  // processor interface PN9 (0x0), PN23 (0x1), PN7 (0x4), PN15 (0x5)
   input [3:0] pn_seq_sel
 );
 
@@ -58,6 +60,10 @@ module ad_ip_jesd204_tpl_adc_pnmon #(
   wire [DW+23:0] full_state_pn23;
   wire [DW:0] pn9;
   wire [DW+9:0] full_state_pn9;
+  wire [DW:0] pn7;
+  wire [DW+7:0] full_state_pn7;
+  wire [DW:0] pn15;
+  wire [DW+15:0] full_state_pn15;
 
   // pn sequence select
   generate if (PN_W > DW) begin
@@ -98,12 +104,37 @@ module ad_ip_jesd204_tpl_adc_pnmon #(
 
   always @(posedge clk) begin
     if (pn_seq_sel == 4'd0) begin
-      pn_data_pn <= PN_W > DW ? {pn_data_pn[PN_W-DW-1:0],pn9} : pn9;
-    end else begin
+      pn_data_pn <= PN_W > DW ? {pn_data_pn[PN_W-DW-1:0],pn9}  : pn9;
+    end else if (pn_seq_sel == 4'd1) begin
       pn_data_pn <= PN_W > DW ? {pn_data_pn[PN_W-DW-1:0],pn23} : pn23;
+    end else if (pn_seq_sel == 4'd4) begin
+      pn_data_pn <= PN_W > DW ? {pn_data_pn[PN_W-DW-1:0],pn7}  : pn7;
+    end else if (pn_seq_sel == 4'd5) begin
+      pn_data_pn <= PN_W > DW ? {pn_data_pn[PN_W-DW-1:0],pn15} : pn15;
     end
   end
 
+ // specific PN sequences
+
+  generate
+    if(PN7_ENABLE == 'b1) begin
+     // PN7  x^7 + x^6 + 1
+     assign pn7 = full_state_pn7[7+:DW+1] ^ full_state_pn7[6+:DW+1];
+     assign full_state_pn7 = {pn_data_pn_s[6:0],pn7};
+    end else begin
+     assign pn7 = 'd0;
+     assign full_state_pn7 = 'd0;
+    end
+    if(PN15_ENABLE == 'b1)  begin
+     // PN15 x^15 + x^14 + 1
+     assign pn15 = full_state_pn15[15+:DW+1] ^ full_state_pn15[14+:DW+1];
+     assign full_state_pn15 = {pn_data_pn_s[14:0],pn15};
+    end else begin
+     assign pn15 = 'd0;
+     assign full_state_pn15 = 'd0;
+    end
+  endgenerate
+
   // pn oos & pn err
 
   ad_pnmon #(