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Merged
merged 20 commits into from
Nov 13, 2020
Merged

Rollup of 7 pull requests #78998

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6dfcf9a
Remove branches from sift_down_to_bottom loop
SkiFire13 Nov 7, 2020
25b3f61
Remove useless branches from sift_down_range loop
SkiFire13 Nov 7, 2020
8d15753
Remove useless bound checks from into_sorted_vec
SkiFire13 Nov 7, 2020
387568c
Added SAFETY comment as request
SkiFire13 Nov 9, 2020
de84ad9
Implement destructuring assignment for structs and slices
fanzier Nov 7, 2020
f344134
Add asm register information for SPIR-V
khyperia Nov 11, 2020
0e34b73
Change capitalization of Spirv to SpirV
khyperia Nov 11, 2020
cd314ae
update rustfmt
calebcartwright Nov 12, 2020
c338c81
Update cargo
ehuss Nov 12, 2020
80b2835
extend min_const_generics param ty tests
lcnr Nov 12, 2020
380b222
Consider mutable ident binding patterns to be simple
ebkalderon Sep 15, 2020
2baa0ce
Don't reuse bindings for `ref mut`
jyn514 Nov 8, 2020
38127ca
Handle and test wildcard arguments
jyn514 Nov 10, 2020
4b0b42a
Rollup merge of #76730 - ebkalderon:rustdoc-fix-mut-args-async-fn, r=…
m-ou-se Nov 12, 2020
755dd14
Rollup merge of #78836 - fanzier:struct-and-slice-destructuring, r=pe…
m-ou-se Nov 12, 2020
4088981
Rollup merge of #78857 - SkiFire13:bheap-opt, r=KodrAus
m-ou-se Nov 12, 2020
76fa5f2
Rollup merge of #78950 - khyperia:spirv-asm, r=Amanieu
m-ou-se Nov 12, 2020
a2e8fb5
Rollup merge of #78970 - calebcartwright:update-rustfmt, r=Aaron1011
m-ou-se Nov 12, 2020
ef77a43
Rollup merge of #78972 - ehuss:update-cargo, r=ehuss
m-ou-se Nov 12, 2020
38ca6e3
Rollup merge of #78987 - lcnr:integer-sizes, r=varkor
m-ou-se Nov 12, 2020
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Change capitalization of Spirv to SpirV 
This matches the capitalization of RiscV
  • Loading branch information
@khyperia
khyperia committed Nov 11, 2020
commit 0e34b73996e87bb3f761b52616b3ac0e081fa84d
8 changes: 4 additions & 4 deletions compiler/rustc_codegen_llvm/src/asm.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -260,7 +260,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
InlineAsmArch::Nvptx64 => {}
InlineAsmArch::Hexagon => {}
InlineAsmArch::Mips | InlineAsmArch::Mips64 => {}
InlineAsmArch::Spirv => {}
InlineAsmArch::SpirV => {}
}
}
if !options.contains(InlineAsmOptions::NOMEM) {
Expand Down Expand Up @@ -519,7 +519,7 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'tcx>>)
| InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg) => "x",
InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => "v",
InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => "^Yk",
InlineAsmRegClass::Spirv(SpirvInlineAsmRegClass::reg) => {
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
bug!("LLVM backend does not support SPIR-V")
}
}
Expand Down Expand Up @@ -584,7 +584,7 @@ fn modifier_to_llvm(
_ => unreachable!(),
},
InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => None,
InlineAsmRegClass::Spirv(SpirvInlineAsmRegClass::reg) => {
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
bug!("LLVM backend does not support SPIR-V")
}
}
Expand Down Expand Up @@ -626,7 +626,7 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll
| InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg)
| InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => cx.type_f32(),
InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => cx.type_i16(),
InlineAsmRegClass::Spirv(SpirvInlineAsmRegClass::reg) => {
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
bug!("LLVM backend does not support SPIR-V")
}
}
Expand Down
30 changes: 15 additions & 15 deletions compiler/rustc_target/src/asm/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -164,7 +164,7 @@ pub use hexagon::{HexagonInlineAsmReg, HexagonInlineAsmRegClass};
pub use mips::{MipsInlineAsmReg, MipsInlineAsmRegClass};
pub use nvptx::{NvptxInlineAsmReg, NvptxInlineAsmRegClass};
pub use riscv::{RiscVInlineAsmReg, RiscVInlineAsmRegClass};
pub use spirv::{SpirvInlineAsmReg, SpirvInlineAsmRegClass};
pub use spirv::{SpirVInlineAsmReg, SpirVInlineAsmRegClass};
pub use x86::{X86InlineAsmReg, X86InlineAsmRegClass};

#[derive(Copy, Clone, Encodable, Decodable, Debug, Eq, PartialEq, Hash)]
Expand All @@ -179,7 +179,7 @@ pub enum InlineAsmArch {
Hexagon,
Mips,
Mips64,
Spirv,
SpirV,
}

impl FromStr for InlineAsmArch {
Expand All @@ -197,7 +197,7 @@ impl FromStr for InlineAsmArch {
"hexagon" => Ok(Self::Hexagon),
"mips" => Ok(Self::Mips),
"mips64" => Ok(Self::Mips64),
"spirv" => Ok(Self::Spirv),
"spirv" => Ok(Self::SpirV),
_ => Err(()),
}
}
Expand All @@ -212,7 +212,7 @@ pub enum InlineAsmReg {
Nvptx(NvptxInlineAsmReg),
Hexagon(HexagonInlineAsmReg),
Mips(MipsInlineAsmReg),
Spirv(SpirvInlineAsmReg),
SpirV(SpirVInlineAsmReg),
}

impl InlineAsmReg {
Expand Down Expand Up @@ -269,8 +269,8 @@ impl InlineAsmReg {
InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
Self::Mips(MipsInlineAsmReg::parse(arch, has_feature, target, &name)?)
}
InlineAsmArch::Spirv => {
Self::Spirv(SpirvInlineAsmReg::parse(arch, has_feature, target, &name)?)
InlineAsmArch::SpirV => {
Self::SpirV(SpirVInlineAsmReg::parse(arch, has_feature, target, &name)?)
}
})
}
Expand Down Expand Up @@ -314,7 +314,7 @@ pub enum InlineAsmRegClass {
Nvptx(NvptxInlineAsmRegClass),
Hexagon(HexagonInlineAsmRegClass),
Mips(MipsInlineAsmRegClass),
Spirv(SpirvInlineAsmRegClass),
SpirV(SpirVInlineAsmRegClass),
}

impl InlineAsmRegClass {
Expand All @@ -327,7 +327,7 @@ impl InlineAsmRegClass {
Self::Nvptx(r) => r.name(),
Self::Hexagon(r) => r.name(),
Self::Mips(r) => r.name(),
Self::Spirv(r) => r.name(),
Self::SpirV(r) => r.name(),
}
}

Expand All @@ -343,7 +343,7 @@ impl InlineAsmRegClass {
Self::Nvptx(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Nvptx),
Self::Hexagon(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Hexagon),
Self::Mips(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Mips),
Self::Spirv(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Spirv),
Self::SpirV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::SpirV),
}
}

Expand All @@ -366,7 +366,7 @@ impl InlineAsmRegClass {
Self::Nvptx(r) => r.suggest_modifier(arch, ty),
Self::Hexagon(r) => r.suggest_modifier(arch, ty),
Self::Mips(r) => r.suggest_modifier(arch, ty),
Self::Spirv(r) => r.suggest_modifier(arch, ty),
Self::SpirV(r) => r.suggest_modifier(arch, ty),
}
}

Expand All @@ -385,7 +385,7 @@ impl InlineAsmRegClass {
Self::Nvptx(r) => r.default_modifier(arch),
Self::Hexagon(r) => r.default_modifier(arch),
Self::Mips(r) => r.default_modifier(arch),
Self::Spirv(r) => r.default_modifier(arch),
Self::SpirV(r) => r.default_modifier(arch),
}
}

Expand All @@ -403,7 +403,7 @@ impl InlineAsmRegClass {
Self::Nvptx(r) => r.supported_types(arch),
Self::Hexagon(r) => r.supported_types(arch),
Self::Mips(r) => r.supported_types(arch),
Self::Spirv(r) => r.supported_types(arch),
Self::SpirV(r) => r.supported_types(arch),
}
}

Expand All @@ -428,7 +428,7 @@ impl InlineAsmRegClass {
InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
Self::Mips(MipsInlineAsmRegClass::parse(arch, name)?)
}
InlineAsmArch::Spirv => Self::Spirv(SpirvInlineAsmRegClass::parse(arch, name)?),
InlineAsmArch::SpirV => Self::SpirV(SpirVInlineAsmRegClass::parse(arch, name)?),
})
})
}
Expand All @@ -444,7 +444,7 @@ impl InlineAsmRegClass {
Self::Nvptx(r) => r.valid_modifiers(arch),
Self::Hexagon(r) => r.valid_modifiers(arch),
Self::Mips(r) => r.valid_modifiers(arch),
Self::Spirv(r) => r.valid_modifiers(arch),
Self::SpirV(r) => r.valid_modifiers(arch),
}
}
}
Expand Down Expand Up @@ -587,7 +587,7 @@ pub fn allocatable_registers(
mips::fill_reg_map(arch, has_feature, target, &mut map);
map
}
InlineAsmArch::Spirv => {
InlineAsmArch::SpirV => {
let mut map = spirv::regclass_map();
spirv::fill_reg_map(arch, has_feature, target, &mut map);
map
Expand Down
6 changes: 3 additions & 3 deletions compiler/rustc_target/src/asm/spirv.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -2,12 +2,12 @@ use super::{InlineAsmArch, InlineAsmType};
use rustc_macros::HashStable_Generic;

def_reg_class! {
Spirv SpirvInlineAsmRegClass {
SpirV SpirVInlineAsmRegClass {
reg,
}
}

impl SpirvInlineAsmRegClass {
impl SpirVInlineAsmRegClass {
pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
&[]
}
Expand Down Expand Up @@ -42,5 +42,5 @@ impl SpirvInlineAsmRegClass {

def_regs! {
// SPIR-V is SSA-based, it does not have registers.
Spirv SpirvInlineAsmReg SpirvInlineAsmRegClass {}
SpirV SpirVInlineAsmReg SpirVInlineAsmRegClass {}
}