SI-8570 set the checkinit bit for unit-typed fields of traits

Fix only, refactoring in subsequent commit.

Author: lrytz

src/compiler/scala/tools/nsc/transform/Mixin.scala

@@ -1042,15 +1042,18 @@ abstract class Mixin extends InfoTransform with ast.TreeDSL {
             // add accessor definitions
             addDefDef(sym, {
               if (sym.isSetter) {
+                val getter = sym.getter(clazz)
+                def setInitFlag = mkSetFlag(clazz, fieldOffset(getter), getter, bitmapKind(getter))
                 if (isOverriddenSetter(sym)) UNIT
                 else accessedRef match {
-                  case ref @ Literal(_) => ref
+                  case ref @ Literal(_) =>
+                    if (!needsInitFlag(getter)) ref
+                    else Block(setInitFlag, ref)
                   case ref =>
                     val init   = Assign(ref, Ident(sym.firstParam))
-                    val getter = sym.getter(clazz)
 
                     if (!needsInitFlag(getter)) init
-                    else Block(init, mkSetFlag(clazz, fieldOffset(getter), getter, bitmapKind(getter)), UNIT)
+                    else Block(init, setInitFlag, UNIT)
                 }
               }
               else if (needsInitFlag(sym))

test/files/run/t8570.flags

@@ -0,0 +1 @@
+-Xcheckinit

test/files/run/t8570.scala

@@ -0,0 +1,10 @@
+trait Trait40_1 {
+  val value37_2 = ()
+  def run = { value37_2 }
+}
+
+object Test {
+  def main(args: Array[String]) {
+    (new Trait40_1 {}).run
+  }
+}

test/files/run/t8570a.check

@@ -0,0 +1 @@
+()

test/files/run/t8570a.flags

@@ -0,0 +1 @@
+-Xcheckinit

test/files/run/t8570a.scala

@@ -0,0 +1,14 @@
+trait Trait40_1 {
+  val value37_2 = ()
+  def run = { value37_2 }
+}
+
+trait T1 extends Trait40_1 {
+  override val value37_2 = ()
+}
+
+object Test {
+  def main(args: Array[String]) {
+    println((new T1 {}).run)
+  }
+}