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emit_tests.rs
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7844 lines (7454 loc) · 188 KB
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use crate::ir::types::*;
use crate::ir::TrapCode;
use crate::isa::aarch64::inst::*;
use crate::isa::CallConv;
use crate::settings;
use alloc::boxed::Box;
use alloc::vec::Vec;
#[cfg(test)]
fn simm9_zero() -> SImm9 {
SImm9::maybe_from_i64(0).unwrap()
}
#[cfg(test)]
fn simm7_scaled_zero(scale_ty: Type) -> SImm7Scaled {
SImm7Scaled::maybe_from_i64(0, scale_ty).unwrap()
}
#[test]
fn test_aarch64_binemit() {
let mut insns = Vec::<(Inst, &str, &str)>::new();
// N.B.: the architecture is little-endian, so when transcribing the 32-bit
// hex instructions from e.g. objdump disassembly, one must swap the bytes
// seen below. (E.g., a `ret` is normally written as the u32 `D65F03C0`,
// but we write it here as C0035FD6.)
// Useful helper script to produce the encodings from the text:
//
// #!/bin/sh
// tmp=`mktemp /tmp/XXXXXXXX.o`
// aarch64-linux-gnu-as /dev/stdin -o $tmp
// aarch64-linux-gnu-objdump -d $tmp
// rm -f $tmp
//
// Then:
//
// $ echo "mov x1, x2" | aarch64inst.sh
insns.push((Inst::Ret { rets: vec![] }, "C0035FD6", "ret"));
insns.push((
Inst::AuthenticatedRet {
key: APIKey::A,
is_hint: true,
rets: vec![],
},
"BF2303D5C0035FD6",
"autiasp ; ret",
));
insns.push((
Inst::AuthenticatedRet {
key: APIKey::B,
is_hint: false,
rets: vec![],
},
"FF0F5FD6",
"retab",
));
insns.push((Inst::Pacisp { key: APIKey::B }, "7F2303D5", "pacibsp"));
insns.push((Inst::Xpaclri, "FF2003D5", "xpaclri"));
insns.push((
Inst::Bti {
targets: BranchTargetType::J,
},
"9F2403D5",
"bti j",
));
insns.push((Inst::Nop0, "", "nop-zero-len"));
insns.push((Inst::Nop4, "1F2003D5", "nop"));
insns.push((Inst::Csdb, "9F2203D5", "csdb"));
insns.push((
Inst::Udf {
trap_code: TrapCode::Interrupt,
},
"1FC10000",
"udf #0xc11f",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Add,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
},
"4100030B",
"add w1, w2, w3",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Add,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A400068B",
"add x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Adc,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
},
"4100031A",
"adc w1, w2, w3",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Adc,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A400069A",
"adc x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::AdcS,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
},
"4100033A",
"adcs w1, w2, w3",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::AdcS,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A40006BA",
"adcs x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Sub,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
},
"4100034B",
"sub w1, w2, w3",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Sub,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A40006CB",
"sub x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Sbc,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
},
"4100035A",
"sbc w1, w2, w3",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Sbc,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A40006DA",
"sbc x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::SbcS,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
},
"4100037A",
"sbcs w1, w2, w3",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::SbcS,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A40006FA",
"sbcs x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Orr,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
},
"4100032A",
"orr w1, w2, w3",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Orr,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A40006AA",
"orr x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::And,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
},
"4100030A",
"and w1, w2, w3",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::And,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A400068A",
"and x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::AndS,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
},
"4100036A",
"ands w1, w2, w3",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::AndS,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A40006EA",
"ands x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::SubS,
size: OperandSize::Size32,
rd: writable_zero_reg(),
rn: xreg(2),
rm: xreg(3),
},
"5F00036B",
// TODO: Display as cmp
"subs wzr, w2, w3",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::SubS,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
},
"4100036B",
"subs w1, w2, w3",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::SubS,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A40006EB",
"subs x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::AddS,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
},
"4100032B",
"adds w1, w2, w3",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::AddS,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A40006AB",
"adds x4, x5, x6",
));
insns.push((
Inst::AluRRImm12 {
alu_op: ALUOp::AddS,
size: OperandSize::Size64,
rd: writable_zero_reg(),
rn: xreg(5),
imm12: Imm12::maybe_from_u64(1).unwrap(),
},
"BF0400B1",
// TODO: Display as cmn.
"adds xzr, x5, #1",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::SDiv,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A40CC69A",
"sdiv x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::UDiv,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A408C69A",
"udiv x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Eor,
size: OperandSize::Size32,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A400064A",
"eor w4, w5, w6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Eor,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A40006CA",
"eor x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::AndNot,
size: OperandSize::Size32,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A400260A",
"bic w4, w5, w6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::AndNot,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A400268A",
"bic x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::OrrNot,
size: OperandSize::Size32,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A400262A",
"orn w4, w5, w6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::OrrNot,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A40026AA",
"orn x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::EorNot,
size: OperandSize::Size32,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A400264A",
"eon w4, w5, w6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::EorNot,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A40026CA",
"eon x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::RotR,
size: OperandSize::Size32,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A42CC61A",
"ror w4, w5, w6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::RotR,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A42CC69A",
"ror x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Lsr,
size: OperandSize::Size32,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A424C61A",
"lsr w4, w5, w6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Lsr,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A424C69A",
"lsr x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Asr,
size: OperandSize::Size32,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A428C61A",
"asr w4, w5, w6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Asr,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A428C69A",
"asr x4, x5, x6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Lsl,
size: OperandSize::Size32,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A420C61A",
"lsl w4, w5, w6",
));
insns.push((
Inst::AluRRR {
alu_op: ALUOp::Lsl,
size: OperandSize::Size64,
rd: writable_xreg(4),
rn: xreg(5),
rm: xreg(6),
},
"A420C69A",
"lsl x4, x5, x6",
));
insns.push((
Inst::AluRRImm12 {
alu_op: ALUOp::Add,
size: OperandSize::Size32,
rd: writable_xreg(7),
rn: xreg(8),
imm12: Imm12 {
bits: 0x123,
shift12: false,
},
},
"078D0411",
"add w7, w8, #291",
));
insns.push((
Inst::AluRRImm12 {
alu_op: ALUOp::Add,
size: OperandSize::Size32,
rd: writable_xreg(7),
rn: xreg(8),
imm12: Imm12 {
bits: 0x123,
shift12: true,
},
},
"078D4411",
"add w7, w8, #1191936",
));
insns.push((
Inst::AluRRImm12 {
alu_op: ALUOp::Add,
size: OperandSize::Size64,
rd: writable_xreg(7),
rn: xreg(8),
imm12: Imm12 {
bits: 0x123,
shift12: false,
},
},
"078D0491",
"add x7, x8, #291",
));
insns.push((
Inst::AluRRImm12 {
alu_op: ALUOp::Sub,
size: OperandSize::Size32,
rd: writable_xreg(7),
rn: xreg(8),
imm12: Imm12 {
bits: 0x123,
shift12: false,
},
},
"078D0451",
"sub w7, w8, #291",
));
insns.push((
Inst::AluRRImm12 {
alu_op: ALUOp::Sub,
size: OperandSize::Size64,
rd: writable_xreg(7),
rn: xreg(8),
imm12: Imm12 {
bits: 0x123,
shift12: false,
},
},
"078D04D1",
"sub x7, x8, #291",
));
insns.push((
Inst::AluRRImm12 {
alu_op: ALUOp::SubS,
size: OperandSize::Size32,
rd: writable_xreg(7),
rn: xreg(8),
imm12: Imm12 {
bits: 0x123,
shift12: false,
},
},
"078D0471",
"subs w7, w8, #291",
));
insns.push((
Inst::AluRRImm12 {
alu_op: ALUOp::SubS,
size: OperandSize::Size64,
rd: writable_xreg(7),
rn: xreg(8),
imm12: Imm12 {
bits: 0x123,
shift12: false,
},
},
"078D04F1",
"subs x7, x8, #291",
));
insns.push((
Inst::AluRRRExtend {
alu_op: ALUOp::Add,
size: OperandSize::Size32,
rd: writable_xreg(7),
rn: xreg(8),
rm: xreg(9),
extendop: ExtendOp::SXTB,
},
"0781290B",
"add w7, w8, w9, SXTB",
));
insns.push((
Inst::AluRRRExtend {
alu_op: ALUOp::Add,
size: OperandSize::Size64,
rd: writable_xreg(15),
rn: xreg(16),
rm: xreg(17),
extendop: ExtendOp::UXTB,
},
"0F02318B",
"add x15, x16, x17, UXTB",
));
insns.push((
Inst::AluRRRExtend {
alu_op: ALUOp::Sub,
size: OperandSize::Size32,
rd: writable_xreg(1),
rn: xreg(2),
rm: xreg(3),
extendop: ExtendOp::SXTH,
},
"41A0234B",
"sub w1, w2, w3, SXTH",
));
insns.push((
Inst::AluRRRExtend {
alu_op: ALUOp::Sub,
size: OperandSize::Size64,
rd: writable_xreg(20),
rn: xreg(21),
rm: xreg(22),
extendop: ExtendOp::UXTW,
},
"B44236CB",
"sub x20, x21, x22, UXTW",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::Add,
size: OperandSize::Size32,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
shiftop: ShiftOpAndAmt::new(
ShiftOp::LSL,
ShiftOpShiftImm::maybe_from_shift(20).unwrap(),
),
},
"6A510C0B",
"add w10, w11, w12, LSL 20",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::Add,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
shiftop: ShiftOpAndAmt::new(
ShiftOp::ASR,
ShiftOpShiftImm::maybe_from_shift(42).unwrap(),
),
},
"6AA98C8B",
"add x10, x11, x12, ASR 42",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::Sub,
size: OperandSize::Size32,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
shiftop: ShiftOpAndAmt::new(
ShiftOp::LSL,
ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
),
},
"6A5D0C4B",
"sub w10, w11, w12, LSL 23",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::Sub,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
shiftop: ShiftOpAndAmt::new(
ShiftOp::LSL,
ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
),
},
"6A5D0CCB",
"sub x10, x11, x12, LSL 23",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::Orr,
size: OperandSize::Size32,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
shiftop: ShiftOpAndAmt::new(
ShiftOp::LSL,
ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
),
},
"6A5D0C2A",
"orr w10, w11, w12, LSL 23",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::Orr,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
shiftop: ShiftOpAndAmt::new(
ShiftOp::LSL,
ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
),
},
"6A5D0CAA",
"orr x10, x11, x12, LSL 23",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::And,
size: OperandSize::Size32,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
shiftop: ShiftOpAndAmt::new(
ShiftOp::LSL,
ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
),
},
"6A5D0C0A",
"and w10, w11, w12, LSL 23",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::And,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
shiftop: ShiftOpAndAmt::new(
ShiftOp::LSL,
ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
),
},
"6A5D0C8A",
"and x10, x11, x12, LSL 23",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::AndS,
size: OperandSize::Size32,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
shiftop: ShiftOpAndAmt::new(
ShiftOp::LSL,
ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
),
},
"6A5D0C6A",
"ands w10, w11, w12, LSL 23",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::AndS,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
shiftop: ShiftOpAndAmt::new(
ShiftOp::LSL,
ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
),
},
"6A5D0CEA",
"ands x10, x11, x12, LSL 23",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::Eor,
size: OperandSize::Size32,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
shiftop: ShiftOpAndAmt::new(
ShiftOp::LSL,
ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
),
},
"6A5D0C4A",
"eor w10, w11, w12, LSL 23",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::Eor,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
shiftop: ShiftOpAndAmt::new(
ShiftOp::LSL,
ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
),
},
"6A5D0CCA",
"eor x10, x11, x12, LSL 23",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::OrrNot,
size: OperandSize::Size32,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
shiftop: ShiftOpAndAmt::new(
ShiftOp::LSL,
ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
),
},
"6A5D2C2A",
"orn w10, w11, w12, LSL 23",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::OrrNot,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
shiftop: ShiftOpAndAmt::new(
ShiftOp::LSL,
ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
),
},
"6A5D2CAA",
"orn x10, x11, x12, LSL 23",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::AndNot,
size: OperandSize::Size32,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
shiftop: ShiftOpAndAmt::new(
ShiftOp::LSL,
ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
),
},
"6A5D2C0A",
"bic w10, w11, w12, LSL 23",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::AndNot,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
shiftop: ShiftOpAndAmt::new(
ShiftOp::LSL,
ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
),
},
"6A5D2C8A",
"bic x10, x11, x12, LSL 23",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::EorNot,
size: OperandSize::Size32,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
shiftop: ShiftOpAndAmt::new(
ShiftOp::LSL,
ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
),
},
"6A5D2C4A",
"eon w10, w11, w12, LSL 23",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::EorNot,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
shiftop: ShiftOpAndAmt::new(
ShiftOp::LSL,
ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
),
},
"6A5D2CCA",
"eon x10, x11, x12, LSL 23",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::AddS,
size: OperandSize::Size32,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
shiftop: ShiftOpAndAmt::new(
ShiftOp::LSL,
ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
),
},
"6A5D0C2B",
"adds w10, w11, w12, LSL 23",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::AddS,
size: OperandSize::Size64,
rd: writable_xreg(10),
rn: xreg(11),
rm: xreg(12),
shiftop: ShiftOpAndAmt::new(
ShiftOp::LSL,
ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
),
},
"6A5D0CAB",
"adds x10, x11, x12, LSL 23",
));
insns.push((
Inst::AluRRRShift {
alu_op: ALUOp::SubS,
size: OperandSize::Size32,