From 0e2a66be4dd0b74cf36e91e52749937cc627b77e Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 28 Jul 2025 14:16:37 +0200 Subject: [PATCH 01/18] chore: update core version to 2.12.0-dev (0x020C00F0) Signed-off-by: Frederic Pillon --- libraries/SrcWrapper/inc/stm32_def.h | 4 ++-- platform.txt | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/libraries/SrcWrapper/inc/stm32_def.h b/libraries/SrcWrapper/inc/stm32_def.h index fabc06919b..ad34a8c847 100644 --- a/libraries/SrcWrapper/inc/stm32_def.h +++ b/libraries/SrcWrapper/inc/stm32_def.h @@ -6,7 +6,7 @@ * @brief STM32 core version number */ #define STM32_CORE_VERSION_MAJOR (0x02U) /*!< [31:24] major version */ -#define STM32_CORE_VERSION_MINOR (0x0BU) /*!< [23:16] minor version */ +#define STM32_CORE_VERSION_MINOR (0x0CU) /*!< [23:16] minor version */ #define STM32_CORE_VERSION_PATCH (0x00U) /*!< [15:8] patch version */ /* * Extra label for development: @@ -14,7 +14,7 @@ * [1-9]: release candidate * F[0-9]: development */ -#define STM32_CORE_VERSION_EXTRA (0x00U) /*!< [7:0] extra version */ +#define STM32_CORE_VERSION_EXTRA (0xF0U) /*!< [7:0] extra version */ #define STM32_CORE_VERSION ((STM32_CORE_VERSION_MAJOR << 24U)\ |(STM32_CORE_VERSION_MINOR << 16U)\ |(STM32_CORE_VERSION_PATCH << 8U )\ diff --git a/platform.txt b/platform.txt index 58d8ca2d6f..0ec0678391 100644 --- a/platform.txt +++ b/platform.txt @@ -5,7 +5,7 @@ # https://arduino.github.io/arduino-cli/latest/platform-specification/ name=STM32 boards groups (Board to be selected from Tools submenu 'Board part number') -version=2.11.0 +version=2.12.0-dev # Define variables used multiple times in platform file From 212705127939e99f1b8f6c16271e937a52cd2fa9 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 20 Aug 2025 14:13:09 +0200 Subject: [PATCH 02/18] Revert "chore(f7): use HSE bypass for Nucleo-F767ZI" This reverts commit 1ef1f862c81257c73d046a957194e3c541653988. Fixes #2795. Signed-off-by: Frederic Pillon --- .../variant_NUCLEO_F767ZI.cpp | 23 ++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/variant_NUCLEO_F767ZI.cpp b/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/variant_NUCLEO_F767ZI.cpp index b7edea0f36..c0f7688f94 100644 --- a/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/variant_NUCLEO_F767ZI.cpp +++ b/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/variant_NUCLEO_F767ZI.cpp @@ -171,6 +171,23 @@ extern "C" { /** * @brief System Clock Configuration + * The system Clock is configured as follow : + * System Clock source = PLL (HSI) + * SYSCLK(Hz) = 216000000 + * HCLK(Hz) = 216000000 + * AHB Prescaler = 1 + * APB1 Prescaler = 4 + * APB2 Prescaler = 2 + * HSE Frequency(Hz) = 16000000 + * PLL_M = 8 + * PLL_N = 216 + * PLL_P = 2 + * PLL_Q = 9 + * PLLSAI_N = 192 + * PLLSAI_P = 2 + * VDD(V) = 3.3 + * Main regulator output voltage = Scale1 mode + * Flash Latency(WS) = 7 * @param None * @retval None */ @@ -186,12 +203,12 @@ WEAK void SystemClock_Config(void) __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); /* Initializes the CPU, AHB and APB busses clocks */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSICalibrationValue = 16; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLM = 4; + RCC_OscInitStruct.PLL.PLLM = 8; RCC_OscInitStruct.PLL.PLLN = 216; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = 9; From 06e2a4b640776ef37d3f36afe38660987a44570a Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 21 Aug 2025 11:27:35 +0200 Subject: [PATCH 03/18] chore(variants): update variants against CubeMX DB release 6.0.140 Signed-off-by: Frederic Pillon --- README.md | 2 +- boards.txt | 61 ++- .../C011D6Y_C011F(4-6)(P-U)/PeripheralPins.c | 2 +- .../STM32C0xx/C011J(4-6)M/PeripheralPins.c | 2 +- .../C031C(4-6)(T-U)/PeripheralPins.c | 2 +- .../STM32C0xx/C031F(4-6)P/PeripheralPins.c | 2 +- .../STM32C0xx/C031G(4-6)U/PeripheralPins.c | 2 +- .../C031K(4-6)(T-U)/PeripheralPins.c | 2 +- .../C051C(6-8)(T-U)/PeripheralPins.c | 2 +- .../C051D8Y_C051F(6-8)P/PeripheralPins.c | 2 +- .../STM32C0xx/C051G(6-8)U/PeripheralPins.c | 2 +- .../C051K6(T-U)_C051K8T/PeripheralPins.c | 2 +- .../C071C(8-B)(T-U)/PeripheralPins.c | 2 +- .../C071C(8-B)(T-U)xN/PeripheralPins.c | 2 +- .../STM32C0xx/C071F(8-B)PxN/PeripheralPins.c | 2 +- .../C071F8P_C071FB(P-Y)/PeripheralPins.c | 2 +- .../STM32C0xx/C071G(8-B)U/PeripheralPins.c | 2 +- .../STM32C0xx/C071G(8-B)UxN/PeripheralPins.c | 2 +- .../C071K(8-B)(T-U)/PeripheralPins.c | 2 +- .../C071K(8-B)(T-U)xN/PeripheralPins.c | 2 +- .../STM32C0xx/C071R(8-B)T/PeripheralPins.c | 2 +- .../C071R8TxN_C071RB(I-T)xN/PeripheralPins.c | 2 +- .../C091C(B-C)(T-U)/PeripheralPins.c | 2 +- .../C091ECY_C091F(B-C)P/PeripheralPins.c | 2 +- .../STM32C0xx/C091G(B-C)U/PeripheralPins.c | 2 +- .../C091K(B-C)(T-U)/PeripheralPins.c | 2 +- .../C091RBT_C091RC(I-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 6 +- .../PinNamesVar.h | 0 .../boards_entry.txt | 15 +- .../generic_clock.c | 4 +- .../STM32C0xx/C092C(B-C)(T-U)/ldscript.ld | 187 +++++++++ .../variant_generic.cpp | 4 +- .../variant_generic.h | 0 .../CMakeLists.txt | 32 -- .../C092CBU_C092CC(T-U)/CMakeLists.txt | 31 -- .../C092ECY_C092F(B-C)P/PeripheralPins.c | 2 +- .../STM32C0xx/C092G(B-C)U/PeripheralPins.c | 2 +- .../C092K(B-C)(T-U)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 6 +- .../PinNamesVar.h | 0 .../boards_entry.txt | 15 +- .../C092RBT_C092RC(I-T)/generic_clock.c | 54 +++ .../ldscript.ld | 0 .../variant_NUCLEO_C092RC.cpp | 0 .../variant_NUCLEO_C092RC.h | 0 .../variant_generic.cpp | 4 +- .../variant_generic.h | 0 variants/STM32F0xx/F030C6T/PeripheralPins.c | 2 +- variants/STM32F0xx/F030C8T/PeripheralPins.c | 2 +- variants/STM32F0xx/F030CCT/PeripheralPins.c | 2 +- variants/STM32F0xx/F030F4P/PeripheralPins.c | 2 +- variants/STM32F0xx/F030K6T/PeripheralPins.c | 2 +- variants/STM32F0xx/F030R8T/PeripheralPins.c | 2 +- variants/STM32F0xx/F030RCT/PeripheralPins.c | 2 +- .../STM32F0xx/F031C(4-6)T/PeripheralPins.c | 2 +- .../F031E6Y_F038E6Y/PeripheralPins.c | 2 +- .../STM32F0xx/F031F(4-6)P/PeripheralPins.c | 2 +- .../STM32F0xx/F031G(4-6)U/PeripheralPins.c | 2 +- .../STM32F0xx/F031K(4-6)U/PeripheralPins.c | 2 +- variants/STM32F0xx/F031K6T/PeripheralPins.c | 2 +- variants/STM32F0xx/F038C6T/PeripheralPins.c | 2 +- variants/STM32F0xx/F038F6P/PeripheralPins.c | 2 +- variants/STM32F0xx/F038G6U/PeripheralPins.c | 2 +- variants/STM32F0xx/F038K6U/PeripheralPins.c | 2 +- .../F042C(4-6)(T-U)/PeripheralPins.c | 2 +- .../STM32F0xx/F042F(4-6)P/PeripheralPins.c | 2 +- .../STM32F0xx/F042G(4-6)U/PeripheralPins.c | 2 +- .../STM32F0xx/F042K(4-6)T/PeripheralPins.c | 2 +- .../STM32F0xx/F042K(4-6)U/PeripheralPins.c | 2 +- variants/STM32F0xx/F042T6Y/PeripheralPins.c | 2 +- variants/STM32F0xx/F048C6U/PeripheralPins.c | 2 +- variants/STM32F0xx/F048G6U/PeripheralPins.c | 2 +- variants/STM32F0xx/F048T6Y/PeripheralPins.c | 2 +- .../STM32F0xx/F051C4(T-U)/PeripheralPins.c | 2 +- .../STM32F0xx/F051C6(T-U)/PeripheralPins.c | 2 +- .../STM32F0xx/F051C8(T-U)/PeripheralPins.c | 2 +- .../STM32F0xx/F051K(6-8)T/PeripheralPins.c | 2 +- .../STM32F0xx/F051K(6-8)U/PeripheralPins.c | 2 +- variants/STM32F0xx/F051K4T/PeripheralPins.c | 2 +- variants/STM32F0xx/F051K4U/PeripheralPins.c | 2 +- variants/STM32F0xx/F051R4T/PeripheralPins.c | 2 +- variants/STM32F0xx/F051R6T/PeripheralPins.c | 2 +- .../STM32F0xx/F051R8(H-T)/PeripheralPins.c | 2 +- variants/STM32F0xx/F051T8Y/PeripheralPins.c | 2 +- variants/STM32F0xx/F058C8U/PeripheralPins.c | 2 +- .../STM32F0xx/F058R8(H-T)/PeripheralPins.c | 2 +- variants/STM32F0xx/F058T8Y/PeripheralPins.c | 2 +- variants/STM32F0xx/F070C6T/PeripheralPins.c | 2 +- variants/STM32F0xx/F070CBT/PeripheralPins.c | 2 +- variants/STM32F0xx/F070F6P/PeripheralPins.c | 2 +- variants/STM32F0xx/F070RBT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32F0xx/F071RBT/PeripheralPins.c | 2 +- .../F071V(8-B)(H-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F072R8T_F072RB(H-I-T)/PeripheralPins.c | 2 +- .../F072V(8-B)(H-T)/PeripheralPins.c | 2 +- .../STM32F0xx/F078CB(T-U-Y)/PeripheralPins.c | 2 +- .../STM32F0xx/F078RB(H-T)/PeripheralPins.c | 2 +- .../STM32F0xx/F078VB(H-T)/PeripheralPins.c | 2 +- .../F091C(B-C)(T-U)/PeripheralPins.c | 2 +- .../F091RBT_F091RC(H-T-Y)/PeripheralPins.c | 2 +- .../F091VBT_F091VC(H-T)/PeripheralPins.c | 2 +- .../STM32F0xx/F098CC(T-U)/PeripheralPins.c | 2 +- .../STM32F0xx/F098RC(H-T-Y)/PeripheralPins.c | 2 +- .../STM32F0xx/F098VC(H-T)/PeripheralPins.c | 2 +- .../STM32F1xx/F100C(4-6)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100C(8-B)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100R(4-6)H/PeripheralPins.c | 2 +- .../STM32F1xx/F100R(4-6)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100R(8-B)H/PeripheralPins.c | 2 +- .../STM32F1xx/F100R(8-B)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100R(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100V(8-B)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100V(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F100Z(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101C(4-6)T/PeripheralPins.c | 2 +- .../F101C(8-B)(T-U)/PeripheralPins.c | 2 +- .../STM32F1xx/F101R(4-6)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101R(8-B)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101R(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101R(F-G)T/PeripheralPins.c | 2 +- variants/STM32F1xx/F101RBH/PeripheralPins.c | 2 +- .../STM32F1xx/F101T(4-6)U/PeripheralPins.c | 2 +- .../STM32F1xx/F101T(8-B)U/PeripheralPins.c | 2 +- .../STM32F1xx/F101V(8-B)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101V(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101V(F-G)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101Z(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F101Z(F-G)T/PeripheralPins.c | 2 +- .../STM32F1xx/F102C(4-6)T/PeripheralPins.c | 2 +- .../STM32F1xx/F102C(8-B)T/PeripheralPins.c | 2 +- .../STM32F1xx/F102R(4-6)T/PeripheralPins.c | 2 +- .../STM32F1xx/F102R(8-B)T/PeripheralPins.c | 2 +- .../F103C4T_F103C6(T-U)/PeripheralPins.c | 2 +- .../F103C8T_F103CB(T-U)/PeripheralPins.c | 2 +- .../STM32F1xx/F103R(4-6)H/PeripheralPins.c | 2 +- .../STM32F1xx/F103R(4-6)T/PeripheralPins.c | 2 +- .../STM32F1xx/F103R(8-B)H/PeripheralPins.c | 2 +- .../STM32F1xx/F103R(8-B)T/PeripheralPins.c | 2 +- .../STM32F1xx/F103R(C-D-E)T/PeripheralPins.c | 2 +- .../STM32F1xx/F103R(C-D-E)Y/PeripheralPins.c | 2 +- .../STM32F1xx/F103R(F-G)T/PeripheralPins.c | 2 +- .../STM32F1xx/F103T(4-6)U/PeripheralPins.c | 2 +- .../STM32F1xx/F103T(8-B)U/PeripheralPins.c | 2 +- .../F103V(C-D-E)(H-T)/PeripheralPins.c | 2 +- .../STM32F1xx/F103V(F-G)T/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F103Z(C-D-E)(H-T)/PeripheralPins.c | 2 +- .../F103Z(F-G)(H-T)/PeripheralPins.c | 2 +- .../STM32F1xx/F105R(8-B-C)T/PeripheralPins.c | 2 +- .../F105V(8-B)(H-T)_F105VCT/PeripheralPins.c | 2 +- .../STM32F1xx/F107R(B-C)T/PeripheralPins.c | 2 +- .../F107VBT_F107VC(H-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F301C6T_F301C8(T-Y)/PeripheralPins.c | 2 +- .../STM32F3xx/F301K(6-8)T/PeripheralPins.c | 2 +- .../STM32F3xx/F301K(6-8)U/PeripheralPins.c | 2 +- .../STM32F3xx/F301R(6-8)T/PeripheralPins.c | 2 +- .../STM32F3xx/F302C(B-C)T/PeripheralPins.c | 2 +- .../F302C6T_F302C8(T-Y)/PeripheralPins.c | 2 +- .../STM32F3xx/F302K(6-8)U/PeripheralPins.c | 2 +- .../STM32F3xx/F302R(6-8)T/PeripheralPins.c | 2 +- .../STM32F3xx/F302R(B-C)T/PeripheralPins.c | 2 +- .../STM32F3xx/F302R(D-E)T/PeripheralPins.c | 2 +- .../STM32F3xx/F302V(B-C)T/PeripheralPins.c | 2 +- .../F302V(D-E)(H-T)/PeripheralPins.c | 2 +- variants/STM32F3xx/F302VCY/PeripheralPins.c | 2 +- .../STM32F3xx/F302Z(D-E)T/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32F3xx/F303C(B-C)T/PeripheralPins.c | 2 +- .../F303C8Y_F334C8Y/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F303R(6-8)T_F334R(6-8)T/PeripheralPins.c | 2 +- .../STM32F3xx/F303R(B-C)T/PeripheralPins.c | 2 +- .../STM32F3xx/F303R(D-E)T/PeripheralPins.c | 2 +- .../STM32F3xx/F303V(B-C)T/PeripheralPins.c | 2 +- .../F303V(D-E)(H-T)/PeripheralPins.c | 2 +- variants/STM32F3xx/F303VCY/PeripheralPins.c | 2 +- variants/STM32F3xx/F303VEY/PeripheralPins.c | 2 +- .../STM32F3xx/F303Z(D-E)T/PeripheralPins.c | 2 +- .../STM32F3xx/F318C8(T-Y)/PeripheralPins.c | 2 +- variants/STM32F3xx/F318K8U/PeripheralPins.c | 2 +- variants/STM32F3xx/F328C8T/PeripheralPins.c | 2 +- variants/STM32F3xx/F358CCT/PeripheralPins.c | 2 +- variants/STM32F3xx/F358RCT/PeripheralPins.c | 2 +- variants/STM32F3xx/F358VCT/PeripheralPins.c | 2 +- .../STM32F3xx/F373C(8-B-C)T/PeripheralPins.c | 2 +- .../STM32F3xx/F373R(8-B-C)T/PeripheralPins.c | 2 +- .../F373V(8-B-C)(H-T)/PeripheralPins.c | 2 +- variants/STM32F3xx/F378CCT/PeripheralPins.c | 2 +- .../STM32F3xx/F378RC(T-Y)/PeripheralPins.c | 2 +- .../STM32F3xx/F378VC(H-T)/PeripheralPins.c | 2 +- variants/STM32F3xx/F398VET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F401R(B-C-D-E)T/PeripheralPins.c | 2 +- .../F401V(B-C-D-E)H/PeripheralPins.c | 2 +- .../F401V(B-C-D-E)T/PeripheralPins.c | 2 +- .../F405O(E-G)Y_F415OGY/PeripheralPins.c | 2 +- .../F405RGT_F415RGT/PeripheralPins.c | 2 +- .../F405VGT_F415VGT/PeripheralPins.c | 2 +- .../F405ZGT_F415ZGT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F407V(E-G)T_F417V(E-G)T/PeripheralPins.c | 2 +- .../F407Z(E-G)T_F417Z(E-G)T/PeripheralPins.c | 2 +- .../STM32F4xx/F410C(8-B)T/PeripheralPins.c | 2 +- .../STM32F4xx/F410C(8-B)U/PeripheralPins.c | 2 +- .../F410R(8-B)(I-T)/PeripheralPins.c | 2 +- .../STM32F4xx/F410T(8-B)Y/PeripheralPins.c | 2 +- .../F411C(C-E)(U-Y)/PeripheralPins.c | 2 +- .../STM32F4xx/F411R(C-E)T/PeripheralPins.c | 2 +- .../STM32F4xx/F411V(C-E)H/PeripheralPins.c | 2 +- .../STM32F4xx/F411V(C-E)T/PeripheralPins.c | 2 +- .../STM32F4xx/F412C(E-G)U/PeripheralPins.c | 2 +- .../F412R(E-G)(T-Y)x(P)/PeripheralPins.c | 2 +- .../STM32F4xx/F412V(E-G)H/PeripheralPins.c | 2 +- .../STM32F4xx/F412V(E-G)T/PeripheralPins.c | 2 +- .../F412Z(E-G)(J-T)/PeripheralPins.c | 2 +- .../F413C(G-H)U_F423CHU/PeripheralPins.c | 2 +- .../F413M(G-H)Y_F423MHY/PeripheralPins.c | 2 +- .../F413R(G-H)T_F423RHT/PeripheralPins.c | 2 +- .../F413V(G-H)H_F423VHH/PeripheralPins.c | 2 +- .../F413V(G-H)T_F423VHT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32F4xx/F446M(C-E)Y/PeripheralPins.c | 2 +- .../STM32F4xx/F446R(C-E)T/PeripheralPins.c | 2 +- .../STM32F4xx/F446V(C-E)T/PeripheralPins.c | 2 +- .../F446Z(C-E)(H-J-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F722Z(C-E)T_F732ZET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../F769I(G-I)T_F779IIT/PeripheralPins.c | 2 +- .../STM32G0xx/G030C(6-8)T/PeripheralPins.c | 2 +- variants/STM32G0xx/G030F6P/PeripheralPins.c | 2 +- variants/STM32G0xx/G030J6M/PeripheralPins.c | 2 +- .../STM32G0xx/G030K(6-8)T/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G031J(4-6)M_G041J6M/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32G0xx/G050C(6-8)T/PeripheralPins.c | 2 +- variants/STM32G0xx/G050F6P/PeripheralPins.c | 2 +- .../STM32G0xx/G050K(6-8)T/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G051G(6-8)U_G061G(6-8)U/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32G0xx/G070CBT/PeripheralPins.c | 2 +- variants/STM32G0xx/G070KBT/PeripheralPins.c | 2 +- variants/STM32G0xx/G070RBT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G071EBY_G081EBY/PeripheralPins.c | 2 +- .../G071G(6-8-B)U_G081GBU/PeripheralPins.c | 2 +- .../G071G(8-B)UxN_G081GBUxN/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32G0xx/G0B0CET/PeripheralPins.c | 2 +- variants/STM32G0xx/G0B0KET/PeripheralPins.c | 2 +- variants/STM32G0xx/G0B0RET/PeripheralPins.c | 2 +- variants/STM32G0xx/G0B0VET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G0B1NEY_G0C1NEY/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32G4xx/G411C(6-8-B)T/PeripheralPins.c | 2 +- .../STM32G4xx/G411C(6-8-B)U/PeripheralPins.c | 2 +- variants/STM32G4xx/G411CCT/PeripheralPins.c | 2 +- variants/STM32G4xx/G411CCU/PeripheralPins.c | 2 +- .../G411K(6-8-B)(T-U)/PeripheralPins.c | 2 +- .../STM32G4xx/G411M(6-8-B)T/PeripheralPins.c | 2 +- variants/STM32G4xx/G411MCT/PeripheralPins.c | 2 +- .../STM32G4xx/G411R(6-8-B)T/PeripheralPins.c | 2 +- variants/STM32G4xx/G411RCT/PeripheralPins.c | 2 +- .../STM32G4xx/G414C(B-C)T/PeripheralPins.c | 2 +- .../STM32G4xx/G414C(B-C)U/PeripheralPins.c | 2 +- .../STM32G4xx/G414M(B-C)T/PeripheralPins.c | 2 +- .../STM32G4xx/G414R(B-C)T/PeripheralPins.c | 2 +- .../STM32G4xx/G414V(B-C)T/PeripheralPins.c | 2 +- .../G431C(6-8-B)T_G441CBT/PeripheralPins.c | 2 +- .../G431C(6-8-B)U_G441CBU/PeripheralPins.c | 2 +- variants/STM32G4xx/G431CBTxZ/PeripheralPins.c | 2 +- .../G431CBY_G441CBY/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G431M(6-8-B)T_G441MBT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G431V(6-8-B)T_G441VBT/PeripheralPins.c | 2 +- .../STM32G4xx/G471C(C-E)T/PeripheralPins.c | 2 +- .../STM32G4xx/G471C(C-E)U/PeripheralPins.c | 2 +- .../STM32G4xx/G471M(C-E)T/PeripheralPins.c | 2 +- variants/STM32G4xx/G471MEY/PeripheralPins.c | 2 +- .../STM32G4xx/G471Q(C-E)T/PeripheralPins.c | 2 +- .../STM32G4xx/G471R(C-E)T/PeripheralPins.c | 2 +- .../G471V(C-E)(H-I-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G491C(C-E)T_G4A1CET/PeripheralPins.c | 2 +- .../STM32G4xx/G491C(C-E)U/PeripheralPins.c | 380 ++++++++++++++++++ variants/STM32G4xx/G491C(C-E)U/PinNamesVar.h | 77 ++++ .../boards_entry.txt | 13 +- .../generic_clock.c | 5 +- .../variant_generic.cpp | 3 +- .../STM32G4xx/G491C(C-E)U/variant_generic.h | 208 ++++++++++ .../G491C(C-E)U_G4A1CEU/CMakeLists.txt | 31 -- .../G491K(C-E)U_G4A1KEU/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../G491V(C-E)T_G4A1VET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 4 +- .../PinNamesVar.h | 0 variants/STM32G4xx/G4A1CEU/boards_entry.txt | 14 + .../G4A1CEU}/generic_clock.c | 3 +- .../STM32G4xx/G4A1CEU/variant_generic.cpp | 85 ++++ .../variant_generic.h | 0 .../STM32H5xx/H503CB(T-U)/PeripheralPins.c | 2 +- variants/STM32H5xx/H503EBY/PeripheralPins.c | 2 +- variants/STM32H5xx/H503KBU/PeripheralPins.c | 2 +- variants/STM32H5xx/H503RBT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../H523HEY_H533HEY/PeripheralPins.c | 2 +- .../H523R(C-E)T_H533RET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32H5xx/H562A(G-I)I/PeripheralPins.c | 2 +- .../H562I(G-I)(K-T)/PeripheralPins.c | 2 +- .../STM32H5xx/H562R(G-I)T/PeripheralPins.c | 2 +- .../STM32H5xx/H562R(G-I)V/PeripheralPins.c | 2 +- .../STM32H5xx/H562V(G-I)T/PeripheralPins.c | 2 +- .../STM32H5xx/H562Z(G-I)T/PeripheralPins.c | 2 +- .../H563A(G-I)I_H573AII/PeripheralPins.c | 2 +- .../H563AIIxQ_H573AIIxQ/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../H563IIKxQ_H573IIKxQ/PeripheralPins.c | 2 +- .../H563IITxQ_H573IITxQ/PeripheralPins.c | 2 +- .../H563MIYxQ_H573MIYxQ/PeripheralPins.c | 2 +- .../H563R(G-I)T_H573RIT/PeripheralPins.c | 2 +- .../H563R(G-I)V_H573RIV/PeripheralPins.c | 2 +- .../H563V(G-I)T_H573VIT/PeripheralPins.c | 2 +- .../H563VITxQ_H573VITxQ/PeripheralPins.c | 2 +- .../H563Z(G-I)T_H573ZIT/PeripheralPins.c | 2 +- .../H563ZITxQ_H573ZITxQ/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../H725R(E-G)V_H735RGV/PeripheralPins.c | 2 +- .../H725V(E-G)H_H735VGH/PeripheralPins.c | 2 +- .../H725V(E-G)T_H735VGT/PeripheralPins.c | 2 +- .../H725VGY_H735VGY/PeripheralPins.c | 2 +- .../H725Z(E-G)T_H735ZGT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../H745B(G-I)T_H755BIT/PeripheralPins.c | 2 +- .../H745I(G-I)K_H755IIK/PeripheralPins.c | 2 +- .../H745I(G-I)T_H755IIT/PeripheralPins.c | 2 +- .../H745Z(G-I)T_H755ZIT/PeripheralPins.c | 2 +- .../H747B(G-I)T_H757BIT/PeripheralPins.c | 2 +- .../H747ZIY_H757ZIY/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../H7A3I(G-I)TxQ_H7B3IITxQ/PeripheralPins.c | 2 +- .../H7A3L(G-I)HxQ_H7B3LIHxQ/PeripheralPins.c | 2 +- .../H7A3N(G-I)H_H7B3NIH/PeripheralPins.c | 2 +- .../H7A3QIYxQ_H7B3QIYxQ/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../H7A3V(G-I)HxQ_H7B3VIHxQ/PeripheralPins.c | 2 +- .../H7A3V(G-I)TxQ_H7B3VITxQ/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../H7A3Z(G-I)TxQ_H7B3ZITxQ/PeripheralPins.c | 2 +- variants/STM32L0xx/L010C6T/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L0xx/L010K8T/PeripheralPins.c | 2 +- variants/STM32L0xx/L010R8T/PeripheralPins.c | 2 +- variants/STM32L0xx/L010RBT/PeripheralPins.c | 2 +- .../L011D(3-4)P_L021D4P/PeripheralPins.c | 2 +- .../STM32L0xx/L011E(3-4)Y/PeripheralPins.c | 2 +- .../L011F(3-4)U_L021F4U/PeripheralPins.c | 2 +- .../L011G(3-4)U_L021G4U/PeripheralPins.c | 2 +- .../L011K(3-4)U_L021K4U/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L031E(4-6)Y_L041E6Y/PeripheralPins.c | 2 +- .../L031F(4-6)P_L041F6P/PeripheralPins.c | 2 +- .../L031G(4-6)U_L041G6U/PeripheralPins.c | 2 +- .../L031G6UxS_L041G6UxS/PeripheralPins.c | 2 +- .../L031K(4-6)T_L041K6T/PeripheralPins.c | 2 +- .../L031K(4-6)U_L041K6U/PeripheralPins.c | 2 +- .../L051C(6-8)(T-U)/PeripheralPins.c | 2 +- .../STM32L0xx/L051K(6-8)T/PeripheralPins.c | 2 +- .../STM32L0xx/L051K(6-8)U/PeripheralPins.c | 2 +- .../STM32L0xx/L051R(6-8)H/PeripheralPins.c | 2 +- .../STM32L0xx/L051R(6-8)T/PeripheralPins.c | 2 +- .../STM32L0xx/L051T(6-8)Y/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L052K(6-8)T_L062K8T/PeripheralPins.c | 2 +- .../L052K(6-8)U_L062K8U/PeripheralPins.c | 2 +- .../L052R(6-8)H_L053R(6-8)H/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L052T6Y_L052T8(F-Y)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32L0xx/L071C(B-Z)Y/PeripheralPins.c | 2 +- .../L071K(8-B-Z)U_L081KZU/PeripheralPins.c | 2 +- .../L071K(B-Z)T_L081KZT/PeripheralPins.c | 2 +- .../STM32L0xx/L071R(B-Z)H/PeripheralPins.c | 2 +- .../STM32L0xx/L071R(B-Z)T/PeripheralPins.c | 2 +- .../L071V(8-B-Z)(I-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L072K(B-Z)T_L082K(B-Z)T/PeripheralPins.c | 2 +- .../L072K(B-Z)U_L082K(B-Z)U/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L1xx/L100RCT/PeripheralPins.c | 2 +- .../L151CC(T-U)_L152CC(T-U)/PeripheralPins.c | 2 +- .../L151QCH_L152QCH_L162QCH/PeripheralPins.c | 2 +- .../L151QDH_L152QDH_L162QDH/PeripheralPins.c | 2 +- .../L151QEH_L152QEH/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L151RET_L152RET_L162RET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L151VDT_L152VDT_L162VDT/PeripheralPins.c | 2 +- .../L151ZCT_L152ZCT_L162ZCT/PeripheralPins.c | 2 +- .../L151ZDT_L152ZDT_L162ZDT/PeripheralPins.c | 2 +- .../L151ZET_L152ZET_L162ZET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32L4xx/L412CB(T-U)xP/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32L4xx/L412RB(I-T)xP/PeripheralPins.c | 2 +- .../L412T(8-B)Y_L422TBY/PeripheralPins.c | 2 +- variants/STM32L4xx/L412TBYxP/PeripheralPins.c | 2 +- .../L431C(B-C)(T-U)/PeripheralPins.c | 2 +- .../STM32L4xx/L431C(B-C)Y/PeripheralPins.c | 2 +- .../STM32L4xx/L431K(B-C)U/PeripheralPins.c | 2 +- .../L431R(B-C)(I-T-Y)/PeripheralPins.c | 2 +- .../STM32L4xx/L431VC(I-T)/PeripheralPins.c | 2 +- .../L432K(B-C)U_L442KCU/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L4xx/L433RCTxP/PeripheralPins.c | 2 +- .../L433VC(I-T)_L443VC(I-T)/PeripheralPins.c | 2 +- .../L451CCU_L451CE(T-U)/PeripheralPins.c | 2 +- .../L451R(C-E)(I-T-Y)/PeripheralPins.c | 2 +- .../L451V(C-E)(I-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L4xx/L452RETxP/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32L4xx/L471Q(E-G)I/PeripheralPins.c | 2 +- .../STM32L4xx/L471R(E-G)T/PeripheralPins.c | 2 +- .../STM32L4xx/L471V(E-G)T/PeripheralPins.c | 2 +- .../L471Z(E-G)(J-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L4xx/L476JGYxP/PeripheralPins.c | 2 +- .../STM32L4xx/L476M(E-G)Y/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L4xx/L476VGYxP/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L4xx/L476ZGTxP/PeripheralPins.c | 2 +- .../L496A(E-G)I_L4A6AGI/PeripheralPins.c | 2 +- .../L496AGIxP_L4A6AGIxP/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L496QGIxP_L4A6QGIxP/PeripheralPins.c | 2 +- .../L496R(E-G)T_L4A6RGT/PeripheralPins.c | 2 +- variants/STM32L4xx/L496RGTxP/PeripheralPins.c | 2 +- .../L496V(E-G)T_L4A6VGT/PeripheralPins.c | 2 +- .../L496VGTxP_L4A6VGTxP/PeripheralPins.c | 2 +- .../L496VGY_L4A6VGY/PeripheralPins.c | 2 +- .../L496VGYxP_L4A6VGYxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L496WGYxP/PeripheralPins.c | 2 +- .../L496Z(E-G)T_L4A6ZGT/PeripheralPins.c | 2 +- .../L496ZGTxP_L4A6ZGTxP/PeripheralPins.c | 2 +- variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c | 2 +- .../L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c | 2 +- .../L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c | 2 +- .../L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c | 2 +- .../L4P5R(G-E)T_L4Q5RGT/PeripheralPins.c | 2 +- .../L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c | 2 +- .../L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c | 2 +- .../L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c | 2 +- .../L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c | 2 +- .../L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c | 2 +- .../L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c | 2 +- .../L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c | 2 +- .../L4R9A(G-I)I_L4S9AII/PeripheralPins.c | 2 +- .../L4R9V(G-I)T_L4S9VIT/PeripheralPins.c | 2 +- .../L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c | 2 +- .../L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c | 2 +- variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../L552MEYxP_L562MEYxP/PeripheralPins.c | 2 +- .../L552MEYxQ_L562MEYxQ/PeripheralPins.c | 2 +- .../L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins.c | 2 +- .../L552QEI_L562QEI/PeripheralPins.c | 2 +- .../L552QEIxP_L562QEIxP/PeripheralPins.c | 2 +- .../L552R(C-E)T_L562RET/PeripheralPins.c | 2 +- .../L552RETxP_L562RETxP/PeripheralPins.c | 2 +- .../L552RETxQ_L562RETxQ/PeripheralPins.c | 2 +- .../L552V(C-E)TxQ_L562VETxQ/PeripheralPins.c | 2 +- .../L552VET_L562VET/PeripheralPins.c | 2 +- .../L552Z(C-E)TxQ_L562ZETxQ/PeripheralPins.c | 2 +- .../L552ZET_L562ZET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U031C(6-8)(T-U)/PeripheralPins.c | 2 +- .../STM32U0xx/U031F(4-6-8)P/PeripheralPins.c | 2 +- .../STM32U0xx/U031G(6-8)Y/PeripheralPins.c | 2 +- .../STM32U0xx/U031K(4-6-8)U/PeripheralPins.c | 2 +- .../U031R(6-8)(I-T)/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U073H(8-B-C)Y_U083HCY/PeripheralPins.c | 2 +- .../U073K(8-B-C)U_U083KCU/PeripheralPins.c | 2 +- .../U073M(8-B-C)I_U083MCI/PeripheralPins.c | 2 +- .../U073M(8-B-C)T_U083MCT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../boards_entry.txt | 12 +- .../PeripheralPins.c | 2 +- .../boards_entry.txt | 12 +- .../U375C(E-G)YxQ_U385CGYxQ/PeripheralPins.c | 2 +- .../U375C(E-G)YxQ_U385CGYxQ/boards_entry.txt | 6 +- .../U375K(E-G)U_U385KGU/PeripheralPins.c | 2 +- .../U375K(E-G)U_U385KGU/boards_entry.txt | 6 +- .../U375R(E-G)I_U385RGI/PeripheralPins.c | 2 +- .../U375R(E-G)I_U385RGI/boards_entry.txt | 6 +- .../U375R(E-G)IxQ_U385RGIxQ/PeripheralPins.c | 2 +- .../U375R(E-G)IxQ_U385RGIxQ/boards_entry.txt | 6 +- .../U375R(E-G)T_U385RGT/PeripheralPins.c | 2 +- .../U375R(E-G)T_U385RGT/boards_entry.txt | 6 +- .../U375R(E-G)TxQ_U385RGTxQ/PeripheralPins.c | 2 +- .../U375R(E-G)TxQ_U385RGTxQ/boards_entry.txt | 6 +- .../U375R(E-G)YxG_U385RGYxG/PeripheralPins.c | 2 +- .../U375R(E-G)YxG_U385RGYxG/boards_entry.txt | 6 +- .../U375R(E-G)YxQ_U385RGYxQ/PeripheralPins.c | 2 +- .../U375R(E-G)YxQ_U385RGYxQ/boards_entry.txt | 6 +- .../U375V(E-G)I_U385VGI/PeripheralPins.c | 2 +- .../U375V(E-G)I_U385VGI/boards_entry.txt | 6 +- .../U375V(E-G)IxQ_U385VGIxQ/PeripheralPins.c | 2 +- .../U375V(E-G)IxQ_U385VGIxQ/boards_entry.txt | 6 +- .../U375V(E-G)T_U385VGT/PeripheralPins.c | 2 +- .../U375V(E-G)T_U385VGT/boards_entry.txt | 6 +- .../U375V(E-G)TxQ_U385VGTxQ/PeripheralPins.c | 2 +- .../U375V(E-G)TxQ_U385VGTxQ/boards_entry.txt | 6 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U535JEYxQ_U545JEYxQ/PeripheralPins.c | 2 +- .../U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c | 2 +- .../U535R(B-C-E)I_U545REI/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U535R(B-C-E)T_U545RET/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U535V(C-E)I_U545VEI/PeripheralPins.c | 2 +- .../U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c | 2 +- .../U535V(C-E)T_U545VET/PeripheralPins.c | 2 +- .../U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c | 2 +- .../U575A(G-I)I_U585AII/PeripheralPins.c | 2 +- .../U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c | 2 +- .../U575Q(G-I)I_U585QII/PeripheralPins.c | 2 +- .../U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c | 2 +- .../U575R(G-I)T_U585RIT/PeripheralPins.c | 2 +- .../U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c | 2 +- .../U575V(G-I)T_U585VIT/PeripheralPins.c | 2 +- .../U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c | 2 +- .../U575Z(G-I)T_U585ZIT/PeripheralPins.c | 2 +- .../U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c | 2 +- .../U595A(I-J)H_U5A5AJH/PeripheralPins.c | 2 +- .../U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c | 2 +- .../U595Q(I-J)I_U5A5QJI/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U595R(I-J)T_U5A5RJT/PeripheralPins.c | 2 +- .../U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U595Z(I-J)T_U5A5ZJT/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c | 2 +- .../U599BJYxQ_U5A9BJYxQ/PeripheralPins.c | 2 +- .../U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c | 2 +- .../U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c | 2 +- .../STM32U5xx/U5F7V(I-J)T/PeripheralPins.c | 2 +- .../STM32U5xx/U5F7V(I-J)TxQ/PeripheralPins.c | 2 +- .../U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c | 2 +- variants/STM32U5xx/U5F9NJHxQ/PeripheralPins.c | 2 +- .../STM32U5xx/U5F9V(I-J)TxQ/PeripheralPins.c | 2 +- .../STM32U5xx/U5F9Z(I-J)JxQ/PeripheralPins.c | 2 +- .../STM32U5xx/U5F9Z(I-J)TxQ/PeripheralPins.c | 2 +- variants/STM32U5xx/U5G7VJT/PeripheralPins.c | 2 +- variants/STM32U5xx/U5G7VJTxQ/PeripheralPins.c | 2 +- variants/STM32U5xx/U5G9NJHxQ/PeripheralPins.c | 2 +- variants/STM32U5xx/U5G9VJTxQ/PeripheralPins.c | 2 +- variants/STM32U5xx/U5G9ZJJxQ/PeripheralPins.c | 2 +- variants/STM32U5xx/U5G9ZJTxQ/PeripheralPins.c | 2 +- variants/STM32WBAxx/WBA5MMGH/boards_entry.txt | 1 + variants/STM32WBxx/WB10CCU/PeripheralPins.c | 2 +- variants/STM32WBxx/WB15CCU/PeripheralPins.c | 2 +- variants/STM32WBxx/WB15CCUxE/PeripheralPins.c | 2 +- variants/STM32WBxx/WB15CCY/PeripheralPins.c | 2 +- variants/STM32WBxx/WB1MMCH/PeripheralPins.c | 2 +- .../WB30CEUxA_WB50CGU/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../boards_entry.txt | 4 +- variants/STM32WBxx/WB5MMGH/PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- .../PeripheralPins.c | 2 +- variants/STM32WLxx/WL5MOCH/PeripheralPins.c | 2 +- 685 files changed, 1772 insertions(+), 845 deletions(-) rename variants/STM32C0xx/{C092CBU_C092CC(T-U) => C092C(B-C)(T-U)}/PeripheralPins.c (99%) rename variants/STM32C0xx/{C092CBU_C092CC(T-U) => C092C(B-C)(T-U)}/PinNamesVar.h (100%) rename variants/STM32C0xx/{C092CBU_C092CC(T-U) => C092C(B-C)(T-U)}/boards_entry.txt (67%) rename variants/STM32C0xx/{C092CBT_C092RBT_C092RC(I-T) => C092C(B-C)(T-U)}/generic_clock.c (95%) create mode 100644 variants/STM32C0xx/C092C(B-C)(T-U)/ldscript.ld rename variants/STM32C0xx/{C092CBU_C092CC(T-U) => C092C(B-C)(T-U)}/variant_generic.cpp (92%) rename variants/STM32C0xx/{C092CBU_C092CC(T-U) => C092C(B-C)(T-U)}/variant_generic.h (100%) delete mode 100644 variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/CMakeLists.txt delete mode 100644 variants/STM32C0xx/C092CBU_C092CC(T-U)/CMakeLists.txt rename variants/STM32C0xx/{C092CBT_C092RBT_C092RC(I-T) => C092RBT_C092RC(I-T)}/PeripheralPins.c (99%) rename variants/STM32C0xx/{C092CBT_C092RBT_C092RC(I-T) => C092RBT_C092RC(I-T)}/PinNamesVar.h (100%) rename variants/STM32C0xx/{C092CBT_C092RBT_C092RC(I-T) => C092RBT_C092RC(I-T)}/boards_entry.txt (66%) create mode 100644 variants/STM32C0xx/C092RBT_C092RC(I-T)/generic_clock.c rename variants/STM32C0xx/{C092CBT_C092RBT_C092RC(I-T) => C092RBT_C092RC(I-T)}/ldscript.ld (100%) rename variants/STM32C0xx/{C092CBT_C092RBT_C092RC(I-T) => C092RBT_C092RC(I-T)}/variant_NUCLEO_C092RC.cpp (100%) rename variants/STM32C0xx/{C092CBT_C092RBT_C092RC(I-T) => C092RBT_C092RC(I-T)}/variant_NUCLEO_C092RC.h (100%) rename variants/STM32C0xx/{C092CBT_C092RBT_C092RC(I-T) => C092RBT_C092RC(I-T)}/variant_generic.cpp (93%) rename variants/STM32C0xx/{C092CBT_C092RBT_C092RC(I-T) => C092RBT_C092RC(I-T)}/variant_generic.h (100%) create mode 100644 variants/STM32G4xx/G491C(C-E)U/PeripheralPins.c create mode 100644 variants/STM32G4xx/G491C(C-E)U/PinNamesVar.h rename variants/STM32G4xx/{G491C(C-E)U_G4A1CEU => G491C(C-E)U}/boards_entry.txt (69%) rename variants/STM32G4xx/{G491C(C-E)U_G4A1CEU => G491C(C-E)U}/generic_clock.c (89%) rename variants/STM32G4xx/{G491C(C-E)U_G4A1CEU => G491C(C-E)U}/variant_generic.cpp (97%) create mode 100644 variants/STM32G4xx/G491C(C-E)U/variant_generic.h delete mode 100644 variants/STM32G4xx/G491C(C-E)U_G4A1CEU/CMakeLists.txt rename variants/STM32G4xx/{G491C(C-E)U_G4A1CEU => G4A1CEU}/PeripheralPins.c (99%) rename variants/STM32G4xx/{G491C(C-E)U_G4A1CEU => G4A1CEU}/PinNamesVar.h (100%) create mode 100644 variants/STM32G4xx/G4A1CEU/boards_entry.txt rename variants/{STM32C0xx/C092CBU_C092CC(T-U) => STM32G4xx/G4A1CEU}/generic_clock.c (87%) create mode 100644 variants/STM32G4xx/G4A1CEU/variant_generic.cpp rename variants/STM32G4xx/{G491C(C-E)U_G4A1CEU => G4A1CEU}/variant_generic.h (100%) diff --git a/README.md b/README.md index c9377b8e62..07cd09856a 100644 --- a/README.md +++ b/README.md @@ -227,7 +227,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32C031F4
STM32C031F6 | Generic Board | *2.6.0* | | | :green_heart: | STM32C071G8
STM32C071GB | Generic Board | *2.11.0* | | | :green_heart: | STM32C071R8
STM32C071RB | Generic Board | *2.9.0* | | -| :green_heart: | STM32C092CBT | Generic Board | *2.11.0* | | +| :yellow_heart: | STM32C092CB
STM32C092CC| Generic Board | **2.12.0** | STM32C092CBT since 2.11.0 | | :green_heart: | STM32C092RBT
STM32C092RCT | Generic Board | *2.11.0* | | | :green_heart: | STM32C092RCI | Generic Board | *2.11.0* | | diff --git a/boards.txt b/boards.txt index 17d2769d65..70e6ab6f95 100644 --- a/boards.txt +++ b/boards.txt @@ -501,7 +501,7 @@ Nucleo_64.menu.pnum.NUCLEO_C092RC.build.mcu=cortex-m0plus Nucleo_64.menu.pnum.NUCLEO_C092RC.build.board=NUCLEO_C092RC Nucleo_64.menu.pnum.NUCLEO_C092RC.build.series=STM32C0xx Nucleo_64.menu.pnum.NUCLEO_C092RC.build.product_line=STM32C092xx -Nucleo_64.menu.pnum.NUCLEO_C092RC.build.variant=STM32C0xx/C092CBT_C092RBT_C092RC(I-T) +Nucleo_64.menu.pnum.NUCLEO_C092RC.build.variant=STM32C0xx/C092RBT_C092RC(I-T) Nucleo_64.menu.pnum.NUCLEO_C092RC.build.st_extra_flags=-DSTM32C092xx {build.xSerial} -D__CORTEX_SC=0 Nucleo_64.menu.pnum.NUCLEO_C092RC.openocd.target=stm32c0x Nucleo_64.menu.pnum.NUCLEO_C092RC.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd @@ -905,7 +905,7 @@ Nucleo_64.menu.pnum.NUCLEO_U385RG_Q.build.series=STM32U3xx Nucleo_64.menu.pnum.NUCLEO_U385RG_Q.build.product_line=STM32U385xx Nucleo_64.menu.pnum.NUCLEO_U385RG_Q.build.variant=STM32U3xx/U375R(E-G)TxQ_U385RGTxQ #Nucleo_64.menu.pnum.NUCLEO_U385RG_Q.openocd.target=stm32u3x -#Nucleo_64.menu.pnum.NUCLEO_U385RG_Q.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +#Nucleo_64.menu.pnum.NUCLEO_U385RG_Q.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd # NUCLEO_WB09KE board Nucleo_64.menu.pnum.NUCLEO_WB09KE=Nucleo WB09KE @@ -1871,16 +1871,43 @@ GenC0.menu.pnum.GENERIC_C092CBTX.upload.maximum_size=131072 GenC0.menu.pnum.GENERIC_C092CBTX.upload.maximum_data_size=30720 GenC0.menu.pnum.GENERIC_C092CBTX.build.board=GENERIC_C092CBTX GenC0.menu.pnum.GENERIC_C092CBTX.build.product_line=STM32C092xx -GenC0.menu.pnum.GENERIC_C092CBTX.build.variant=STM32C0xx/C092CBT_C092RBT_C092RC(I-T) +GenC0.menu.pnum.GENERIC_C092CBTX.build.variant=STM32C0xx/C092C(B-C)(T-U) GenC0.menu.pnum.GENERIC_C092CBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd +# Generic C092CBUx +GenC0.menu.pnum.GENERIC_C092CBUX=Generic C092CBUx +GenC0.menu.pnum.GENERIC_C092CBUX.upload.maximum_size=131072 +GenC0.menu.pnum.GENERIC_C092CBUX.upload.maximum_data_size=30720 +GenC0.menu.pnum.GENERIC_C092CBUX.build.board=GENERIC_C092CBUX +GenC0.menu.pnum.GENERIC_C092CBUX.build.product_line=STM32C092xx +GenC0.menu.pnum.GENERIC_C092CBUX.build.variant=STM32C0xx/C092C(B-C)(T-U) +GenC0.menu.pnum.GENERIC_C092CBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd + +# Generic C092CCTx +GenC0.menu.pnum.GENERIC_C092CCTX=Generic C092CCTx +GenC0.menu.pnum.GENERIC_C092CCTX.upload.maximum_size=262144 +GenC0.menu.pnum.GENERIC_C092CCTX.upload.maximum_data_size=30720 +GenC0.menu.pnum.GENERIC_C092CCTX.build.board=GENERIC_C092CCTX +GenC0.menu.pnum.GENERIC_C092CCTX.build.product_line=STM32C092xx +GenC0.menu.pnum.GENERIC_C092CCTX.build.variant=STM32C0xx/C092C(B-C)(T-U) +GenC0.menu.pnum.GENERIC_C092CCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd + +# Generic C092CCUx +GenC0.menu.pnum.GENERIC_C092CCUX=Generic C092CCUx +GenC0.menu.pnum.GENERIC_C092CCUX.upload.maximum_size=262144 +GenC0.menu.pnum.GENERIC_C092CCUX.upload.maximum_data_size=30720 +GenC0.menu.pnum.GENERIC_C092CCUX.build.board=GENERIC_C092CCUX +GenC0.menu.pnum.GENERIC_C092CCUX.build.product_line=STM32C092xx +GenC0.menu.pnum.GENERIC_C092CCUX.build.variant=STM32C0xx/C092C(B-C)(T-U) +GenC0.menu.pnum.GENERIC_C092CCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd + # Generic C092RBTx GenC0.menu.pnum.GENERIC_C092RBTX=Generic C092RBTx GenC0.menu.pnum.GENERIC_C092RBTX.upload.maximum_size=131072 GenC0.menu.pnum.GENERIC_C092RBTX.upload.maximum_data_size=30720 GenC0.menu.pnum.GENERIC_C092RBTX.build.board=GENERIC_C092RBTX GenC0.menu.pnum.GENERIC_C092RBTX.build.product_line=STM32C092xx -GenC0.menu.pnum.GENERIC_C092RBTX.build.variant=STM32C0xx/C092CBT_C092RBT_C092RC(I-T) +GenC0.menu.pnum.GENERIC_C092RBTX.build.variant=STM32C0xx/C092RBT_C092RC(I-T) GenC0.menu.pnum.GENERIC_C092RBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd # Generic C092RCIx @@ -1889,7 +1916,7 @@ GenC0.menu.pnum.GENERIC_C092RCIX.upload.maximum_size=262144 GenC0.menu.pnum.GENERIC_C092RCIX.upload.maximum_data_size=30720 GenC0.menu.pnum.GENERIC_C092RCIX.build.board=GENERIC_C092RCIX GenC0.menu.pnum.GENERIC_C092RCIX.build.product_line=STM32C092xx -GenC0.menu.pnum.GENERIC_C092RCIX.build.variant=STM32C0xx/C092CBT_C092RBT_C092RC(I-T) +GenC0.menu.pnum.GENERIC_C092RCIX.build.variant=STM32C0xx/C092RBT_C092RC(I-T) GenC0.menu.pnum.GENERIC_C092RCIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd # Generic C092RCTx @@ -1898,7 +1925,7 @@ GenC0.menu.pnum.GENERIC_C092RCTX.upload.maximum_size=262144 GenC0.menu.pnum.GENERIC_C092RCTX.upload.maximum_data_size=30720 GenC0.menu.pnum.GENERIC_C092RCTX.build.board=GENERIC_C092RCTX GenC0.menu.pnum.GENERIC_C092RCTX.build.product_line=STM32C092xx -GenC0.menu.pnum.GENERIC_C092RCTX.build.variant=STM32C0xx/C092CBT_C092RBT_C092RC(I-T) +GenC0.menu.pnum.GENERIC_C092RCTX.build.variant=STM32C0xx/C092RBT_C092RC(I-T) GenC0.menu.pnum.GENERIC_C092RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd # Upload menu @@ -12697,7 +12724,7 @@ GenU3.menu.pnum.GENERIC_U375RETXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375RETXQ.build.board=GENERIC_U375RETXQ GenU3.menu.pnum.GENERIC_U375RETXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375RETXQ.build.variant=STM32U3xx/U375R(E-G)TxQ_U385RGTxQ -GenU3.menu.pnum.GENERIC_U375RETXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375RETXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375RGTxQ GenU3.menu.pnum.GENERIC_U375RGTXQ=Generic U375RGTxQ @@ -12706,7 +12733,7 @@ GenU3.menu.pnum.GENERIC_U375RGTXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375RGTXQ.build.board=GENERIC_U375RGTXQ GenU3.menu.pnum.GENERIC_U375RGTXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375RGTXQ.build.variant=STM32U3xx/U375R(E-G)TxQ_U385RGTxQ -GenU3.menu.pnum.GENERIC_U375RGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375RGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375VEIx GenU3.menu.pnum.GENERIC_U375VEIX=Generic U375VEIx @@ -12715,7 +12742,7 @@ GenU3.menu.pnum.GENERIC_U375VEIX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375VEIX.build.board=GENERIC_U375VEIX GenU3.menu.pnum.GENERIC_U375VEIX.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375VEIX.build.variant=STM32U3xx/U375V(E-G)I_U385VGI -GenU3.menu.pnum.GENERIC_U375VEIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375VEIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375VEIxQ GenU3.menu.pnum.GENERIC_U375VEIXQ=Generic U375VEIxQ @@ -12724,7 +12751,7 @@ GenU3.menu.pnum.GENERIC_U375VEIXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375VEIXQ.build.board=GENERIC_U375VEIXQ GenU3.menu.pnum.GENERIC_U375VEIXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375VEIXQ.build.variant=STM32U3xx/U375V(E-G)IxQ_U385VGIxQ -GenU3.menu.pnum.GENERIC_U375VEIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375VEIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375VGIx GenU3.menu.pnum.GENERIC_U375VGIX=Generic U375VGIx @@ -12733,7 +12760,7 @@ GenU3.menu.pnum.GENERIC_U375VGIX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375VGIX.build.board=GENERIC_U375VGIX GenU3.menu.pnum.GENERIC_U375VGIX.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375VGIX.build.variant=STM32U3xx/U375V(E-G)I_U385VGI -GenU3.menu.pnum.GENERIC_U375VGIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375VGIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375VGIxQ GenU3.menu.pnum.GENERIC_U375VGIXQ=Generic U375VGIxQ @@ -12742,7 +12769,7 @@ GenU3.menu.pnum.GENERIC_U375VGIXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375VGIXQ.build.board=GENERIC_U375VGIXQ GenU3.menu.pnum.GENERIC_U375VGIXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375VGIXQ.build.variant=STM32U3xx/U375V(E-G)IxQ_U385VGIxQ -GenU3.menu.pnum.GENERIC_U375VGIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375VGIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U385RGTxQ GenU3.menu.pnum.GENERIC_U385RGTXQ=Generic U385RGTxQ @@ -12751,7 +12778,7 @@ GenU3.menu.pnum.GENERIC_U385RGTXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U385RGTXQ.build.board=GENERIC_U385RGTXQ GenU3.menu.pnum.GENERIC_U385RGTXQ.build.product_line=STM32U385xx GenU3.menu.pnum.GENERIC_U385RGTXQ.build.variant=STM32U3xx/U375R(E-G)TxQ_U385RGTxQ -GenU3.menu.pnum.GENERIC_U385RGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U385RGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd # Generic U385VGIx GenU3.menu.pnum.GENERIC_U385VGIX=Generic U385VGIx @@ -12760,7 +12787,7 @@ GenU3.menu.pnum.GENERIC_U385VGIX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U385VGIX.build.board=GENERIC_U385VGIX GenU3.menu.pnum.GENERIC_U385VGIX.build.product_line=STM32U385xx GenU3.menu.pnum.GENERIC_U385VGIX.build.variant=STM32U3xx/U375V(E-G)I_U385VGI -GenU3.menu.pnum.GENERIC_U385VGIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U385VGIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd # Generic U385VGIxQ GenU3.menu.pnum.GENERIC_U385VGIXQ=Generic U385VGIxQ @@ -12769,7 +12796,7 @@ GenU3.menu.pnum.GENERIC_U385VGIXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U385VGIXQ.build.board=GENERIC_U385VGIXQ GenU3.menu.pnum.GENERIC_U385VGIXQ.build.product_line=STM32U385xx GenU3.menu.pnum.GENERIC_U385VGIXQ.build.variant=STM32U3xx/U375V(E-G)IxQ_U385VGIxQ -GenU3.menu.pnum.GENERIC_U385VGIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U385VGIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd # Upload menu GenU3.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) @@ -13110,7 +13137,7 @@ GenWB.menu.pnum.GENERIC_WB55VCYX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic WB55VEQx GenWB.menu.pnum.GENERIC_WB55VEQX=Generic WB55VEQx GenWB.menu.pnum.GENERIC_WB55VEQX.upload.maximum_size=262144 -GenWB.menu.pnum.GENERIC_WB55VEQX.upload.maximum_data_size=65536 +GenWB.menu.pnum.GENERIC_WB55VEQX.upload.maximum_data_size=131072 GenWB.menu.pnum.GENERIC_WB55VEQX.build.board=GENERIC_WB55VEQX GenWB.menu.pnum.GENERIC_WB55VEQX.build.product_line=STM32WB55xx GenWB.menu.pnum.GENERIC_WB55VEQX.build.variant=STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY @@ -13128,7 +13155,7 @@ GenWB.menu.pnum.GENERIC_WB55VEYX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic WB55VGQx GenWB.menu.pnum.GENERIC_WB55VGQX=Generic WB55VGQx GenWB.menu.pnum.GENERIC_WB55VGQX.upload.maximum_size=524288 -GenWB.menu.pnum.GENERIC_WB55VGQX.upload.maximum_data_size=65536 +GenWB.menu.pnum.GENERIC_WB55VGQX.upload.maximum_data_size=131072 GenWB.menu.pnum.GENERIC_WB55VGQX.build.board=GENERIC_WB55VGQX GenWB.menu.pnum.GENERIC_WB55VGQX.build.product_line=STM32WB55xx GenWB.menu.pnum.GENERIC_WB55VGQX.build.variant=STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY diff --git a/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)/PeripheralPins.c b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)/PeripheralPins.c index ca3de2628a..1641b264ca 100644 --- a/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C011D6Y_C011F(4-6)(P-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C011D6Yx.xml, STM32C011F(4-6)Px.xml * STM32C011F(4-6)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C011J(4-6)M/PeripheralPins.c b/variants/STM32C0xx/C011J(4-6)M/PeripheralPins.c index ecf48b6787..f4c335b36a 100644 --- a/variants/STM32C0xx/C011J(4-6)M/PeripheralPins.c +++ b/variants/STM32C0xx/C011J(4-6)M/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C011J(4-6)Mx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C031C(4-6)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C031C(4-6)(T-U)/PeripheralPins.c index f8bddd9dcd..f79b662648 100644 --- a/variants/STM32C0xx/C031C(4-6)(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C031C(4-6)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C031C(4-6)Tx.xml, STM32C031C(4-6)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C031F(4-6)P/PeripheralPins.c b/variants/STM32C0xx/C031F(4-6)P/PeripheralPins.c index a26aece10c..159d1d7f5e 100644 --- a/variants/STM32C0xx/C031F(4-6)P/PeripheralPins.c +++ b/variants/STM32C0xx/C031F(4-6)P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C031F(4-6)Px.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C031G(4-6)U/PeripheralPins.c b/variants/STM32C0xx/C031G(4-6)U/PeripheralPins.c index 9bd0c86808..523e74ef1e 100644 --- a/variants/STM32C0xx/C031G(4-6)U/PeripheralPins.c +++ b/variants/STM32C0xx/C031G(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C031G(4-6)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C031K(4-6)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C031K(4-6)(T-U)/PeripheralPins.c index e4cb794114..cbc060e6fe 100644 --- a/variants/STM32C0xx/C031K(4-6)(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C031K(4-6)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C031K(4-6)Tx.xml, STM32C031K(4-6)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C051C(6-8)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C051C(6-8)(T-U)/PeripheralPins.c index 0d9315fbbc..acd05997d1 100644 --- a/variants/STM32C0xx/C051C(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C051C(6-8)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C051C6Tx.xml, STM32C051C6Ux.xml * STM32C051C8Tx.xml, STM32C051C8Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C051D8Y_C051F(6-8)P/PeripheralPins.c b/variants/STM32C0xx/C051D8Y_C051F(6-8)P/PeripheralPins.c index 5dcdf8fbfe..f24f63065b 100644 --- a/variants/STM32C0xx/C051D8Y_C051F(6-8)P/PeripheralPins.c +++ b/variants/STM32C0xx/C051D8Y_C051F(6-8)P/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C051D8Yx.xml, STM32C051F6Px.xml * STM32C051F8Px.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C051G(6-8)U/PeripheralPins.c b/variants/STM32C0xx/C051G(6-8)U/PeripheralPins.c index 4732c97765..df7e977806 100644 --- a/variants/STM32C0xx/C051G(6-8)U/PeripheralPins.c +++ b/variants/STM32C0xx/C051G(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C051G6Ux.xml, STM32C051G8Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C051K6(T-U)_C051K8T/PeripheralPins.c b/variants/STM32C0xx/C051K6(T-U)_C051K8T/PeripheralPins.c index 9bf2cc123e..d16a08c75c 100644 --- a/variants/STM32C0xx/C051K6(T-U)_C051K8T/PeripheralPins.c +++ b/variants/STM32C0xx/C051K6(T-U)_C051K8T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C051K6Tx.xml, STM32C051K6Ux.xml * STM32C051K8Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071C(8-B)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C071C(8-B)(T-U)/PeripheralPins.c index 5ccea63acd..31af92e34b 100644 --- a/variants/STM32C0xx/C071C(8-B)(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C071C(8-B)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C071C8Tx.xml, STM32C071C8Ux.xml * STM32C071CBTx.xml, STM32C071CBUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071C(8-B)(T-U)xN/PeripheralPins.c b/variants/STM32C0xx/C071C(8-B)(T-U)xN/PeripheralPins.c index b3e0d7b3ef..0e12b73bc5 100644 --- a/variants/STM32C0xx/C071C(8-B)(T-U)xN/PeripheralPins.c +++ b/variants/STM32C0xx/C071C(8-B)(T-U)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C071C8TxN.xml, STM32C071C8UxN.xml * STM32C071CBTxN.xml, STM32C071CBUxN.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071F(8-B)PxN/PeripheralPins.c b/variants/STM32C0xx/C071F(8-B)PxN/PeripheralPins.c index 0a35952aa1..964aa6a9ae 100644 --- a/variants/STM32C0xx/C071F(8-B)PxN/PeripheralPins.c +++ b/variants/STM32C0xx/C071F(8-B)PxN/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C071F8PxN.xml, STM32C071FBPxN.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071F8P_C071FB(P-Y)/PeripheralPins.c b/variants/STM32C0xx/C071F8P_C071FB(P-Y)/PeripheralPins.c index 4e60912e49..621d134ab9 100644 --- a/variants/STM32C0xx/C071F8P_C071FB(P-Y)/PeripheralPins.c +++ b/variants/STM32C0xx/C071F8P_C071FB(P-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C071F8Px.xml, STM32C071FBPx.xml * STM32C071FBYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071G(8-B)U/PeripheralPins.c b/variants/STM32C0xx/C071G(8-B)U/PeripheralPins.c index a23dfda406..f3b779b6e8 100644 --- a/variants/STM32C0xx/C071G(8-B)U/PeripheralPins.c +++ b/variants/STM32C0xx/C071G(8-B)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C071G8Ux.xml, STM32C071GBUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071G(8-B)UxN/PeripheralPins.c b/variants/STM32C0xx/C071G(8-B)UxN/PeripheralPins.c index 11c592512d..bd5acd997c 100644 --- a/variants/STM32C0xx/C071G(8-B)UxN/PeripheralPins.c +++ b/variants/STM32C0xx/C071G(8-B)UxN/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C071G8UxN.xml, STM32C071GBUxN.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071K(8-B)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C071K(8-B)(T-U)/PeripheralPins.c index bcdc9affdf..b73510cfaf 100644 --- a/variants/STM32C0xx/C071K(8-B)(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C071K(8-B)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C071K8Tx.xml, STM32C071K8Ux.xml * STM32C071KBTx.xml, STM32C071KBUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071K(8-B)(T-U)xN/PeripheralPins.c b/variants/STM32C0xx/C071K(8-B)(T-U)xN/PeripheralPins.c index 92e27627ec..69924ede3b 100644 --- a/variants/STM32C0xx/C071K(8-B)(T-U)xN/PeripheralPins.c +++ b/variants/STM32C0xx/C071K(8-B)(T-U)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C071K8TxN.xml, STM32C071K8UxN.xml * STM32C071KBTxN.xml, STM32C071KBUxN.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071R(8-B)T/PeripheralPins.c b/variants/STM32C0xx/C071R(8-B)T/PeripheralPins.c index 93f05b37f3..62fc1420cc 100644 --- a/variants/STM32C0xx/C071R(8-B)T/PeripheralPins.c +++ b/variants/STM32C0xx/C071R(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C071R8Tx.xml, STM32C071RBTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C071R8TxN_C071RB(I-T)xN/PeripheralPins.c b/variants/STM32C0xx/C071R8TxN_C071RB(I-T)xN/PeripheralPins.c index eacd7e226c..f556bae274 100644 --- a/variants/STM32C0xx/C071R8TxN_C071RB(I-T)xN/PeripheralPins.c +++ b/variants/STM32C0xx/C071R8TxN_C071RB(I-T)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C071R8TxN.xml, STM32C071RBIxN.xml * STM32C071RBTxN.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C091C(B-C)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C091C(B-C)(T-U)/PeripheralPins.c index a765c764ec..a87340cf45 100644 --- a/variants/STM32C0xx/C091C(B-C)(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C091C(B-C)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C091CBTx.xml, STM32C091CBUx.xml * STM32C091CCTx.xml, STM32C091CCUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C091ECY_C091F(B-C)P/PeripheralPins.c b/variants/STM32C0xx/C091ECY_C091F(B-C)P/PeripheralPins.c index 234052e3b2..3ef3c0e140 100644 --- a/variants/STM32C0xx/C091ECY_C091F(B-C)P/PeripheralPins.c +++ b/variants/STM32C0xx/C091ECY_C091F(B-C)P/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C091ECYx.xml, STM32C091FBPx.xml * STM32C091FCPx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C091G(B-C)U/PeripheralPins.c b/variants/STM32C0xx/C091G(B-C)U/PeripheralPins.c index 8c0a86e0eb..5d4922f23d 100644 --- a/variants/STM32C0xx/C091G(B-C)U/PeripheralPins.c +++ b/variants/STM32C0xx/C091G(B-C)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C091GBUx.xml, STM32C091GCUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C091K(B-C)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C091K(B-C)(T-U)/PeripheralPins.c index fda363ef55..1423e3acfc 100644 --- a/variants/STM32C0xx/C091K(B-C)(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C091K(B-C)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C091KBTx.xml, STM32C091KBUx.xml * STM32C091KCTx.xml, STM32C091KCUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C091RBT_C091RC(I-T)/PeripheralPins.c b/variants/STM32C0xx/C091RBT_C091RC(I-T)/PeripheralPins.c index 1d3c0a47a1..88a2935aeb 100644 --- a/variants/STM32C0xx/C091RBT_C091RC(I-T)/PeripheralPins.c +++ b/variants/STM32C0xx/C091RBT_C091RC(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C091RBTx.xml, STM32C091RCIx.xml * STM32C091RCTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C092CBU_C092CC(T-U)/PeripheralPins.c b/variants/STM32C0xx/C092C(B-C)(T-U)/PeripheralPins.c similarity index 99% rename from variants/STM32C0xx/C092CBU_C092CC(T-U)/PeripheralPins.c rename to variants/STM32C0xx/C092C(B-C)(T-U)/PeripheralPins.c index df949e26ed..22161b8b85 100644 --- a/variants/STM32C0xx/C092CBU_C092CC(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C092C(B-C)(T-U)/PeripheralPins.c @@ -11,9 +11,9 @@ ******************************************************************************* */ /* - * Automatically generated from STM32C092CBUx.xml, STM32C092CCTx.xml - * STM32C092CCUx.xml - * CubeMX DB release 6.0.140 + * Automatically generated from STM32C092CBTx.xml, STM32C092CBUx.xml + * STM32C092CCTx.xml, STM32C092CCUx.xml + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C092CBU_C092CC(T-U)/PinNamesVar.h b/variants/STM32C0xx/C092C(B-C)(T-U)/PinNamesVar.h similarity index 100% rename from variants/STM32C0xx/C092CBU_C092CC(T-U)/PinNamesVar.h rename to variants/STM32C0xx/C092C(B-C)(T-U)/PinNamesVar.h diff --git a/variants/STM32C0xx/C092CBU_C092CC(T-U)/boards_entry.txt b/variants/STM32C0xx/C092C(B-C)(T-U)/boards_entry.txt similarity index 67% rename from variants/STM32C0xx/C092CBU_C092CC(T-U)/boards_entry.txt rename to variants/STM32C0xx/C092C(B-C)(T-U)/boards_entry.txt index ea08295a93..be4b46b45f 100644 --- a/variants/STM32C0xx/C092CBU_C092CC(T-U)/boards_entry.txt +++ b/variants/STM32C0xx/C092C(B-C)(T-U)/boards_entry.txt @@ -3,13 +3,22 @@ # and changed if needed. # See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 +# Generic C092CBTx +GenC0.menu.pnum.GENERIC_C092CBTX=Generic C092CBTx +GenC0.menu.pnum.GENERIC_C092CBTX.upload.maximum_size=131072 +GenC0.menu.pnum.GENERIC_C092CBTX.upload.maximum_data_size=30720 +GenC0.menu.pnum.GENERIC_C092CBTX.build.board=GENERIC_C092CBTX +GenC0.menu.pnum.GENERIC_C092CBTX.build.product_line=STM32C092xx +GenC0.menu.pnum.GENERIC_C092CBTX.build.variant=STM32C0xx/C092C(B-C)(T-U) +GenC0.menu.pnum.GENERIC_C092CBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd + # Generic C092CBUx GenC0.menu.pnum.GENERIC_C092CBUX=Generic C092CBUx GenC0.menu.pnum.GENERIC_C092CBUX.upload.maximum_size=131072 GenC0.menu.pnum.GENERIC_C092CBUX.upload.maximum_data_size=30720 GenC0.menu.pnum.GENERIC_C092CBUX.build.board=GENERIC_C092CBUX GenC0.menu.pnum.GENERIC_C092CBUX.build.product_line=STM32C092xx -GenC0.menu.pnum.GENERIC_C092CBUX.build.variant=STM32C0xx/C092CBU_C092CC(T-U) +GenC0.menu.pnum.GENERIC_C092CBUX.build.variant=STM32C0xx/C092C(B-C)(T-U) GenC0.menu.pnum.GENERIC_C092CBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd # Generic C092CCTx @@ -18,7 +27,7 @@ GenC0.menu.pnum.GENERIC_C092CCTX.upload.maximum_size=262144 GenC0.menu.pnum.GENERIC_C092CCTX.upload.maximum_data_size=30720 GenC0.menu.pnum.GENERIC_C092CCTX.build.board=GENERIC_C092CCTX GenC0.menu.pnum.GENERIC_C092CCTX.build.product_line=STM32C092xx -GenC0.menu.pnum.GENERIC_C092CCTX.build.variant=STM32C0xx/C092CBU_C092CC(T-U) +GenC0.menu.pnum.GENERIC_C092CCTX.build.variant=STM32C0xx/C092C(B-C)(T-U) GenC0.menu.pnum.GENERIC_C092CCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd # Generic C092CCUx @@ -27,6 +36,6 @@ GenC0.menu.pnum.GENERIC_C092CCUX.upload.maximum_size=262144 GenC0.menu.pnum.GENERIC_C092CCUX.upload.maximum_data_size=30720 GenC0.menu.pnum.GENERIC_C092CCUX.build.board=GENERIC_C092CCUX GenC0.menu.pnum.GENERIC_C092CCUX.build.product_line=STM32C092xx -GenC0.menu.pnum.GENERIC_C092CCUX.build.variant=STM32C0xx/C092CBU_C092CC(T-U) +GenC0.menu.pnum.GENERIC_C092CCUX.build.variant=STM32C0xx/C092C(B-C)(T-U) GenC0.menu.pnum.GENERIC_C092CCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd diff --git a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/generic_clock.c b/variants/STM32C0xx/C092C(B-C)(T-U)/generic_clock.c similarity index 95% rename from variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/generic_clock.c rename to variants/STM32C0xx/C092C(B-C)(T-U)/generic_clock.c index 3cf436e56f..acc8cb24e2 100644 --- a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/generic_clock.c +++ b/variants/STM32C0xx/C092C(B-C)(T-U)/generic_clock.c @@ -10,8 +10,8 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_C092CBTX) || defined(ARDUINO_GENERIC_C092RBTX) ||\ - defined(ARDUINO_GENERIC_C092RCIX) || defined(ARDUINO_GENERIC_C092RCTX) +#if defined(ARDUINO_GENERIC_C092CBTX) || defined(ARDUINO_GENERIC_C092CBUX) ||\ + defined(ARDUINO_GENERIC_C092CCTX) || defined(ARDUINO_GENERIC_C092CCUX) #include "pins_arduino.h" /** diff --git a/variants/STM32C0xx/C092C(B-C)(T-U)/ldscript.ld b/variants/STM32C0xx/C092C(B-C)(T-U)/ldscript.ld new file mode 100644 index 0000000000..d77bd287f3 --- /dev/null +++ b/variants/STM32C0xx/C092C(B-C)(T-U)/ldscript.ld @@ -0,0 +1,187 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32C092CCTx Device from STM32C0 series +** 256KBytes FLASH +** 30KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2025 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE + FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/variants/STM32C0xx/C092CBU_C092CC(T-U)/variant_generic.cpp b/variants/STM32C0xx/C092C(B-C)(T-U)/variant_generic.cpp similarity index 92% rename from variants/STM32C0xx/C092CBU_C092CC(T-U)/variant_generic.cpp rename to variants/STM32C0xx/C092C(B-C)(T-U)/variant_generic.cpp index cd8c37df88..22e883f504 100644 --- a/variants/STM32C0xx/C092CBU_C092CC(T-U)/variant_generic.cpp +++ b/variants/STM32C0xx/C092C(B-C)(T-U)/variant_generic.cpp @@ -10,8 +10,8 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_C092CBUX) || defined(ARDUINO_GENERIC_C092CCTX) ||\ - defined(ARDUINO_GENERIC_C092CCUX) +#if defined(ARDUINO_GENERIC_C092CBTX) || defined(ARDUINO_GENERIC_C092CBUX) ||\ + defined(ARDUINO_GENERIC_C092CCTX) || defined(ARDUINO_GENERIC_C092CCUX) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32C0xx/C092CBU_C092CC(T-U)/variant_generic.h b/variants/STM32C0xx/C092C(B-C)(T-U)/variant_generic.h similarity index 100% rename from variants/STM32C0xx/C092CBU_C092CC(T-U)/variant_generic.h rename to variants/STM32C0xx/C092C(B-C)(T-U)/variant_generic.h diff --git a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/CMakeLists.txt b/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/CMakeLists.txt deleted file mode 100644 index 52db19363f..0000000000 --- a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/CMakeLists.txt +++ /dev/null @@ -1,32 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp - variant_NUCLEO_C092RC.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32C0xx/C092CBU_C092CC(T-U)/CMakeLists.txt b/variants/STM32C0xx/C092CBU_C092CC(T-U)/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32C0xx/C092CBU_C092CC(T-U)/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32C0xx/C092ECY_C092F(B-C)P/PeripheralPins.c b/variants/STM32C0xx/C092ECY_C092F(B-C)P/PeripheralPins.c index 81d3f76eec..52e952b51e 100644 --- a/variants/STM32C0xx/C092ECY_C092F(B-C)P/PeripheralPins.c +++ b/variants/STM32C0xx/C092ECY_C092F(B-C)P/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C092ECYx.xml, STM32C092FBPx.xml * STM32C092FCPx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C092G(B-C)U/PeripheralPins.c b/variants/STM32C0xx/C092G(B-C)U/PeripheralPins.c index 614c319c59..6be37ac122 100644 --- a/variants/STM32C0xx/C092G(B-C)U/PeripheralPins.c +++ b/variants/STM32C0xx/C092G(B-C)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32C092GBUx.xml, STM32C092GCUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C092K(B-C)(T-U)/PeripheralPins.c b/variants/STM32C0xx/C092K(B-C)(T-U)/PeripheralPins.c index d8ed933af3..ccc5792afd 100644 --- a/variants/STM32C0xx/C092K(B-C)(T-U)/PeripheralPins.c +++ b/variants/STM32C0xx/C092K(B-C)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32C092KBTx.xml, STM32C092KBUx.xml * STM32C092KCTx.xml, STM32C092KCUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/PeripheralPins.c b/variants/STM32C0xx/C092RBT_C092RC(I-T)/PeripheralPins.c similarity index 99% rename from variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/PeripheralPins.c rename to variants/STM32C0xx/C092RBT_C092RC(I-T)/PeripheralPins.c index 20ae981fb6..8df79d39db 100644 --- a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/PeripheralPins.c +++ b/variants/STM32C0xx/C092RBT_C092RC(I-T)/PeripheralPins.c @@ -11,9 +11,9 @@ ******************************************************************************* */ /* - * Automatically generated from STM32C092CBTx.xml, STM32C092RBTx.xml - * STM32C092RCIx.xml, STM32C092RCTx.xml - * CubeMX DB release 6.0.140 + * Automatically generated from STM32C092RBTx.xml, STM32C092RCIx.xml + * STM32C092RCTx.xml + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/PinNamesVar.h b/variants/STM32C0xx/C092RBT_C092RC(I-T)/PinNamesVar.h similarity index 100% rename from variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/PinNamesVar.h rename to variants/STM32C0xx/C092RBT_C092RC(I-T)/PinNamesVar.h diff --git a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/boards_entry.txt b/variants/STM32C0xx/C092RBT_C092RC(I-T)/boards_entry.txt similarity index 66% rename from variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/boards_entry.txt rename to variants/STM32C0xx/C092RBT_C092RC(I-T)/boards_entry.txt index c043a2e699..51c82b8907 100644 --- a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/boards_entry.txt +++ b/variants/STM32C0xx/C092RBT_C092RC(I-T)/boards_entry.txt @@ -3,22 +3,13 @@ # and changed if needed. # See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 -# Generic C092CBTx -GenC0.menu.pnum.GENERIC_C092CBTX=Generic C092CBTx -GenC0.menu.pnum.GENERIC_C092CBTX.upload.maximum_size=131072 -GenC0.menu.pnum.GENERIC_C092CBTX.upload.maximum_data_size=30720 -GenC0.menu.pnum.GENERIC_C092CBTX.build.board=GENERIC_C092CBTX -GenC0.menu.pnum.GENERIC_C092CBTX.build.product_line=STM32C092xx -GenC0.menu.pnum.GENERIC_C092CBTX.build.variant=STM32C0xx/C092CBT_C092RBT_C092RC(I-T) -GenC0.menu.pnum.GENERIC_C092CBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd - # Generic C092RBTx GenC0.menu.pnum.GENERIC_C092RBTX=Generic C092RBTx GenC0.menu.pnum.GENERIC_C092RBTX.upload.maximum_size=131072 GenC0.menu.pnum.GENERIC_C092RBTX.upload.maximum_data_size=30720 GenC0.menu.pnum.GENERIC_C092RBTX.build.board=GENERIC_C092RBTX GenC0.menu.pnum.GENERIC_C092RBTX.build.product_line=STM32C092xx -GenC0.menu.pnum.GENERIC_C092RBTX.build.variant=STM32C0xx/C092CBT_C092RBT_C092RC(I-T) +GenC0.menu.pnum.GENERIC_C092RBTX.build.variant=STM32C0xx/C092RBT_C092RC(I-T) GenC0.menu.pnum.GENERIC_C092RBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd # Generic C092RCIx @@ -27,7 +18,7 @@ GenC0.menu.pnum.GENERIC_C092RCIX.upload.maximum_size=262144 GenC0.menu.pnum.GENERIC_C092RCIX.upload.maximum_data_size=30720 GenC0.menu.pnum.GENERIC_C092RCIX.build.board=GENERIC_C092RCIX GenC0.menu.pnum.GENERIC_C092RCIX.build.product_line=STM32C092xx -GenC0.menu.pnum.GENERIC_C092RCIX.build.variant=STM32C0xx/C092CBT_C092RBT_C092RC(I-T) +GenC0.menu.pnum.GENERIC_C092RCIX.build.variant=STM32C0xx/C092RBT_C092RC(I-T) GenC0.menu.pnum.GENERIC_C092RCIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd # Generic C092RCTx @@ -36,6 +27,6 @@ GenC0.menu.pnum.GENERIC_C092RCTX.upload.maximum_size=262144 GenC0.menu.pnum.GENERIC_C092RCTX.upload.maximum_data_size=30720 GenC0.menu.pnum.GENERIC_C092RCTX.build.board=GENERIC_C092RCTX GenC0.menu.pnum.GENERIC_C092RCTX.build.product_line=STM32C092xx -GenC0.menu.pnum.GENERIC_C092RCTX.build.variant=STM32C0xx/C092CBT_C092RBT_C092RC(I-T) +GenC0.menu.pnum.GENERIC_C092RCTX.build.variant=STM32C0xx/C092RBT_C092RC(I-T) GenC0.menu.pnum.GENERIC_C092RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd diff --git a/variants/STM32C0xx/C092RBT_C092RC(I-T)/generic_clock.c b/variants/STM32C0xx/C092RBT_C092RC(I-T)/generic_clock.c new file mode 100644 index 0000000000..c0f40abe42 --- /dev/null +++ b/variants/STM32C0xx/C092RBT_C092RC(I-T)/generic_clock.c @@ -0,0 +1,54 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_C092RBTX) || defined(ARDUINO_GENERIC_C092RCIX) ||\ + defined(ARDUINO_GENERIC_C092RCTX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + + __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_1); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { + Error_Handler(); + } +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/ldscript.ld b/variants/STM32C0xx/C092RBT_C092RC(I-T)/ldscript.ld similarity index 100% rename from variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/ldscript.ld rename to variants/STM32C0xx/C092RBT_C092RC(I-T)/ldscript.ld diff --git a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/variant_NUCLEO_C092RC.cpp b/variants/STM32C0xx/C092RBT_C092RC(I-T)/variant_NUCLEO_C092RC.cpp similarity index 100% rename from variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/variant_NUCLEO_C092RC.cpp rename to variants/STM32C0xx/C092RBT_C092RC(I-T)/variant_NUCLEO_C092RC.cpp diff --git a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/variant_NUCLEO_C092RC.h b/variants/STM32C0xx/C092RBT_C092RC(I-T)/variant_NUCLEO_C092RC.h similarity index 100% rename from variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/variant_NUCLEO_C092RC.h rename to variants/STM32C0xx/C092RBT_C092RC(I-T)/variant_NUCLEO_C092RC.h diff --git a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/variant_generic.cpp b/variants/STM32C0xx/C092RBT_C092RC(I-T)/variant_generic.cpp similarity index 93% rename from variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/variant_generic.cpp rename to variants/STM32C0xx/C092RBT_C092RC(I-T)/variant_generic.cpp index 63906e073c..a16beab4a4 100644 --- a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/variant_generic.cpp +++ b/variants/STM32C0xx/C092RBT_C092RC(I-T)/variant_generic.cpp @@ -10,8 +10,8 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_C092CBTX) || defined(ARDUINO_GENERIC_C092RBTX) ||\ - defined(ARDUINO_GENERIC_C092RCIX) || defined(ARDUINO_GENERIC_C092RCTX) +#if defined(ARDUINO_GENERIC_C092RBTX) || defined(ARDUINO_GENERIC_C092RCIX) ||\ + defined(ARDUINO_GENERIC_C092RCTX) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/variant_generic.h b/variants/STM32C0xx/C092RBT_C092RC(I-T)/variant_generic.h similarity index 100% rename from variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)/variant_generic.h rename to variants/STM32C0xx/C092RBT_C092RC(I-T)/variant_generic.h diff --git a/variants/STM32F0xx/F030C6T/PeripheralPins.c b/variants/STM32F0xx/F030C6T/PeripheralPins.c index 46787a4bf0..5243bb3b08 100644 --- a/variants/STM32F0xx/F030C6T/PeripheralPins.c +++ b/variants/STM32F0xx/F030C6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030C6Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030C8T/PeripheralPins.c b/variants/STM32F0xx/F030C8T/PeripheralPins.c index 414dad7a62..8cbc6b1c57 100644 --- a/variants/STM32F0xx/F030C8T/PeripheralPins.c +++ b/variants/STM32F0xx/F030C8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030C8Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030CCT/PeripheralPins.c b/variants/STM32F0xx/F030CCT/PeripheralPins.c index 1dd10d8de0..40ccfec454 100644 --- a/variants/STM32F0xx/F030CCT/PeripheralPins.c +++ b/variants/STM32F0xx/F030CCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030CCTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030F4P/PeripheralPins.c b/variants/STM32F0xx/F030F4P/PeripheralPins.c index 8b37a9f565..1ff47b8084 100644 --- a/variants/STM32F0xx/F030F4P/PeripheralPins.c +++ b/variants/STM32F0xx/F030F4P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030F4Px.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030K6T/PeripheralPins.c b/variants/STM32F0xx/F030K6T/PeripheralPins.c index b28711e7ce..92a245490a 100644 --- a/variants/STM32F0xx/F030K6T/PeripheralPins.c +++ b/variants/STM32F0xx/F030K6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030K6Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030R8T/PeripheralPins.c b/variants/STM32F0xx/F030R8T/PeripheralPins.c index 31b131fb68..5e0ee778bd 100644 --- a/variants/STM32F0xx/F030R8T/PeripheralPins.c +++ b/variants/STM32F0xx/F030R8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030R8Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F030RCT/PeripheralPins.c b/variants/STM32F0xx/F030RCT/PeripheralPins.c index 34e5aa7857..0406f9b409 100644 --- a/variants/STM32F0xx/F030RCT/PeripheralPins.c +++ b/variants/STM32F0xx/F030RCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F030RCTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031C(4-6)T/PeripheralPins.c b/variants/STM32F0xx/F031C(4-6)T/PeripheralPins.c index a44522d515..e8245d3b4e 100644 --- a/variants/STM32F0xx/F031C(4-6)T/PeripheralPins.c +++ b/variants/STM32F0xx/F031C(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031C(4-6)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031E6Y_F038E6Y/PeripheralPins.c b/variants/STM32F0xx/F031E6Y_F038E6Y/PeripheralPins.c index 30888677f7..d9a467b48d 100644 --- a/variants/STM32F0xx/F031E6Y_F038E6Y/PeripheralPins.c +++ b/variants/STM32F0xx/F031E6Y_F038E6Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031E6Yx.xml, STM32F038E6Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031F(4-6)P/PeripheralPins.c b/variants/STM32F0xx/F031F(4-6)P/PeripheralPins.c index 3b09065ad1..15dad46052 100644 --- a/variants/STM32F0xx/F031F(4-6)P/PeripheralPins.c +++ b/variants/STM32F0xx/F031F(4-6)P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031F(4-6)Px.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031G(4-6)U/PeripheralPins.c b/variants/STM32F0xx/F031G(4-6)U/PeripheralPins.c index 44cd46d725..d5b1d0e474 100644 --- a/variants/STM32F0xx/F031G(4-6)U/PeripheralPins.c +++ b/variants/STM32F0xx/F031G(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031G(4-6)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031K(4-6)U/PeripheralPins.c b/variants/STM32F0xx/F031K(4-6)U/PeripheralPins.c index 16783912d5..8222743793 100644 --- a/variants/STM32F0xx/F031K(4-6)U/PeripheralPins.c +++ b/variants/STM32F0xx/F031K(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031K(4-6)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F031K6T/PeripheralPins.c b/variants/STM32F0xx/F031K6T/PeripheralPins.c index b7dd7b226e..35d459fab8 100644 --- a/variants/STM32F0xx/F031K6T/PeripheralPins.c +++ b/variants/STM32F0xx/F031K6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F031K6Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F038C6T/PeripheralPins.c b/variants/STM32F0xx/F038C6T/PeripheralPins.c index 292c2e426b..45f4eb2428 100644 --- a/variants/STM32F0xx/F038C6T/PeripheralPins.c +++ b/variants/STM32F0xx/F038C6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F038C6Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F038F6P/PeripheralPins.c b/variants/STM32F0xx/F038F6P/PeripheralPins.c index 681bda7e50..16e7d86a09 100644 --- a/variants/STM32F0xx/F038F6P/PeripheralPins.c +++ b/variants/STM32F0xx/F038F6P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F038F6Px.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F038G6U/PeripheralPins.c b/variants/STM32F0xx/F038G6U/PeripheralPins.c index b0359efc91..f656b76a31 100644 --- a/variants/STM32F0xx/F038G6U/PeripheralPins.c +++ b/variants/STM32F0xx/F038G6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F038G6Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F038K6U/PeripheralPins.c b/variants/STM32F0xx/F038K6U/PeripheralPins.c index 365c02be8f..ff53442f61 100644 --- a/variants/STM32F0xx/F038K6U/PeripheralPins.c +++ b/variants/STM32F0xx/F038K6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F038K6Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042C(4-6)(T-U)/PeripheralPins.c b/variants/STM32F0xx/F042C(4-6)(T-U)/PeripheralPins.c index 0b871fb620..9f2821c9a8 100644 --- a/variants/STM32F0xx/F042C(4-6)(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F042C(4-6)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042C(4-6)Tx.xml, STM32F042C(4-6)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042F(4-6)P/PeripheralPins.c b/variants/STM32F0xx/F042F(4-6)P/PeripheralPins.c index d2b0eb56e1..55feb0e9a8 100644 --- a/variants/STM32F0xx/F042F(4-6)P/PeripheralPins.c +++ b/variants/STM32F0xx/F042F(4-6)P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042F4Px.xml, STM32F042F6Px.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042G(4-6)U/PeripheralPins.c b/variants/STM32F0xx/F042G(4-6)U/PeripheralPins.c index a7111e7697..ed641a0454 100644 --- a/variants/STM32F0xx/F042G(4-6)U/PeripheralPins.c +++ b/variants/STM32F0xx/F042G(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042G(4-6)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042K(4-6)T/PeripheralPins.c b/variants/STM32F0xx/F042K(4-6)T/PeripheralPins.c index ebf186e24e..0e68d7ef45 100644 --- a/variants/STM32F0xx/F042K(4-6)T/PeripheralPins.c +++ b/variants/STM32F0xx/F042K(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042K(4-6)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042K(4-6)U/PeripheralPins.c b/variants/STM32F0xx/F042K(4-6)U/PeripheralPins.c index e063551b5d..c2aaeaa321 100644 --- a/variants/STM32F0xx/F042K(4-6)U/PeripheralPins.c +++ b/variants/STM32F0xx/F042K(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042K(4-6)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F042T6Y/PeripheralPins.c b/variants/STM32F0xx/F042T6Y/PeripheralPins.c index 31713e2792..5d20af41ef 100644 --- a/variants/STM32F0xx/F042T6Y/PeripheralPins.c +++ b/variants/STM32F0xx/F042T6Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F042T6Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F048C6U/PeripheralPins.c b/variants/STM32F0xx/F048C6U/PeripheralPins.c index 229de8fb0f..ea94db04fd 100644 --- a/variants/STM32F0xx/F048C6U/PeripheralPins.c +++ b/variants/STM32F0xx/F048C6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F048C6Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F048G6U/PeripheralPins.c b/variants/STM32F0xx/F048G6U/PeripheralPins.c index 986da70c37..2bde04e22b 100644 --- a/variants/STM32F0xx/F048G6U/PeripheralPins.c +++ b/variants/STM32F0xx/F048G6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F048G6Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F048T6Y/PeripheralPins.c b/variants/STM32F0xx/F048T6Y/PeripheralPins.c index 357f0e6db3..82812d9159 100644 --- a/variants/STM32F0xx/F048T6Y/PeripheralPins.c +++ b/variants/STM32F0xx/F048T6Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F048T6Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051C4(T-U)/PeripheralPins.c b/variants/STM32F0xx/F051C4(T-U)/PeripheralPins.c index e0056a8433..bec0284887 100644 --- a/variants/STM32F0xx/F051C4(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F051C4(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051C4Tx.xml, STM32F051C4Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051C6(T-U)/PeripheralPins.c b/variants/STM32F0xx/F051C6(T-U)/PeripheralPins.c index 15f2f41858..81a8c9bde2 100644 --- a/variants/STM32F0xx/F051C6(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F051C6(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051C6Tx.xml, STM32F051C6Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051C8(T-U)/PeripheralPins.c b/variants/STM32F0xx/F051C8(T-U)/PeripheralPins.c index 35e6897446..7e4317edb2 100644 --- a/variants/STM32F0xx/F051C8(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F051C8(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051C8Tx.xml, STM32F051C8Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051K(6-8)T/PeripheralPins.c b/variants/STM32F0xx/F051K(6-8)T/PeripheralPins.c index 55932d6617..a0aa9db679 100644 --- a/variants/STM32F0xx/F051K(6-8)T/PeripheralPins.c +++ b/variants/STM32F0xx/F051K(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051K6Tx.xml, STM32F051K8Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051K(6-8)U/PeripheralPins.c b/variants/STM32F0xx/F051K(6-8)U/PeripheralPins.c index 04bef1ff10..2baa1423ae 100644 --- a/variants/STM32F0xx/F051K(6-8)U/PeripheralPins.c +++ b/variants/STM32F0xx/F051K(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051K6Ux.xml, STM32F051K8Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051K4T/PeripheralPins.c b/variants/STM32F0xx/F051K4T/PeripheralPins.c index 0c9bc2963a..3b4ca2e1f4 100644 --- a/variants/STM32F0xx/F051K4T/PeripheralPins.c +++ b/variants/STM32F0xx/F051K4T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051K4Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051K4U/PeripheralPins.c b/variants/STM32F0xx/F051K4U/PeripheralPins.c index bc5ef7c97d..7a5520d349 100644 --- a/variants/STM32F0xx/F051K4U/PeripheralPins.c +++ b/variants/STM32F0xx/F051K4U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051K4Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051R4T/PeripheralPins.c b/variants/STM32F0xx/F051R4T/PeripheralPins.c index e3b00e7a1b..73349a582d 100644 --- a/variants/STM32F0xx/F051R4T/PeripheralPins.c +++ b/variants/STM32F0xx/F051R4T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051R4Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051R6T/PeripheralPins.c b/variants/STM32F0xx/F051R6T/PeripheralPins.c index 61b6f16dbe..ebb661a8cb 100644 --- a/variants/STM32F0xx/F051R6T/PeripheralPins.c +++ b/variants/STM32F0xx/F051R6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051R6Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051R8(H-T)/PeripheralPins.c b/variants/STM32F0xx/F051R8(H-T)/PeripheralPins.c index efbe6c6926..43fd05f224 100644 --- a/variants/STM32F0xx/F051R8(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F051R8(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051R8Hx.xml, STM32F051R8Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F051T8Y/PeripheralPins.c b/variants/STM32F0xx/F051T8Y/PeripheralPins.c index 33325b3ff1..7aa5f53485 100644 --- a/variants/STM32F0xx/F051T8Y/PeripheralPins.c +++ b/variants/STM32F0xx/F051T8Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F051T8Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F058C8U/PeripheralPins.c b/variants/STM32F0xx/F058C8U/PeripheralPins.c index 4b032ef6eb..004c3e40e9 100644 --- a/variants/STM32F0xx/F058C8U/PeripheralPins.c +++ b/variants/STM32F0xx/F058C8U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F058C8Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F058R8(H-T)/PeripheralPins.c b/variants/STM32F0xx/F058R8(H-T)/PeripheralPins.c index d70fa47622..54b4d4f8b0 100644 --- a/variants/STM32F0xx/F058R8(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F058R8(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F058R8Hx.xml, STM32F058R8Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F058T8Y/PeripheralPins.c b/variants/STM32F0xx/F058T8Y/PeripheralPins.c index 6d634ab4c1..1c2bf2bf37 100644 --- a/variants/STM32F0xx/F058T8Y/PeripheralPins.c +++ b/variants/STM32F0xx/F058T8Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F058T8Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F070C6T/PeripheralPins.c b/variants/STM32F0xx/F070C6T/PeripheralPins.c index a38179fb7e..a30d1364bb 100644 --- a/variants/STM32F0xx/F070C6T/PeripheralPins.c +++ b/variants/STM32F0xx/F070C6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F070C6Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F070CBT/PeripheralPins.c b/variants/STM32F0xx/F070CBT/PeripheralPins.c index 83ff02f148..39f64d7220 100644 --- a/variants/STM32F0xx/F070CBT/PeripheralPins.c +++ b/variants/STM32F0xx/F070CBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F070CBTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F070F6P/PeripheralPins.c b/variants/STM32F0xx/F070F6P/PeripheralPins.c index c34a5ea22f..295d6b9e08 100644 --- a/variants/STM32F0xx/F070F6P/PeripheralPins.c +++ b/variants/STM32F0xx/F070F6P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F070F6Px.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F070RBT/PeripheralPins.c b/variants/STM32F0xx/F070RBT/PeripheralPins.c index e1c34774ab..505ba7bd1a 100644 --- a/variants/STM32F0xx/F070RBT/PeripheralPins.c +++ b/variants/STM32F0xx/F070RBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F070RBTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F071C8(T-U)_F071CB(T-U-Y)/PeripheralPins.c b/variants/STM32F0xx/F071C8(T-U)_F071CB(T-U-Y)/PeripheralPins.c index 33882e5a7e..b78e702edf 100644 --- a/variants/STM32F0xx/F071C8(T-U)_F071CB(T-U-Y)/PeripheralPins.c +++ b/variants/STM32F0xx/F071C8(T-U)_F071CB(T-U-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F071C(8-B)Tx.xml, STM32F071C(8-B)Ux.xml * STM32F071CBYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F071RBT/PeripheralPins.c b/variants/STM32F0xx/F071RBT/PeripheralPins.c index e66a578229..7e18091a5a 100644 --- a/variants/STM32F0xx/F071RBT/PeripheralPins.c +++ b/variants/STM32F0xx/F071RBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F071RBTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F071V(8-B)(H-T)/PeripheralPins.c b/variants/STM32F0xx/F071V(8-B)(H-T)/PeripheralPins.c index 167867814e..15d3a3fdda 100644 --- a/variants/STM32F0xx/F071V(8-B)(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F071V(8-B)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F071V(8-B)Hx.xml, STM32F071V(8-B)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F072C8(T-U)_F072CB(T-U-Y)/PeripheralPins.c b/variants/STM32F0xx/F072C8(T-U)_F072CB(T-U-Y)/PeripheralPins.c index cf49a5b8b6..b303a554ca 100644 --- a/variants/STM32F0xx/F072C8(T-U)_F072CB(T-U-Y)/PeripheralPins.c +++ b/variants/STM32F0xx/F072C8(T-U)_F072CB(T-U-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F072C(8-B)Tx.xml, STM32F072C(8-B)Ux.xml * STM32F072CBYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F072R8T_F072RB(H-I-T)/PeripheralPins.c b/variants/STM32F0xx/F072R8T_F072RB(H-I-T)/PeripheralPins.c index 9846a1b423..06cf228894 100644 --- a/variants/STM32F0xx/F072R8T_F072RB(H-I-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F072R8T_F072RB(H-I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F072R(8-B)Tx.xml, STM32F072RBHx.xml * STM32F072RBIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F072V(8-B)(H-T)/PeripheralPins.c b/variants/STM32F0xx/F072V(8-B)(H-T)/PeripheralPins.c index 0e37713c23..84c9fbb347 100644 --- a/variants/STM32F0xx/F072V(8-B)(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F072V(8-B)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F072V(8-B)Hx.xml, STM32F072V(8-B)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F078CB(T-U-Y)/PeripheralPins.c b/variants/STM32F0xx/F078CB(T-U-Y)/PeripheralPins.c index c48dcfbef7..3a251bb242 100644 --- a/variants/STM32F0xx/F078CB(T-U-Y)/PeripheralPins.c +++ b/variants/STM32F0xx/F078CB(T-U-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F078CBTx.xml, STM32F078CBUx.xml * STM32F078CBYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F078RB(H-T)/PeripheralPins.c b/variants/STM32F0xx/F078RB(H-T)/PeripheralPins.c index 026949b8b1..2e121a2fa4 100644 --- a/variants/STM32F0xx/F078RB(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F078RB(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F078RBHx.xml, STM32F078RBTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F078VB(H-T)/PeripheralPins.c b/variants/STM32F0xx/F078VB(H-T)/PeripheralPins.c index fe5f3afcb8..2cb99e2c8b 100644 --- a/variants/STM32F0xx/F078VB(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F078VB(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F078VBHx.xml, STM32F078VBTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F091C(B-C)(T-U)/PeripheralPins.c b/variants/STM32F0xx/F091C(B-C)(T-U)/PeripheralPins.c index 209bbb0a32..18b59ad1a0 100644 --- a/variants/STM32F0xx/F091C(B-C)(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F091C(B-C)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F091C(B-C)Tx.xml, STM32F091C(B-C)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F091RBT_F091RC(H-T-Y)/PeripheralPins.c b/variants/STM32F0xx/F091RBT_F091RC(H-T-Y)/PeripheralPins.c index 1f17236cac..e0c7711b19 100644 --- a/variants/STM32F0xx/F091RBT_F091RC(H-T-Y)/PeripheralPins.c +++ b/variants/STM32F0xx/F091RBT_F091RC(H-T-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F091R(B-C)Tx.xml, STM32F091RCHx.xml * STM32F091RCYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F091VBT_F091VC(H-T)/PeripheralPins.c b/variants/STM32F0xx/F091VBT_F091VC(H-T)/PeripheralPins.c index e0f7da8b7f..83e6ed008b 100644 --- a/variants/STM32F0xx/F091VBT_F091VC(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F091VBT_F091VC(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F091V(B-C)Tx.xml, STM32F091VCHx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F098CC(T-U)/PeripheralPins.c b/variants/STM32F0xx/F098CC(T-U)/PeripheralPins.c index 134904cac8..0a6da9a2c8 100644 --- a/variants/STM32F0xx/F098CC(T-U)/PeripheralPins.c +++ b/variants/STM32F0xx/F098CC(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F098CCTx.xml, STM32F098CCUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F098RC(H-T-Y)/PeripheralPins.c b/variants/STM32F0xx/F098RC(H-T-Y)/PeripheralPins.c index a862271b00..576019961a 100644 --- a/variants/STM32F0xx/F098RC(H-T-Y)/PeripheralPins.c +++ b/variants/STM32F0xx/F098RC(H-T-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F098RCHx.xml, STM32F098RCTx.xml * STM32F098RCYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F0xx/F098VC(H-T)/PeripheralPins.c b/variants/STM32F0xx/F098VC(H-T)/PeripheralPins.c index 662159fc67..48e1cc44d4 100644 --- a/variants/STM32F0xx/F098VC(H-T)/PeripheralPins.c +++ b/variants/STM32F0xx/F098VC(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F098VCHx.xml, STM32F098VCTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100C(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F100C(4-6)T/PeripheralPins.c index 49198d46a1..801a6078bd 100644 --- a/variants/STM32F1xx/F100C(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100C(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100C(4-6)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100C(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F100C(8-B)T/PeripheralPins.c index 377e7b2549..59c0156d02 100644 --- a/variants/STM32F1xx/F100C(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100C(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100C(8-B)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100R(4-6)H/PeripheralPins.c b/variants/STM32F1xx/F100R(4-6)H/PeripheralPins.c index 4f7f67e637..2b182e56f9 100644 --- a/variants/STM32F1xx/F100R(4-6)H/PeripheralPins.c +++ b/variants/STM32F1xx/F100R(4-6)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100R(4-6)Hx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100R(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F100R(4-6)T/PeripheralPins.c index 13724bdd5e..369df0c211 100644 --- a/variants/STM32F1xx/F100R(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100R(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100R(4-6)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100R(8-B)H/PeripheralPins.c b/variants/STM32F1xx/F100R(8-B)H/PeripheralPins.c index 62f436983e..b93a4612fb 100644 --- a/variants/STM32F1xx/F100R(8-B)H/PeripheralPins.c +++ b/variants/STM32F1xx/F100R(8-B)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100R(8-B)Hx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100R(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F100R(8-B)T/PeripheralPins.c index 9fef6c5a99..d7bf06ed5b 100644 --- a/variants/STM32F1xx/F100R(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100R(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100R(8-B)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100R(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F100R(C-D-E)T/PeripheralPins.c index b63dd31fcf..d27a7b7664 100644 --- a/variants/STM32F1xx/F100R(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100R(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100R(C-D-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100V(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F100V(8-B)T/PeripheralPins.c index 301d35de51..3e9c59d3eb 100644 --- a/variants/STM32F1xx/F100V(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100V(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100V(8-B)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100V(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F100V(C-D-E)T/PeripheralPins.c index 049d08ddaf..f3bb1a6d5c 100644 --- a/variants/STM32F1xx/F100V(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100V(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100V(C-D-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F100Z(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F100Z(C-D-E)T/PeripheralPins.c index d071670625..d738f25264 100644 --- a/variants/STM32F1xx/F100Z(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F100Z(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F100Z(C-D-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101C(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F101C(4-6)T/PeripheralPins.c index a038c4fb09..f0101192f5 100644 --- a/variants/STM32F1xx/F101C(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101C(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101C(4-6)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101C(8-B)(T-U)/PeripheralPins.c b/variants/STM32F1xx/F101C(8-B)(T-U)/PeripheralPins.c index 5b3da99ffa..e1435de9b6 100644 --- a/variants/STM32F1xx/F101C(8-B)(T-U)/PeripheralPins.c +++ b/variants/STM32F1xx/F101C(8-B)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101C(8-B)Tx.xml, STM32F101C(8-B)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101R(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F101R(4-6)T/PeripheralPins.c index 294822c545..0105d60ab1 100644 --- a/variants/STM32F1xx/F101R(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101R(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101R(4-6)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101R(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F101R(8-B)T/PeripheralPins.c index b4d968b0e1..a694516c47 100644 --- a/variants/STM32F1xx/F101R(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101R(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101R(8-B)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101R(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F101R(C-D-E)T/PeripheralPins.c index ac57e9773a..c4d0dba9a9 100644 --- a/variants/STM32F1xx/F101R(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101R(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101R(C-D-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101R(F-G)T/PeripheralPins.c b/variants/STM32F1xx/F101R(F-G)T/PeripheralPins.c index a097b5b619..f11476b36f 100644 --- a/variants/STM32F1xx/F101R(F-G)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101R(F-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101R(F-G)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101RBH/PeripheralPins.c b/variants/STM32F1xx/F101RBH/PeripheralPins.c index 9107b6cca2..45fe7f46bc 100644 --- a/variants/STM32F1xx/F101RBH/PeripheralPins.c +++ b/variants/STM32F1xx/F101RBH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101RBHx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101T(4-6)U/PeripheralPins.c b/variants/STM32F1xx/F101T(4-6)U/PeripheralPins.c index 664221498d..779da04e3e 100644 --- a/variants/STM32F1xx/F101T(4-6)U/PeripheralPins.c +++ b/variants/STM32F1xx/F101T(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101T(4-6)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101T(8-B)U/PeripheralPins.c b/variants/STM32F1xx/F101T(8-B)U/PeripheralPins.c index a1439fe9b7..a8354da5eb 100644 --- a/variants/STM32F1xx/F101T(8-B)U/PeripheralPins.c +++ b/variants/STM32F1xx/F101T(8-B)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101T(8-B)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101V(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F101V(8-B)T/PeripheralPins.c index 6ac3a3265d..c001e63aa9 100644 --- a/variants/STM32F1xx/F101V(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101V(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101V(8-B)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101V(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F101V(C-D-E)T/PeripheralPins.c index 076ffdef48..5c23052442 100644 --- a/variants/STM32F1xx/F101V(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101V(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101V(C-D-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101V(F-G)T/PeripheralPins.c b/variants/STM32F1xx/F101V(F-G)T/PeripheralPins.c index 90d2cf7532..ae0ba27977 100644 --- a/variants/STM32F1xx/F101V(F-G)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101V(F-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101V(F-G)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101Z(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F101Z(C-D-E)T/PeripheralPins.c index 93ad69fe96..6c57bf795b 100644 --- a/variants/STM32F1xx/F101Z(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101Z(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101Z(C-D-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F101Z(F-G)T/PeripheralPins.c b/variants/STM32F1xx/F101Z(F-G)T/PeripheralPins.c index 76ab29d7bc..ac713db7c8 100644 --- a/variants/STM32F1xx/F101Z(F-G)T/PeripheralPins.c +++ b/variants/STM32F1xx/F101Z(F-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F101Z(F-G)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F102C(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F102C(4-6)T/PeripheralPins.c index 2a85913a93..df045dbc6d 100644 --- a/variants/STM32F1xx/F102C(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F102C(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F102C(4-6)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F102C(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F102C(8-B)T/PeripheralPins.c index 655c6c14aa..84e94c0270 100644 --- a/variants/STM32F1xx/F102C(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F102C(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F102C(8-B)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F102R(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F102R(4-6)T/PeripheralPins.c index 73db80559d..dcdb313773 100644 --- a/variants/STM32F1xx/F102R(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F102R(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F102R(4-6)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F102R(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F102R(8-B)T/PeripheralPins.c index 2323a80880..20a8bec047 100644 --- a/variants/STM32F1xx/F102R(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F102R(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F102R(8-B)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103C4T_F103C6(T-U)/PeripheralPins.c b/variants/STM32F1xx/F103C4T_F103C6(T-U)/PeripheralPins.c index 589e46eada..5b68a95715 100644 --- a/variants/STM32F1xx/F103C4T_F103C6(T-U)/PeripheralPins.c +++ b/variants/STM32F1xx/F103C4T_F103C6(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103C(4-6)Tx.xml, STM32F103C6Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103C8T_F103CB(T-U)/PeripheralPins.c b/variants/STM32F1xx/F103C8T_F103CB(T-U)/PeripheralPins.c index f883b894a4..5d202f2ab8 100644 --- a/variants/STM32F1xx/F103C8T_F103CB(T-U)/PeripheralPins.c +++ b/variants/STM32F1xx/F103C8T_F103CB(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103C(8-B)Tx.xml, STM32F103CBUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(4-6)H/PeripheralPins.c b/variants/STM32F1xx/F103R(4-6)H/PeripheralPins.c index d99deb794b..563c688746 100644 --- a/variants/STM32F1xx/F103R(4-6)H/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(4-6)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(4-6)Hx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(4-6)T/PeripheralPins.c b/variants/STM32F1xx/F103R(4-6)T/PeripheralPins.c index 1381152315..55b5c0a7d1 100644 --- a/variants/STM32F1xx/F103R(4-6)T/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(4-6)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(4-6)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(8-B)H/PeripheralPins.c b/variants/STM32F1xx/F103R(8-B)H/PeripheralPins.c index 807f7659ae..772dc2d148 100644 --- a/variants/STM32F1xx/F103R(8-B)H/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(8-B)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(8-B)Hx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(8-B)T/PeripheralPins.c b/variants/STM32F1xx/F103R(8-B)T/PeripheralPins.c index 539785a4cc..c99d48193c 100644 --- a/variants/STM32F1xx/F103R(8-B)T/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(8-B)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(C-D-E)T/PeripheralPins.c b/variants/STM32F1xx/F103R(C-D-E)T/PeripheralPins.c index da22c27413..8a3e3146f2 100644 --- a/variants/STM32F1xx/F103R(C-D-E)T/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(C-D-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(C-D-E)Y/PeripheralPins.c b/variants/STM32F1xx/F103R(C-D-E)Y/PeripheralPins.c index 46b3451742..c90d406d6e 100644 --- a/variants/STM32F1xx/F103R(C-D-E)Y/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(C-D-E)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(C-D-E)Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103R(F-G)T/PeripheralPins.c b/variants/STM32F1xx/F103R(F-G)T/PeripheralPins.c index c15446b7fe..9ac16565c5 100644 --- a/variants/STM32F1xx/F103R(F-G)T/PeripheralPins.c +++ b/variants/STM32F1xx/F103R(F-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103R(F-G)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103T(4-6)U/PeripheralPins.c b/variants/STM32F1xx/F103T(4-6)U/PeripheralPins.c index efa902e8ce..3272c7253d 100644 --- a/variants/STM32F1xx/F103T(4-6)U/PeripheralPins.c +++ b/variants/STM32F1xx/F103T(4-6)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103T(4-6)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103T(8-B)U/PeripheralPins.c b/variants/STM32F1xx/F103T(8-B)U/PeripheralPins.c index 225f6a9c45..4062ef9da4 100644 --- a/variants/STM32F1xx/F103T(8-B)U/PeripheralPins.c +++ b/variants/STM32F1xx/F103T(8-B)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103T(8-B)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103V(C-D-E)(H-T)/PeripheralPins.c b/variants/STM32F1xx/F103V(C-D-E)(H-T)/PeripheralPins.c index 5f3e46c89d..5bcbf7aab3 100644 --- a/variants/STM32F1xx/F103V(C-D-E)(H-T)/PeripheralPins.c +++ b/variants/STM32F1xx/F103V(C-D-E)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103V(C-D-E)Hx.xml, STM32F103V(C-D-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103V(F-G)T/PeripheralPins.c b/variants/STM32F1xx/F103V(F-G)T/PeripheralPins.c index 43222abc6a..99bdc552af 100644 --- a/variants/STM32F1xx/F103V(F-G)T/PeripheralPins.c +++ b/variants/STM32F1xx/F103V(F-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103V(F-G)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103V8(H-T)_F103VB(H-I-T)/PeripheralPins.c b/variants/STM32F1xx/F103V8(H-T)_F103VB(H-I-T)/PeripheralPins.c index c60b7cd7eb..08367d39ca 100644 --- a/variants/STM32F1xx/F103V8(H-T)_F103VB(H-I-T)/PeripheralPins.c +++ b/variants/STM32F1xx/F103V8(H-T)_F103VB(H-I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F103V(8-B)Hx.xml, STM32F103V(8-B)Tx.xml * STM32F103VBIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103Z(C-D-E)(H-T)/PeripheralPins.c b/variants/STM32F1xx/F103Z(C-D-E)(H-T)/PeripheralPins.c index ec851c4051..0d61a9b59f 100644 --- a/variants/STM32F1xx/F103Z(C-D-E)(H-T)/PeripheralPins.c +++ b/variants/STM32F1xx/F103Z(C-D-E)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103Z(C-D-E)Hx.xml, STM32F103Z(C-D-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F103Z(F-G)(H-T)/PeripheralPins.c b/variants/STM32F1xx/F103Z(F-G)(H-T)/PeripheralPins.c index cad2a985ce..1741c3becb 100644 --- a/variants/STM32F1xx/F103Z(F-G)(H-T)/PeripheralPins.c +++ b/variants/STM32F1xx/F103Z(F-G)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F103Z(F-G)Hx.xml, STM32F103Z(F-G)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F105R(8-B-C)T/PeripheralPins.c b/variants/STM32F1xx/F105R(8-B-C)T/PeripheralPins.c index af95a0bea5..83872301b0 100644 --- a/variants/STM32F1xx/F105R(8-B-C)T/PeripheralPins.c +++ b/variants/STM32F1xx/F105R(8-B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F105R(8-B-C)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F105V(8-B)(H-T)_F105VCT/PeripheralPins.c b/variants/STM32F1xx/F105V(8-B)(H-T)_F105VCT/PeripheralPins.c index dee7710b3e..de01240921 100644 --- a/variants/STM32F1xx/F105V(8-B)(H-T)_F105VCT/PeripheralPins.c +++ b/variants/STM32F1xx/F105V(8-B)(H-T)_F105VCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F105V(8-B)Hx.xml, STM32F105V(8-B-C)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F107R(B-C)T/PeripheralPins.c b/variants/STM32F1xx/F107R(B-C)T/PeripheralPins.c index c6a965f5b4..027176a35a 100644 --- a/variants/STM32F1xx/F107R(B-C)T/PeripheralPins.c +++ b/variants/STM32F1xx/F107R(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F107R(B-C)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F1xx/F107VBT_F107VC(H-T)/PeripheralPins.c b/variants/STM32F1xx/F107VBT_F107VC(H-T)/PeripheralPins.c index 32e7aa2dca..7c45c15bbe 100644 --- a/variants/STM32F1xx/F107VBT_F107VC(H-T)/PeripheralPins.c +++ b/variants/STM32F1xx/F107VBT_F107VC(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F107V(B-C)Tx.xml, STM32F107VCHx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/PeripheralPins.c b/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/PeripheralPins.c index c848baa78a..0f44cbf1c9 100644 --- a/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/PeripheralPins.c +++ b/variants/STM32F2xx/F205RE(T-Y)_F205R(B-C-F)T_F205RG(E-T-Y)_F215R(E-G)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F205R(B-C-E-F-G)Tx.xml, STM32F205R(E-G)Yx.xml * STM32F205RGEx.xml, STM32F215R(E-G)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/PeripheralPins.c b/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/PeripheralPins.c index df7d89c285..b148be2395 100644 --- a/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/PeripheralPins.c +++ b/variants/STM32F2xx/F205V(B-C-E-F-G)T_F215V(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F205V(B-C-E-F-G)Tx.xml, STM32F215V(E-G)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/PeripheralPins.c b/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/PeripheralPins.c index d736a2c83f..e83da05a2e 100644 --- a/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/PeripheralPins.c +++ b/variants/STM32F2xx/F205Z(C-E-F-G)T_F215Z(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F205Z(C-E-F-G)Tx.xml, STM32F215Z(E-G)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/PeripheralPins.c b/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/PeripheralPins.c index 86d997fb82..fe0af84d59 100644 --- a/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/PeripheralPins.c +++ b/variants/STM32F2xx/F207I(C-E-F-G)(H-T)_F217I(E-G)(H-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F207I(C-E-F-G)Hx.xml, STM32F207I(C-E-F-G)Tx.xml * STM32F217I(E-G)Hx.xml, STM32F217I(E-G)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/PeripheralPins.c b/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/PeripheralPins.c index 33a72bbda4..40e8783eb3 100644 --- a/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/PeripheralPins.c +++ b/variants/STM32F2xx/F207V(C-E-F-G)T_F217V(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F207V(C-E-F-G)Tx.xml, STM32F217V(E-G)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F2xx/F207Z(C-E-F-G)T_F217Z(E-G)T/PeripheralPins.c b/variants/STM32F2xx/F207Z(C-E-F-G)T_F217Z(E-G)T/PeripheralPins.c index 7fa6bc014f..d7fd508d76 100644 --- a/variants/STM32F2xx/F207Z(C-E-F-G)T_F217Z(E-G)T/PeripheralPins.c +++ b/variants/STM32F2xx/F207Z(C-E-F-G)T_F217Z(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F207Z(C-E-F-G)Tx.xml, STM32F217Z(E-G)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F301C6T_F301C8(T-Y)/PeripheralPins.c b/variants/STM32F3xx/F301C6T_F301C8(T-Y)/PeripheralPins.c index a50abd1211..2c4126a6b8 100644 --- a/variants/STM32F3xx/F301C6T_F301C8(T-Y)/PeripheralPins.c +++ b/variants/STM32F3xx/F301C6T_F301C8(T-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F301C(6-8)Tx.xml, STM32F301C8Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F301K(6-8)T/PeripheralPins.c b/variants/STM32F3xx/F301K(6-8)T/PeripheralPins.c index 2f0badbed3..877d2625e3 100644 --- a/variants/STM32F3xx/F301K(6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F301K(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F301K(6-8)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F301K(6-8)U/PeripheralPins.c b/variants/STM32F3xx/F301K(6-8)U/PeripheralPins.c index e0bea1e64a..25a0fac064 100644 --- a/variants/STM32F3xx/F301K(6-8)U/PeripheralPins.c +++ b/variants/STM32F3xx/F301K(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F301K(6-8)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F301R(6-8)T/PeripheralPins.c b/variants/STM32F3xx/F301R(6-8)T/PeripheralPins.c index d285585d60..2bf3480ffb 100644 --- a/variants/STM32F3xx/F301R(6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F301R(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F301R(6-8)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302C(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F302C(B-C)T/PeripheralPins.c index a24c749cba..5684b7aec7 100644 --- a/variants/STM32F3xx/F302C(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302C(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302C(B-C)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302C6T_F302C8(T-Y)/PeripheralPins.c b/variants/STM32F3xx/F302C6T_F302C8(T-Y)/PeripheralPins.c index f764de52d7..3750ee4254 100644 --- a/variants/STM32F3xx/F302C6T_F302C8(T-Y)/PeripheralPins.c +++ b/variants/STM32F3xx/F302C6T_F302C8(T-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302C(6-8)Tx.xml, STM32F302C8Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302K(6-8)U/PeripheralPins.c b/variants/STM32F3xx/F302K(6-8)U/PeripheralPins.c index b5769c67f2..269d08b5f2 100644 --- a/variants/STM32F3xx/F302K(6-8)U/PeripheralPins.c +++ b/variants/STM32F3xx/F302K(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302K(6-8)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302R(6-8)T/PeripheralPins.c b/variants/STM32F3xx/F302R(6-8)T/PeripheralPins.c index 82df987ca6..3d38686536 100644 --- a/variants/STM32F3xx/F302R(6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302R(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302R(6-8)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302R(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F302R(B-C)T/PeripheralPins.c index 8623be0638..e9eacc45f2 100644 --- a/variants/STM32F3xx/F302R(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302R(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302R(B-C)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302R(D-E)T/PeripheralPins.c b/variants/STM32F3xx/F302R(D-E)T/PeripheralPins.c index 7465409a56..ff35ceb960 100644 --- a/variants/STM32F3xx/F302R(D-E)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302R(D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302R(D-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302V(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F302V(B-C)T/PeripheralPins.c index 50d95d07be..18725bc6d6 100644 --- a/variants/STM32F3xx/F302V(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302V(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302V(B-C)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302V(D-E)(H-T)/PeripheralPins.c b/variants/STM32F3xx/F302V(D-E)(H-T)/PeripheralPins.c index 7b519021cd..bbf138ba81 100644 --- a/variants/STM32F3xx/F302V(D-E)(H-T)/PeripheralPins.c +++ b/variants/STM32F3xx/F302V(D-E)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302V(D-E)Hx.xml, STM32F302V(D-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302VCY/PeripheralPins.c b/variants/STM32F3xx/F302VCY/PeripheralPins.c index dba9b11d6c..d72c5b4533 100644 --- a/variants/STM32F3xx/F302VCY/PeripheralPins.c +++ b/variants/STM32F3xx/F302VCY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302VCYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F302Z(D-E)T/PeripheralPins.c b/variants/STM32F3xx/F302Z(D-E)T/PeripheralPins.c index 8ece946a38..faef425c2e 100644 --- a/variants/STM32F3xx/F302Z(D-E)T/PeripheralPins.c +++ b/variants/STM32F3xx/F302Z(D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F302Z(D-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303C(6-8)T_F334C(4-6-8)T/PeripheralPins.c b/variants/STM32F3xx/F303C(6-8)T_F334C(4-6-8)T/PeripheralPins.c index 8e9d92a565..78e363d096 100644 --- a/variants/STM32F3xx/F303C(6-8)T_F334C(4-6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303C(6-8)T_F334C(4-6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303C(6-8)Tx.xml, STM32F334C(4-6-8)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303C(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F303C(B-C)T/PeripheralPins.c index 39afebf8e7..7fd7a8871d 100644 --- a/variants/STM32F3xx/F303C(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303C(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303C(B-C)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303C8Y_F334C8Y/PeripheralPins.c b/variants/STM32F3xx/F303C8Y_F334C8Y/PeripheralPins.c index c1449cecfa..ca08a5e524 100644 --- a/variants/STM32F3xx/F303C8Y_F334C8Y/PeripheralPins.c +++ b/variants/STM32F3xx/F303C8Y_F334C8Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303C8Yx.xml, STM32F334C8Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303K(6-8)T_F334K(4-6-8)T/PeripheralPins.c b/variants/STM32F3xx/F303K(6-8)T_F334K(4-6-8)T/PeripheralPins.c index 6b8b6fd0b8..b3033e10d7 100644 --- a/variants/STM32F3xx/F303K(6-8)T_F334K(4-6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303K(6-8)T_F334K(4-6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303K(6-8)Tx.xml, STM32F334K(4-6-8)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303K(6-8)U_F334K(4-6-8)U/PeripheralPins.c b/variants/STM32F3xx/F303K(6-8)U_F334K(4-6-8)U/PeripheralPins.c index f15a9ef19e..ffbf92db25 100644 --- a/variants/STM32F3xx/F303K(6-8)U_F334K(4-6-8)U/PeripheralPins.c +++ b/variants/STM32F3xx/F303K(6-8)U_F334K(4-6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303K(6-8)Ux.xml, STM32F334K(4-6-8)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303R(6-8)T_F334R(6-8)T/PeripheralPins.c b/variants/STM32F3xx/F303R(6-8)T_F334R(6-8)T/PeripheralPins.c index acd1e12dbb..ce542155e6 100644 --- a/variants/STM32F3xx/F303R(6-8)T_F334R(6-8)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303R(6-8)T_F334R(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303R(6-8)Tx.xml, STM32F334R(6-8)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303R(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F303R(B-C)T/PeripheralPins.c index 2957a88a53..1786cf9085 100644 --- a/variants/STM32F3xx/F303R(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303R(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303R(B-C)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303R(D-E)T/PeripheralPins.c b/variants/STM32F3xx/F303R(D-E)T/PeripheralPins.c index 10364c01c2..83cca59295 100644 --- a/variants/STM32F3xx/F303R(D-E)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303R(D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303R(D-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303V(B-C)T/PeripheralPins.c b/variants/STM32F3xx/F303V(B-C)T/PeripheralPins.c index 715a301b9d..e34d437efc 100644 --- a/variants/STM32F3xx/F303V(B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303V(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303V(B-C)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303V(D-E)(H-T)/PeripheralPins.c b/variants/STM32F3xx/F303V(D-E)(H-T)/PeripheralPins.c index c43dcf9ddc..9479126b48 100644 --- a/variants/STM32F3xx/F303V(D-E)(H-T)/PeripheralPins.c +++ b/variants/STM32F3xx/F303V(D-E)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303V(D-E)Hx.xml, STM32F303V(D-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303VCY/PeripheralPins.c b/variants/STM32F3xx/F303VCY/PeripheralPins.c index 7479ff2f0c..b144cb9cf0 100644 --- a/variants/STM32F3xx/F303VCY/PeripheralPins.c +++ b/variants/STM32F3xx/F303VCY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303VCYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303VEY/PeripheralPins.c b/variants/STM32F3xx/F303VEY/PeripheralPins.c index a3da5364e3..9f48a5626e 100644 --- a/variants/STM32F3xx/F303VEY/PeripheralPins.c +++ b/variants/STM32F3xx/F303VEY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303VEYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F303Z(D-E)T/PeripheralPins.c b/variants/STM32F3xx/F303Z(D-E)T/PeripheralPins.c index 01dc8d3d68..6f4abe0d24 100644 --- a/variants/STM32F3xx/F303Z(D-E)T/PeripheralPins.c +++ b/variants/STM32F3xx/F303Z(D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F303Z(D-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F318C8(T-Y)/PeripheralPins.c b/variants/STM32F3xx/F318C8(T-Y)/PeripheralPins.c index a884bb39bd..3ab760eead 100644 --- a/variants/STM32F3xx/F318C8(T-Y)/PeripheralPins.c +++ b/variants/STM32F3xx/F318C8(T-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F318C8Tx.xml, STM32F318C8Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F318K8U/PeripheralPins.c b/variants/STM32F3xx/F318K8U/PeripheralPins.c index 61543d32e9..9d973c8022 100644 --- a/variants/STM32F3xx/F318K8U/PeripheralPins.c +++ b/variants/STM32F3xx/F318K8U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F318K8Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F328C8T/PeripheralPins.c b/variants/STM32F3xx/F328C8T/PeripheralPins.c index 7719f6a677..3f68f8422c 100644 --- a/variants/STM32F3xx/F328C8T/PeripheralPins.c +++ b/variants/STM32F3xx/F328C8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F328C8Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F358CCT/PeripheralPins.c b/variants/STM32F3xx/F358CCT/PeripheralPins.c index 9e45de91e4..a87a9e937c 100644 --- a/variants/STM32F3xx/F358CCT/PeripheralPins.c +++ b/variants/STM32F3xx/F358CCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F358CCTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F358RCT/PeripheralPins.c b/variants/STM32F3xx/F358RCT/PeripheralPins.c index b42fc63e2f..3bb2190090 100644 --- a/variants/STM32F3xx/F358RCT/PeripheralPins.c +++ b/variants/STM32F3xx/F358RCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F358RCTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F358VCT/PeripheralPins.c b/variants/STM32F3xx/F358VCT/PeripheralPins.c index 2a0b84dc02..d0bbcd5a57 100644 --- a/variants/STM32F3xx/F358VCT/PeripheralPins.c +++ b/variants/STM32F3xx/F358VCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F358VCTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F373C(8-B-C)T/PeripheralPins.c b/variants/STM32F3xx/F373C(8-B-C)T/PeripheralPins.c index 1e5a460d44..75e50f354b 100644 --- a/variants/STM32F3xx/F373C(8-B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F373C(8-B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F373C(8-B-C)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F373R(8-B-C)T/PeripheralPins.c b/variants/STM32F3xx/F373R(8-B-C)T/PeripheralPins.c index 19be99be0d..fda621e983 100644 --- a/variants/STM32F3xx/F373R(8-B-C)T/PeripheralPins.c +++ b/variants/STM32F3xx/F373R(8-B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F373R(8-B-C)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F373V(8-B-C)(H-T)/PeripheralPins.c b/variants/STM32F3xx/F373V(8-B-C)(H-T)/PeripheralPins.c index d1fc6d23d5..a856e9a6fb 100644 --- a/variants/STM32F3xx/F373V(8-B-C)(H-T)/PeripheralPins.c +++ b/variants/STM32F3xx/F373V(8-B-C)(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F373V(8-B-C)Hx.xml, STM32F373V(8-B-C)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F378CCT/PeripheralPins.c b/variants/STM32F3xx/F378CCT/PeripheralPins.c index 01d38ffb0f..a7b8856364 100644 --- a/variants/STM32F3xx/F378CCT/PeripheralPins.c +++ b/variants/STM32F3xx/F378CCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F378CCTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F378RC(T-Y)/PeripheralPins.c b/variants/STM32F3xx/F378RC(T-Y)/PeripheralPins.c index 1f8841bf1d..97d28047a6 100644 --- a/variants/STM32F3xx/F378RC(T-Y)/PeripheralPins.c +++ b/variants/STM32F3xx/F378RC(T-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F378RCTx.xml, STM32F378RCYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F378VC(H-T)/PeripheralPins.c b/variants/STM32F3xx/F378VC(H-T)/PeripheralPins.c index 75666b05ca..44f89a930c 100644 --- a/variants/STM32F3xx/F378VC(H-T)/PeripheralPins.c +++ b/variants/STM32F3xx/F378VC(H-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F378VCHx.xml, STM32F378VCTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F3xx/F398VET/PeripheralPins.c b/variants/STM32F3xx/F398VET/PeripheralPins.c index 5bdc255148..26b9f66bfc 100644 --- a/variants/STM32F3xx/F398VET/PeripheralPins.c +++ b/variants/STM32F3xx/F398VET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F398VETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F401CC(F-U-Y)_F401C(B-D-E)(U-Y)/PeripheralPins.c b/variants/STM32F4xx/F401CC(F-U-Y)_F401C(B-D-E)(U-Y)/PeripheralPins.c index 12c4710f69..173681b6b4 100644 --- a/variants/STM32F4xx/F401CC(F-U-Y)_F401C(B-D-E)(U-Y)/PeripheralPins.c +++ b/variants/STM32F4xx/F401CC(F-U-Y)_F401C(B-D-E)(U-Y)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F401C(B-C)Ux.xml, STM32F401C(B-C)Yx.xml * STM32F401C(D-E)Ux.xml, STM32F401C(D-E)Yx.xml * STM32F401CCFx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F401R(B-C-D-E)T/PeripheralPins.c b/variants/STM32F4xx/F401R(B-C-D-E)T/PeripheralPins.c index f5baac63fc..5205a86bf0 100644 --- a/variants/STM32F4xx/F401R(B-C-D-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F401R(B-C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F401R(B-C)Tx.xml, STM32F401R(D-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F401V(B-C-D-E)H/PeripheralPins.c b/variants/STM32F4xx/F401V(B-C-D-E)H/PeripheralPins.c index 101519b794..12bc5267d0 100644 --- a/variants/STM32F4xx/F401V(B-C-D-E)H/PeripheralPins.c +++ b/variants/STM32F4xx/F401V(B-C-D-E)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F401V(B-C)Hx.xml, STM32F401V(D-E)Hx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F401V(B-C-D-E)T/PeripheralPins.c b/variants/STM32F4xx/F401V(B-C-D-E)T/PeripheralPins.c index 739b23864d..cff95ea93f 100644 --- a/variants/STM32F4xx/F401V(B-C-D-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F401V(B-C-D-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F401V(B-C)Tx.xml, STM32F401V(D-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F405O(E-G)Y_F415OGY/PeripheralPins.c b/variants/STM32F4xx/F405O(E-G)Y_F415OGY/PeripheralPins.c index 66da0ad7cb..47c56047f6 100644 --- a/variants/STM32F4xx/F405O(E-G)Y_F415OGY/PeripheralPins.c +++ b/variants/STM32F4xx/F405O(E-G)Y_F415OGY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F405O(E-G)Yx.xml, STM32F415OGYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F405RGT_F415RGT/PeripheralPins.c b/variants/STM32F4xx/F405RGT_F415RGT/PeripheralPins.c index 62507250af..1a5d60f7a5 100644 --- a/variants/STM32F4xx/F405RGT_F415RGT/PeripheralPins.c +++ b/variants/STM32F4xx/F405RGT_F415RGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F405RGTx.xml, STM32F415RGTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F405VGT_F415VGT/PeripheralPins.c b/variants/STM32F4xx/F405VGT_F415VGT/PeripheralPins.c index 029493293c..d1b4f6820d 100644 --- a/variants/STM32F4xx/F405VGT_F415VGT/PeripheralPins.c +++ b/variants/STM32F4xx/F405VGT_F415VGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F405VGTx.xml, STM32F415VGTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F405ZGT_F415ZGT/PeripheralPins.c b/variants/STM32F4xx/F405ZGT_F415ZGT/PeripheralPins.c index d59783e2fd..1384beacff 100644 --- a/variants/STM32F4xx/F405ZGT_F415ZGT/PeripheralPins.c +++ b/variants/STM32F4xx/F405ZGT_F415ZGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F405ZGTx.xml, STM32F415ZGTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F407I(E-G)(H-T)_F417I(E-G)(H-T)/PeripheralPins.c b/variants/STM32F4xx/F407I(E-G)(H-T)_F417I(E-G)(H-T)/PeripheralPins.c index 3d05cf31db..2427dd6df7 100644 --- a/variants/STM32F4xx/F407I(E-G)(H-T)_F417I(E-G)(H-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F407I(E-G)(H-T)_F417I(E-G)(H-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F407I(E-G)Hx.xml, STM32F407I(E-G)Tx.xml * STM32F417I(E-G)Hx.xml, STM32F417I(E-G)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PeripheralPins.c b/variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PeripheralPins.c index 6dd31351ce..966f1efc2f 100644 --- a/variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PeripheralPins.c +++ b/variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F407V(E-G)Tx.xml, STM32F417V(E-G)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F407Z(E-G)T_F417Z(E-G)T/PeripheralPins.c b/variants/STM32F4xx/F407Z(E-G)T_F417Z(E-G)T/PeripheralPins.c index 54a41b030e..9e4c3e3a6d 100644 --- a/variants/STM32F4xx/F407Z(E-G)T_F417Z(E-G)T/PeripheralPins.c +++ b/variants/STM32F4xx/F407Z(E-G)T_F417Z(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F407Z(E-G)Tx.xml, STM32F417Z(E-G)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F410C(8-B)T/PeripheralPins.c b/variants/STM32F4xx/F410C(8-B)T/PeripheralPins.c index 2f6bade20f..b9f665cbc8 100644 --- a/variants/STM32F4xx/F410C(8-B)T/PeripheralPins.c +++ b/variants/STM32F4xx/F410C(8-B)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F410C(8-B)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F410C(8-B)U/PeripheralPins.c b/variants/STM32F4xx/F410C(8-B)U/PeripheralPins.c index ef0aef8d28..2cb36cbc3a 100644 --- a/variants/STM32F4xx/F410C(8-B)U/PeripheralPins.c +++ b/variants/STM32F4xx/F410C(8-B)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F410C(8-B)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F410R(8-B)(I-T)/PeripheralPins.c b/variants/STM32F4xx/F410R(8-B)(I-T)/PeripheralPins.c index df1838dc29..8d842d72a5 100644 --- a/variants/STM32F4xx/F410R(8-B)(I-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F410R(8-B)(I-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F410R(8-B)Ix.xml, STM32F410R(8-B)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F410T(8-B)Y/PeripheralPins.c b/variants/STM32F4xx/F410T(8-B)Y/PeripheralPins.c index d7906aa815..5b7ab7c15a 100644 --- a/variants/STM32F4xx/F410T(8-B)Y/PeripheralPins.c +++ b/variants/STM32F4xx/F410T(8-B)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F410T(8-B)Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F411C(C-E)(U-Y)/PeripheralPins.c b/variants/STM32F4xx/F411C(C-E)(U-Y)/PeripheralPins.c index c9592bf411..f0a7ea4162 100644 --- a/variants/STM32F4xx/F411C(C-E)(U-Y)/PeripheralPins.c +++ b/variants/STM32F4xx/F411C(C-E)(U-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F411C(C-E)Ux.xml, STM32F411C(C-E)Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F411R(C-E)T/PeripheralPins.c b/variants/STM32F4xx/F411R(C-E)T/PeripheralPins.c index ec308f0b1d..60d1370858 100644 --- a/variants/STM32F4xx/F411R(C-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F411R(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F411R(C-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F411V(C-E)H/PeripheralPins.c b/variants/STM32F4xx/F411V(C-E)H/PeripheralPins.c index d7965b3ab3..5b0cddf3d9 100644 --- a/variants/STM32F4xx/F411V(C-E)H/PeripheralPins.c +++ b/variants/STM32F4xx/F411V(C-E)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F411V(C-E)Hx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F411V(C-E)T/PeripheralPins.c b/variants/STM32F4xx/F411V(C-E)T/PeripheralPins.c index 8aa4e47a58..4c1d011ae5 100644 --- a/variants/STM32F4xx/F411V(C-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F411V(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F411V(C-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F412C(E-G)U/PeripheralPins.c b/variants/STM32F4xx/F412C(E-G)U/PeripheralPins.c index 270fbdf7a2..7e4e9030e8 100644 --- a/variants/STM32F4xx/F412C(E-G)U/PeripheralPins.c +++ b/variants/STM32F4xx/F412C(E-G)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F412C(E-G)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F412R(E-G)(T-Y)x(P)/PeripheralPins.c b/variants/STM32F4xx/F412R(E-G)(T-Y)x(P)/PeripheralPins.c index 81bde3d210..8d5b6294cd 100644 --- a/variants/STM32F4xx/F412R(E-G)(T-Y)x(P)/PeripheralPins.c +++ b/variants/STM32F4xx/F412R(E-G)(T-Y)x(P)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F412R(E-G)Tx.xml, STM32F412R(E-G)Yx.xml * STM32F412R(E-G)YxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F412V(E-G)H/PeripheralPins.c b/variants/STM32F4xx/F412V(E-G)H/PeripheralPins.c index 9583578a30..57a710a0d6 100644 --- a/variants/STM32F4xx/F412V(E-G)H/PeripheralPins.c +++ b/variants/STM32F4xx/F412V(E-G)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F412V(E-G)Hx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F412V(E-G)T/PeripheralPins.c b/variants/STM32F4xx/F412V(E-G)T/PeripheralPins.c index 7a4f00b551..15c2100c4f 100644 --- a/variants/STM32F4xx/F412V(E-G)T/PeripheralPins.c +++ b/variants/STM32F4xx/F412V(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F412V(E-G)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F412Z(E-G)(J-T)/PeripheralPins.c b/variants/STM32F4xx/F412Z(E-G)(J-T)/PeripheralPins.c index 50095b4c38..15a12e4065 100644 --- a/variants/STM32F4xx/F412Z(E-G)(J-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F412Z(E-G)(J-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F412Z(E-G)Jx.xml, STM32F412Z(E-G)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413C(G-H)U_F423CHU/PeripheralPins.c b/variants/STM32F4xx/F413C(G-H)U_F423CHU/PeripheralPins.c index 7ed390670d..743109ca58 100644 --- a/variants/STM32F4xx/F413C(G-H)U_F423CHU/PeripheralPins.c +++ b/variants/STM32F4xx/F413C(G-H)U_F423CHU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F413C(G-H)Ux.xml, STM32F423CHUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413M(G-H)Y_F423MHY/PeripheralPins.c b/variants/STM32F4xx/F413M(G-H)Y_F423MHY/PeripheralPins.c index 43ff7ca7ac..4125133658 100644 --- a/variants/STM32F4xx/F413M(G-H)Y_F423MHY/PeripheralPins.c +++ b/variants/STM32F4xx/F413M(G-H)Y_F423MHY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F413M(G-H)Yx.xml, STM32F423MHYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413R(G-H)T_F423RHT/PeripheralPins.c b/variants/STM32F4xx/F413R(G-H)T_F423RHT/PeripheralPins.c index ab3606e672..eb8c561922 100644 --- a/variants/STM32F4xx/F413R(G-H)T_F423RHT/PeripheralPins.c +++ b/variants/STM32F4xx/F413R(G-H)T_F423RHT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F413R(G-H)Tx.xml, STM32F423RHTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413V(G-H)H_F423VHH/PeripheralPins.c b/variants/STM32F4xx/F413V(G-H)H_F423VHH/PeripheralPins.c index 703570a848..4ee0fee2c0 100644 --- a/variants/STM32F4xx/F413V(G-H)H_F423VHH/PeripheralPins.c +++ b/variants/STM32F4xx/F413V(G-H)H_F423VHH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F413V(G-H)Hx.xml, STM32F423VHHx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413V(G-H)T_F423VHT/PeripheralPins.c b/variants/STM32F4xx/F413V(G-H)T_F423VHT/PeripheralPins.c index cfa40c8081..5d4cc2a1f4 100644 --- a/variants/STM32F4xx/F413V(G-H)T_F423VHT/PeripheralPins.c +++ b/variants/STM32F4xx/F413V(G-H)T_F423VHT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F413V(G-H)Tx.xml, STM32F423VHTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F413Z(G-H)(J-T)_F423ZH(J-T)/PeripheralPins.c b/variants/STM32F4xx/F413Z(G-H)(J-T)_F423ZH(J-T)/PeripheralPins.c index 0a17d1d6a7..4af674e202 100644 --- a/variants/STM32F4xx/F413Z(G-H)(J-T)_F423ZH(J-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F413Z(G-H)(J-T)_F423ZH(J-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F413Z(G-H)Jx.xml, STM32F413Z(G-H)Tx.xml * STM32F423ZHJx.xml, STM32F423ZHTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F427A(G-I)H_F429A(G-I)H_F437AIH_F439AIH/PeripheralPins.c b/variants/STM32F4xx/F427A(G-I)H_F429A(G-I)H_F437AIH_F439AIH/PeripheralPins.c index a4ff23a69d..26162fb704 100644 --- a/variants/STM32F4xx/F427A(G-I)H_F429A(G-I)H_F437AIH_F439AIH/PeripheralPins.c +++ b/variants/STM32F4xx/F427A(G-I)H_F429A(G-I)H_F437AIH_F439AIH/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F427A(G-I)Hx.xml, STM32F429A(G-I)Hx.xml * STM32F437AIHx.xml, STM32F439AIHx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F427I(G-I)(H-T)_F429I(E-G-I)(H-T)_F437I(G-I)(H-T)_F439I(G-I)(H-T)/PeripheralPins.c b/variants/STM32F4xx/F427I(G-I)(H-T)_F429I(E-G-I)(H-T)_F437I(G-I)(H-T)_F439I(G-I)(H-T)/PeripheralPins.c index 32eb889f8e..d2d9d8bb43 100644 --- a/variants/STM32F4xx/F427I(G-I)(H-T)_F429I(E-G-I)(H-T)_F437I(G-I)(H-T)_F439I(G-I)(H-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F427I(G-I)(H-T)_F429I(E-G-I)(H-T)_F437I(G-I)(H-T)_F439I(G-I)(H-T)/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32F429IITx.xml, STM32F437I(G-I)Hx.xml * STM32F437I(G-I)Tx.xml, STM32F439I(G-I)Hx.xml * STM32F439I(G-I)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F427V(G-I)T_F429V(E-G-I)T_F437V(G-I)T_F439V(G-I)T/PeripheralPins.c b/variants/STM32F4xx/F427V(G-I)T_F429V(E-G-I)T_F437V(G-I)T_F439V(G-I)T/PeripheralPins.c index 6a543c9413..55215c308e 100644 --- a/variants/STM32F4xx/F427V(G-I)T_F429V(E-G-I)T_F437V(G-I)T_F439V(G-I)T/PeripheralPins.c +++ b/variants/STM32F4xx/F427V(G-I)T_F429V(E-G-I)T_F437V(G-I)T_F439V(G-I)T/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F427V(G-I)Tx.xml, STM32F429V(E-G)Tx.xml * STM32F429VITx.xml, STM32F437V(G-I)Tx.xml * STM32F439V(G-I)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/PeripheralPins.c b/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/PeripheralPins.c index 296710aee7..48aa67b703 100644 --- a/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/PeripheralPins.c +++ b/variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32F429ZGYx.xml, STM32F429ZITx.xml * STM32F429ZIYx.xml, STM32F437Z(G-I)Tx.xml * STM32F439Z(G-I)Tx.xml, STM32F439Z(G-I)Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F429B(E-G-I)T_F429N(E-G-I)H_F439B(G-I)T_F439N(G-I)H/PeripheralPins.c b/variants/STM32F4xx/F429B(E-G-I)T_F429N(E-G-I)H_F439B(G-I)T_F439N(G-I)H/PeripheralPins.c index 926224b509..69312baa8f 100644 --- a/variants/STM32F4xx/F429B(E-G-I)T_F429N(E-G-I)H_F439B(G-I)T_F439N(G-I)H/PeripheralPins.c +++ b/variants/STM32F4xx/F429B(E-G-I)T_F429N(E-G-I)H_F439B(G-I)T_F439N(G-I)H/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F429B(E-G-I)Tx.xml, STM32F429N(E-G)Hx.xml * STM32F429NIHx.xml, STM32F439B(G-I)Tx.xml * STM32F439N(G-I)Hx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F446M(C-E)Y/PeripheralPins.c b/variants/STM32F4xx/F446M(C-E)Y/PeripheralPins.c index 7ae100ebcd..187bd145be 100644 --- a/variants/STM32F4xx/F446M(C-E)Y/PeripheralPins.c +++ b/variants/STM32F4xx/F446M(C-E)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F446M(C-E)Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F446R(C-E)T/PeripheralPins.c b/variants/STM32F4xx/F446R(C-E)T/PeripheralPins.c index a6dfcc17cc..b9b2ce9e92 100644 --- a/variants/STM32F4xx/F446R(C-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F446R(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F446R(C-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F446V(C-E)T/PeripheralPins.c b/variants/STM32F4xx/F446V(C-E)T/PeripheralPins.c index da9632e108..3727f83f4f 100644 --- a/variants/STM32F4xx/F446V(C-E)T/PeripheralPins.c +++ b/variants/STM32F4xx/F446V(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F446V(C-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F446Z(C-E)(H-J-T)/PeripheralPins.c b/variants/STM32F4xx/F446Z(C-E)(H-J-T)/PeripheralPins.c index 48ce297d4f..56197a030b 100644 --- a/variants/STM32F4xx/F446Z(C-E)(H-J-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F446Z(C-E)(H-J-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F446Z(C-E)Hx.xml, STM32F446Z(C-E)Jx.xml * STM32F446Z(C-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F469A(E-G-I)(H-Y)_F479A(G-I)(H-Y)/PeripheralPins.c b/variants/STM32F4xx/F469A(E-G-I)(H-Y)_F479A(G-I)(H-Y)/PeripheralPins.c index 335d5e89fc..a257bb2a28 100644 --- a/variants/STM32F4xx/F469A(E-G-I)(H-Y)_F479A(G-I)(H-Y)/PeripheralPins.c +++ b/variants/STM32F4xx/F469A(E-G-I)(H-Y)_F479A(G-I)(H-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F469A(E-G-I)Hx.xml, STM32F469A(E-G-I)Yx.xml * STM32F479A(G-I)Hx.xml, STM32F479A(G-I)Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F469B(E-G-I)T_F469N(E-G-I)H_F479B(G-I)T_F479N(G-I)H/PeripheralPins.c b/variants/STM32F4xx/F469B(E-G-I)T_F469N(E-G-I)H_F479B(G-I)T_F479N(G-I)H/PeripheralPins.c index 5d9882a82f..0d7aaadb7f 100644 --- a/variants/STM32F4xx/F469B(E-G-I)T_F469N(E-G-I)H_F479B(G-I)T_F479N(G-I)H/PeripheralPins.c +++ b/variants/STM32F4xx/F469B(E-G-I)T_F469N(E-G-I)H_F479B(G-I)T_F479N(G-I)H/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F469B(E-G-I)Tx.xml, STM32F469N(E-G)Hx.xml * STM32F469NIHx.xml, STM32F479B(G-I)Tx.xml * STM32F479N(G-I)Hx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F469I(E-G-I)(H-T)_F479I(G-I)(H-T)/PeripheralPins.c b/variants/STM32F4xx/F469I(E-G-I)(H-T)_F479I(G-I)(H-T)/PeripheralPins.c index 7499d672a7..7fe377bbc1 100644 --- a/variants/STM32F4xx/F469I(E-G-I)(H-T)_F479I(G-I)(H-T)/PeripheralPins.c +++ b/variants/STM32F4xx/F469I(E-G-I)(H-T)_F479I(G-I)(H-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F469I(E-G)Tx.xml, STM32F469I(E-G-I)Hx.xml * STM32F469IITx.xml, STM32F479I(G-I)Hx.xml * STM32F479I(G-I)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F469V(E-G-I)T_F479V(G-I)T/PeripheralPins.c b/variants/STM32F4xx/F469V(E-G-I)T_F479V(G-I)T/PeripheralPins.c index 287d5f790c..2c3ca621e7 100644 --- a/variants/STM32F4xx/F469V(E-G-I)T_F479V(G-I)T/PeripheralPins.c +++ b/variants/STM32F4xx/F469V(E-G-I)T_F479V(G-I)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F469V(E-G)Tx.xml, STM32F469VITx.xml * STM32F479V(G-I)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F4xx/F469Z(E-G-I)T_F479Z(G-I)T/PeripheralPins.c b/variants/STM32F4xx/F469Z(E-G-I)T_F479Z(G-I)T/PeripheralPins.c index f13b3ee783..39ae484f58 100644 --- a/variants/STM32F4xx/F469Z(E-G-I)T_F479Z(G-I)T/PeripheralPins.c +++ b/variants/STM32F4xx/F469Z(E-G-I)T_F479Z(G-I)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F469Z(E-G)Tx.xml, STM32F469ZITx.xml * STM32F479Z(G-I)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F722I(C-E)(K-T)_F732IE(K-T)/PeripheralPins.c b/variants/STM32F7xx/F722I(C-E)(K-T)_F732IE(K-T)/PeripheralPins.c index 1a416c0743..6b168721e9 100644 --- a/variants/STM32F7xx/F722I(C-E)(K-T)_F732IE(K-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F722I(C-E)(K-T)_F732IE(K-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F722I(C-E)Kx.xml, STM32F722I(C-E)Tx.xml * STM32F732IEKx.xml, STM32F732IETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET/PeripheralPins.c b/variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET/PeripheralPins.c index 4c220132bf..965163f33e 100644 --- a/variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET/PeripheralPins.c +++ b/variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F722R(C-E)Tx.xml, STM32F730R8Tx.xml * STM32F732RETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F722V(C-E)T_F730V8T_F732VET/PeripheralPins.c b/variants/STM32F7xx/F722V(C-E)T_F730V8T_F732VET/PeripheralPins.c index 74b2c81b29..386ac98075 100644 --- a/variants/STM32F7xx/F722V(C-E)T_F730V8T_F732VET/PeripheralPins.c +++ b/variants/STM32F7xx/F722V(C-E)T_F730V8T_F732VET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F722V(C-E)Tx.xml, STM32F730V8Tx.xml * STM32F732VETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F722Z(C-E)T_F732ZET/PeripheralPins.c b/variants/STM32F7xx/F722Z(C-E)T_F732ZET/PeripheralPins.c index 921d0fd725..f13f8c2d01 100644 --- a/variants/STM32F7xx/F722Z(C-E)T_F732ZET/PeripheralPins.c +++ b/variants/STM32F7xx/F722Z(C-E)T_F732ZET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32F722Z(C-E)Tx.xml, STM32F732ZETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PeripheralPins.c b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PeripheralPins.c index 46be3ce18c..9a56c65e35 100644 --- a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F723I(C-E)Kx.xml, STM32F723I(C-E)Tx.xml * STM32F730I8Kx.xml, STM32F733IEKx.xml * STM32F733IETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PeripheralPins.c b/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PeripheralPins.c index 39427344a5..1bca09975b 100644 --- a/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PeripheralPins.c +++ b/variants/STM32F7xx/F723V(C-E)(T-Y)_F733VE(T-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F723V(C-E)Tx.xml, STM32F723V(C-E)Yx.xml * STM32F733VETx.xml, STM32F733VEYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PeripheralPins.c b/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PeripheralPins.c index 49d8b150a3..076dcee544 100644 --- a/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F723Z(C-E)(I-T)_F730Z8T_F733ZE(I-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F723Z(C-E)Ix.xml, STM32F723Z(C-E)Tx.xml * STM32F730Z8Tx.xml, STM32F733ZEIx.xml * STM32F733ZETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F745I(E-G)(K-T)_F746I(E-G)(K-T)_F756IG(K-T)/PeripheralPins.c b/variants/STM32F7xx/F745I(E-G)(K-T)_F746I(E-G)(K-T)_F756IG(K-T)/PeripheralPins.c index 63476a8932..d3497ba5ca 100644 --- a/variants/STM32F7xx/F745I(E-G)(K-T)_F746I(E-G)(K-T)_F756IG(K-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F745I(E-G)(K-T)_F746I(E-G)(K-T)_F756IG(K-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32F746I(E-G)Kx.xml, STM32F746IETx.xml * STM32F746IGTx.xml, STM32F756IGKx.xml * STM32F756IGTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F745V(E-G)(H-T)_F746V(E-G)(H-T)_F750V8T_F756VG(H-T)/PeripheralPins.c b/variants/STM32F7xx/F745V(E-G)(H-T)_F746V(E-G)(H-T)_F750V8T_F756VG(H-T)/PeripheralPins.c index 3385c27086..2fe7b671f6 100644 --- a/variants/STM32F7xx/F745V(E-G)(H-T)_F746V(E-G)(H-T)_F750V8T_F756VG(H-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F745V(E-G)(H-T)_F746V(E-G)(H-T)_F750V8T_F756VG(H-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32F746V(E-G)Hx.xml, STM32F746VETx.xml * STM32F746VGTx.xml, STM32F750V8Tx.xml * STM32F756VGHx.xml, STM32F756VGTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/PeripheralPins.c b/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/PeripheralPins.c index 9f5502477c..f8c50de40c 100644 --- a/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/PeripheralPins.c +++ b/variants/STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32F746ZETx.xml, STM32F746ZGTx.xml * STM32F750Z8Tx.xml, STM32F756ZGTx.xml * STM32F756ZGYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F746B(E-G)T_F746N(E-G)H_F750N8H_F756BGT_F756NGH/PeripheralPins.c b/variants/STM32F7xx/F746B(E-G)T_F746N(E-G)H_F750N8H_F756BGT_F756NGH/PeripheralPins.c index 69fd5a5901..9a805a6cc4 100644 --- a/variants/STM32F7xx/F746B(E-G)T_F746N(E-G)H_F750N8H_F756BGT_F756NGH/PeripheralPins.c +++ b/variants/STM32F7xx/F746B(E-G)T_F746N(E-G)H_F750N8H_F756BGT_F756NGH/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F746B(E-G)Tx.xml, STM32F746NEHx.xml * STM32F746NGHx.xml, STM32F750N8Hx.xml * STM32F756BGTx.xml, STM32F756NGHx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F765B(G-I)T_F765N(G-I)H_F767B(G-I)T_F767N(G-I)H_F777BIT_F777NIH/PeripheralPins.c b/variants/STM32F7xx/F765B(G-I)T_F765N(G-I)H_F767B(G-I)T_F767N(G-I)H_F777BIT_F777NIH/PeripheralPins.c index 466319f587..c309e66a38 100644 --- a/variants/STM32F7xx/F765B(G-I)T_F765N(G-I)H_F767B(G-I)T_F767N(G-I)H_F777BIT_F777NIH/PeripheralPins.c +++ b/variants/STM32F7xx/F765B(G-I)T_F765N(G-I)H_F767B(G-I)T_F767N(G-I)H_F777BIT_F777NIH/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F765B(G-I)Tx.xml, STM32F765N(G-I)Hx.xml * STM32F767B(G-I)Tx.xml, STM32F767N(G-I)Hx.xml * STM32F777BITx.xml, STM32F777NIHx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F765I(G-I)(K-T)_F767I(G-I)(K-T)_F777II(K-T)/PeripheralPins.c b/variants/STM32F7xx/F765I(G-I)(K-T)_F767I(G-I)(K-T)_F777II(K-T)/PeripheralPins.c index a290cd5245..c160fa9a3b 100644 --- a/variants/STM32F7xx/F765I(G-I)(K-T)_F767I(G-I)(K-T)_F777II(K-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F765I(G-I)(K-T)_F767I(G-I)(K-T)_F777II(K-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F765I(G-I)Kx.xml, STM32F765I(G-I)Tx.xml * STM32F767I(G-I)Kx.xml, STM32F767I(G-I)Tx.xml * STM32F777IIKx.xml, STM32F777IITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/PeripheralPins.c b/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/PeripheralPins.c index 225c0b265a..ee553c210a 100644 --- a/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/PeripheralPins.c +++ b/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32F767VGHx.xml, STM32F767VGTx.xml * STM32F767VIHx.xml, STM32F767VITx.xml * STM32F777VIHx.xml, STM32F777VITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/PeripheralPins.c b/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/PeripheralPins.c index 8fc7c583bd..e29e01d8e4 100644 --- a/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/PeripheralPins.c +++ b/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F765Z(G-I)Tx.xml, STM32F767ZGTx.xml * STM32F767ZITx.xml, STM32F777ZITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F768AIY_F769A(G-I)Y_F778AIY_F779AIY/PeripheralPins.c b/variants/STM32F7xx/F768AIY_F769A(G-I)Y_F778AIY_F779AIY/PeripheralPins.c index 499ab3272d..d3b6fb6c76 100644 --- a/variants/STM32F7xx/F768AIY_F769A(G-I)Y_F778AIY_F779AIY/PeripheralPins.c +++ b/variants/STM32F7xx/F768AIY_F769A(G-I)Y_F778AIY_F779AIY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F768AIYx.xml, STM32F769A(G-I)Yx.xml * STM32F778AIYx.xml, STM32F779AIYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F769B(G-I)T_F769N(G-I)H_F779BIT_F779NIH/PeripheralPins.c b/variants/STM32F7xx/F769B(G-I)T_F769N(G-I)H_F779BIT_F779NIH/PeripheralPins.c index 17e039b7eb..2440c4a270 100644 --- a/variants/STM32F7xx/F769B(G-I)T_F769N(G-I)H_F779BIT_F779NIH/PeripheralPins.c +++ b/variants/STM32F7xx/F769B(G-I)T_F769N(G-I)H_F779BIT_F779NIH/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32F769B(G-I)Tx.xml, STM32F769NGHx.xml * STM32F769NIHx.xml, STM32F779BITx.xml * STM32F779NIHx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32F7xx/F769I(G-I)T_F779IIT/PeripheralPins.c b/variants/STM32F7xx/F769I(G-I)T_F779IIT/PeripheralPins.c index d7c4b07ea3..c3762c1c03 100644 --- a/variants/STM32F7xx/F769I(G-I)T_F779IIT/PeripheralPins.c +++ b/variants/STM32F7xx/F769I(G-I)T_F779IIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32F769IGTx.xml, STM32F769IITx.xml * STM32F779IITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G030C(6-8)T/PeripheralPins.c b/variants/STM32G0xx/G030C(6-8)T/PeripheralPins.c index 248bfb870a..ea8d6799d1 100644 --- a/variants/STM32G0xx/G030C(6-8)T/PeripheralPins.c +++ b/variants/STM32G0xx/G030C(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G030C(6-8)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G030F6P/PeripheralPins.c b/variants/STM32G0xx/G030F6P/PeripheralPins.c index 694c7f5a37..318209221a 100644 --- a/variants/STM32G0xx/G030F6P/PeripheralPins.c +++ b/variants/STM32G0xx/G030F6P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G030F6Px.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G030J6M/PeripheralPins.c b/variants/STM32G0xx/G030J6M/PeripheralPins.c index 9dc3c520b5..0b8b02f5c3 100644 --- a/variants/STM32G0xx/G030J6M/PeripheralPins.c +++ b/variants/STM32G0xx/G030J6M/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G030J6Mx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G030K(6-8)T/PeripheralPins.c b/variants/STM32G0xx/G030K(6-8)T/PeripheralPins.c index b396e5e5ea..20e2933a39 100644 --- a/variants/STM32G0xx/G030K(6-8)T/PeripheralPins.c +++ b/variants/STM32G0xx/G030K(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G030K(6-8)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/PeripheralPins.c index dc605ced2d..6a1707ba59 100644 --- a/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G031C(4-6-8)Tx.xml, STM32G031C(4-6-8)Ux.xml * STM32G041C(6-8)Tx.xml, STM32G041C(6-8)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G031F(4-6-8)P_G031Y8Y_G041F(6-8)P_G041Y8Y/PeripheralPins.c b/variants/STM32G0xx/G031F(4-6-8)P_G031Y8Y_G041F(6-8)P_G041Y8Y/PeripheralPins.c index 21da9a3abb..76f0d63ce3 100644 --- a/variants/STM32G0xx/G031F(4-6-8)P_G031Y8Y_G041F(6-8)P_G041Y8Y/PeripheralPins.c +++ b/variants/STM32G0xx/G031F(4-6-8)P_G031Y8Y_G041F(6-8)P_G041Y8Y/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G031F(4-6-8)Px.xml, STM32G031Y8Yx.xml * STM32G041F(6-8)Px.xml, STM32G041Y8Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/PeripheralPins.c b/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/PeripheralPins.c index e4312f99c0..0c7faf17e3 100644 --- a/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/PeripheralPins.c +++ b/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G031G(4-6-8)Ux.xml, STM32G041G(6-8)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G031J(4-6)M_G041J6M/PeripheralPins.c b/variants/STM32G0xx/G031J(4-6)M_G041J6M/PeripheralPins.c index 181447c09b..01efd75e5d 100644 --- a/variants/STM32G0xx/G031J(4-6)M_G041J6M/PeripheralPins.c +++ b/variants/STM32G0xx/G031J(4-6)M_G041J6M/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G031J(4-6)Mx.xml, STM32G041J6Mx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G031K(4-6-8)(T-U)_G041K(6-8)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G031K(4-6-8)(T-U)_G041K(6-8)(T-U)/PeripheralPins.c index 3c1ae77039..65464d93b0 100644 --- a/variants/STM32G0xx/G031K(4-6-8)(T-U)_G041K(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G031K(4-6-8)(T-U)_G041K(6-8)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G031K(4-6-8)Tx.xml, STM32G031K(4-6-8)Ux.xml * STM32G041K(6-8)Tx.xml, STM32G041K(6-8)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G050C(6-8)T/PeripheralPins.c b/variants/STM32G0xx/G050C(6-8)T/PeripheralPins.c index 7f961a3ab5..f10bc7dd34 100644 --- a/variants/STM32G0xx/G050C(6-8)T/PeripheralPins.c +++ b/variants/STM32G0xx/G050C(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G050C6Tx.xml, STM32G050C8Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G050F6P/PeripheralPins.c b/variants/STM32G0xx/G050F6P/PeripheralPins.c index aec7d4e7d0..fdded4978f 100644 --- a/variants/STM32G0xx/G050F6P/PeripheralPins.c +++ b/variants/STM32G0xx/G050F6P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G050F6Px.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G050K(6-8)T/PeripheralPins.c b/variants/STM32G0xx/G050K(6-8)T/PeripheralPins.c index 31c85e0b64..a4969ffbbd 100644 --- a/variants/STM32G0xx/G050K(6-8)T/PeripheralPins.c +++ b/variants/STM32G0xx/G050K(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G050K6Tx.xml, STM32G050K8Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/PeripheralPins.c index 2e54e71b14..7897c87646 100644 --- a/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G051C(6-8)Tx.xml, STM32G051C(6-8)Ux.xml * STM32G061C(6-8)Tx.xml, STM32G061C(6-8)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/PeripheralPins.c b/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/PeripheralPins.c index fb655f10cf..2a37f4847e 100644 --- a/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/PeripheralPins.c +++ b/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G051F(6-8)Px.xml, STM32G051F8Yx.xml * STM32G061F(6-8)Px.xml, STM32G061F8Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/PeripheralPins.c b/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/PeripheralPins.c index 84e45400d2..5d45d3556a 100644 --- a/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/PeripheralPins.c +++ b/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G051G(6-8)Ux.xml, STM32G061G(6-8)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/PeripheralPins.c index d6448e25eb..393414a49a 100644 --- a/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G051K(6-8)Tx.xml, STM32G051K(6-8)Ux.xml * STM32G061K(6-8)Tx.xml, STM32G061K(6-8)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G070CBT/PeripheralPins.c b/variants/STM32G0xx/G070CBT/PeripheralPins.c index 2ec3627f08..0312fcde80 100644 --- a/variants/STM32G0xx/G070CBT/PeripheralPins.c +++ b/variants/STM32G0xx/G070CBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G070CBTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G070KBT/PeripheralPins.c b/variants/STM32G0xx/G070KBT/PeripheralPins.c index 1e7615fab9..a93c6943ea 100644 --- a/variants/STM32G0xx/G070KBT/PeripheralPins.c +++ b/variants/STM32G0xx/G070KBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G070KBTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G070RBT/PeripheralPins.c b/variants/STM32G0xx/G070RBT/PeripheralPins.c index d3f14d5c92..a19ffbf177 100644 --- a/variants/STM32G0xx/G070RBT/PeripheralPins.c +++ b/variants/STM32G0xx/G070RBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G070RBTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071C(6-8-B)(T-U)_G081CB(T-U)/PeripheralPins.c b/variants/STM32G0xx/G071C(6-8-B)(T-U)_G081CB(T-U)/PeripheralPins.c index e66f91eb11..ebd2b520e6 100644 --- a/variants/STM32G0xx/G071C(6-8-B)(T-U)_G081CB(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G071C(6-8-B)(T-U)_G081CB(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G071C(6-8-B)Tx.xml, STM32G071C(6-8-B)Ux.xml * STM32G081CBTx.xml, STM32G081CBUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071EBY_G081EBY/PeripheralPins.c b/variants/STM32G0xx/G071EBY_G081EBY/PeripheralPins.c index 937d69b911..5f8b244346 100644 --- a/variants/STM32G0xx/G071EBY_G081EBY/PeripheralPins.c +++ b/variants/STM32G0xx/G071EBY_G081EBY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G071EBYx.xml, STM32G081EBYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/PeripheralPins.c b/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/PeripheralPins.c index 80db7301a8..1402fa5c72 100644 --- a/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/PeripheralPins.c +++ b/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G071G(6-8-B)Ux.xml, STM32G081GBUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/PeripheralPins.c b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/PeripheralPins.c index e4ed94e9b2..4d833a3c5f 100644 --- a/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/PeripheralPins.c +++ b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G071G(8-B)UxN.xml, STM32G081GBUxN.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/PeripheralPins.c b/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/PeripheralPins.c index 8f502e5c9d..671fc46d89 100644 --- a/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G071K(6-8-B)Tx.xml, STM32G071K(6-8-B)Ux.xml * STM32G081KBTx.xml, STM32G081KBUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071K(8-B)(T-U)xN_G081KB(T-U)xN/PeripheralPins.c b/variants/STM32G0xx/G071K(8-B)(T-U)xN_G081KB(T-U)xN/PeripheralPins.c index 0730acfd6f..f04303dc80 100644 --- a/variants/STM32G0xx/G071K(8-B)(T-U)xN_G081KB(T-U)xN/PeripheralPins.c +++ b/variants/STM32G0xx/G071K(8-B)(T-U)xN_G081KB(T-U)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G071K(8-B)TxN.xml, STM32G071K(8-B)UxN.xml * STM32G081KBTxN.xml, STM32G081KBUxN.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)/PeripheralPins.c b/variants/STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)/PeripheralPins.c index d07cdef285..49820bc6b9 100644 --- a/variants/STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)/PeripheralPins.c +++ b/variants/STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G071R(6-8-B)Tx.xml, STM32G071RBIx.xml * STM32G081RBIx.xml, STM32G081RBTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B0CET/PeripheralPins.c b/variants/STM32G0xx/G0B0CET/PeripheralPins.c index 42071f3fbc..c936c98bb6 100644 --- a/variants/STM32G0xx/G0B0CET/PeripheralPins.c +++ b/variants/STM32G0xx/G0B0CET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B0CETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B0KET/PeripheralPins.c b/variants/STM32G0xx/G0B0KET/PeripheralPins.c index 46e9257272..74a275e827 100644 --- a/variants/STM32G0xx/G0B0KET/PeripheralPins.c +++ b/variants/STM32G0xx/G0B0KET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B0KETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B0RET/PeripheralPins.c b/variants/STM32G0xx/G0B0RET/PeripheralPins.c index 68620803cb..00d8de8c86 100644 --- a/variants/STM32G0xx/G0B0RET/PeripheralPins.c +++ b/variants/STM32G0xx/G0B0RET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B0RETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B0VET/PeripheralPins.c b/variants/STM32G0xx/G0B0VET/PeripheralPins.c index e2e00fe8a8..4e46a5f6e4 100644 --- a/variants/STM32G0xx/G0B0VET/PeripheralPins.c +++ b/variants/STM32G0xx/G0B0VET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B0VETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/PeripheralPins.c index b3db4b320a..09c1a302c2 100644 --- a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1C(B-C-E)Tx.xml, STM32G0B1C(B-C-E)Ux.xml * STM32G0C1C(C-E)Tx.xml, STM32G0C1C(C-E)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)xN_G0C1C(C-E)(T-U)xN/PeripheralPins.c b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)xN_G0C1C(C-E)(T-U)xN/PeripheralPins.c index 81a4a058f0..6ca27ced15 100644 --- a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)xN_G0C1C(C-E)(T-U)xN/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)xN_G0C1C(C-E)(T-U)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1C(B-C-E)TxN.xml, STM32G0B1C(B-C-E)UxN.xml * STM32G0C1C(C-E)TxN.xml, STM32G0C1C(C-E)UxN.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/PeripheralPins.c b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/PeripheralPins.c index 15bb2e97bb..b7317ad68c 100644 --- a/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1K(B-C-E)Tx.xml, STM32G0B1K(B-C-E)Ux.xml * STM32G0C1K(C-E)Tx.xml, STM32G0C1K(C-E)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1K(B-C-E)(T-U)xN_G0C1K(C-E)(T-U)xN/PeripheralPins.c b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)xN_G0C1K(C-E)(T-U)xN/PeripheralPins.c index b846df6c4a..76d43aa1f0 100644 --- a/variants/STM32G0xx/G0B1K(B-C-E)(T-U)xN_G0C1K(C-E)(T-U)xN/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)xN_G0C1K(C-E)(T-U)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1K(B-C-E)TxN.xml, STM32G0B1K(B-C-E)UxN.xml * STM32G0C1K(C-E)TxN.xml, STM32G0C1K(C-E)UxN.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/PeripheralPins.c b/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/PeripheralPins.c index d8a00dada5..a9cdf48d13 100644 --- a/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B1M(B-C-E)Tx.xml, STM32G0C1M(C-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1NEY_G0C1NEY/PeripheralPins.c b/variants/STM32G0xx/G0B1NEY_G0C1NEY/PeripheralPins.c index 1e6e284274..4939aeacf6 100644 --- a/variants/STM32G0xx/G0B1NEY_G0C1NEY/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1NEY_G0C1NEY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B1NEYx.xml, STM32G0C1NEYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1R(B-C-E)(I-T)xN_G0C1R(C-E)(I-T)xN/PeripheralPins.c b/variants/STM32G0xx/G0B1R(B-C-E)(I-T)xN_G0C1R(C-E)(I-T)xN/PeripheralPins.c index 75afe27b55..6dccea3e99 100644 --- a/variants/STM32G0xx/G0B1R(B-C-E)(I-T)xN_G0C1R(C-E)(I-T)xN/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1R(B-C-E)(I-T)xN_G0C1R(C-E)(I-T)xN/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1R(B-C-E)IxN.xml, STM32G0B1R(B-C-E)TxN.xml * STM32G0C1R(C-E)IxN.xml, STM32G0C1R(C-E)TxN.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/PeripheralPins.c b/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/PeripheralPins.c index 1f267c433a..93031dc6a2 100644 --- a/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G0B1R(B-C-E)Tx.xml, STM32G0C1R(C-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/PeripheralPins.c b/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/PeripheralPins.c index 4f16015722..5f9dcd6d1e 100644 --- a/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/PeripheralPins.c +++ b/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G0B1V(B-C-E)Ix.xml, STM32G0B1V(B-C-E)Tx.xml * STM32G0C1V(C-E)Ix.xml, STM32G0C1V(C-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G411C(6-8-B)T/PeripheralPins.c b/variants/STM32G4xx/G411C(6-8-B)T/PeripheralPins.c index 4b19c8142e..20dadb394d 100644 --- a/variants/STM32G4xx/G411C(6-8-B)T/PeripheralPins.c +++ b/variants/STM32G4xx/G411C(6-8-B)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G411C6Tx.xml, STM32G411C8Tx.xml * STM32G411CBTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G411C(6-8-B)U/PeripheralPins.c b/variants/STM32G4xx/G411C(6-8-B)U/PeripheralPins.c index 65b1d04f4f..f86274eaa6 100644 --- a/variants/STM32G4xx/G411C(6-8-B)U/PeripheralPins.c +++ b/variants/STM32G4xx/G411C(6-8-B)U/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G411C6Ux.xml, STM32G411C8Ux.xml * STM32G411CBUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G411CCT/PeripheralPins.c b/variants/STM32G4xx/G411CCT/PeripheralPins.c index 377e14c845..3e101109b5 100644 --- a/variants/STM32G4xx/G411CCT/PeripheralPins.c +++ b/variants/STM32G4xx/G411CCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G411CCTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G411CCU/PeripheralPins.c b/variants/STM32G4xx/G411CCU/PeripheralPins.c index c284259cf2..4a7d21765b 100644 --- a/variants/STM32G4xx/G411CCU/PeripheralPins.c +++ b/variants/STM32G4xx/G411CCU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G411CCUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G411K(6-8-B)(T-U)/PeripheralPins.c b/variants/STM32G4xx/G411K(6-8-B)(T-U)/PeripheralPins.c index ad506a3342..f1d32c705f 100644 --- a/variants/STM32G4xx/G411K(6-8-B)(T-U)/PeripheralPins.c +++ b/variants/STM32G4xx/G411K(6-8-B)(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32G411K6Tx.xml, STM32G411K6Ux.xml * STM32G411K8Tx.xml, STM32G411K8Ux.xml * STM32G411KBTx.xml, STM32G411KBUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G411M(6-8-B)T/PeripheralPins.c b/variants/STM32G4xx/G411M(6-8-B)T/PeripheralPins.c index 31fe4617bd..5367789c97 100644 --- a/variants/STM32G4xx/G411M(6-8-B)T/PeripheralPins.c +++ b/variants/STM32G4xx/G411M(6-8-B)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G411M6Tx.xml, STM32G411M8Tx.xml * STM32G411MBTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G411MCT/PeripheralPins.c b/variants/STM32G4xx/G411MCT/PeripheralPins.c index 68709552cc..8c515765cd 100644 --- a/variants/STM32G4xx/G411MCT/PeripheralPins.c +++ b/variants/STM32G4xx/G411MCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G411MCTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G411R(6-8-B)T/PeripheralPins.c b/variants/STM32G4xx/G411R(6-8-B)T/PeripheralPins.c index ce7c05b05e..42ac343f87 100644 --- a/variants/STM32G4xx/G411R(6-8-B)T/PeripheralPins.c +++ b/variants/STM32G4xx/G411R(6-8-B)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G411R6Tx.xml, STM32G411R8Tx.xml * STM32G411RBTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G411RCT/PeripheralPins.c b/variants/STM32G4xx/G411RCT/PeripheralPins.c index 239c44be33..9c772686f6 100644 --- a/variants/STM32G4xx/G411RCT/PeripheralPins.c +++ b/variants/STM32G4xx/G411RCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G411RCTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G414C(B-C)T/PeripheralPins.c b/variants/STM32G4xx/G414C(B-C)T/PeripheralPins.c index 5618f07d2f..a5e66e89c9 100644 --- a/variants/STM32G4xx/G414C(B-C)T/PeripheralPins.c +++ b/variants/STM32G4xx/G414C(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G414CBTx.xml, STM32G414CCTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G414C(B-C)U/PeripheralPins.c b/variants/STM32G4xx/G414C(B-C)U/PeripheralPins.c index e80d4673b6..df07d10986 100644 --- a/variants/STM32G4xx/G414C(B-C)U/PeripheralPins.c +++ b/variants/STM32G4xx/G414C(B-C)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G414CBUx.xml, STM32G414CCUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G414M(B-C)T/PeripheralPins.c b/variants/STM32G4xx/G414M(B-C)T/PeripheralPins.c index 29721ccb96..995ada5596 100644 --- a/variants/STM32G4xx/G414M(B-C)T/PeripheralPins.c +++ b/variants/STM32G4xx/G414M(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G414MBTx.xml, STM32G414MCTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G414R(B-C)T/PeripheralPins.c b/variants/STM32G4xx/G414R(B-C)T/PeripheralPins.c index 9e18088024..244b2f8cd3 100644 --- a/variants/STM32G4xx/G414R(B-C)T/PeripheralPins.c +++ b/variants/STM32G4xx/G414R(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G414RBTx.xml, STM32G414RCTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G414V(B-C)T/PeripheralPins.c b/variants/STM32G4xx/G414V(B-C)T/PeripheralPins.c index aa49869460..de03e85edd 100644 --- a/variants/STM32G4xx/G414V(B-C)T/PeripheralPins.c +++ b/variants/STM32G4xx/G414V(B-C)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G414VBTx.xml, STM32G414VCTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/PeripheralPins.c b/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/PeripheralPins.c index 630ebf2ef5..a6c8612bb7 100644 --- a/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/PeripheralPins.c +++ b/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G431C(6-8-B)Tx.xml, STM32G441CBTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/PeripheralPins.c b/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/PeripheralPins.c index 63125206c9..36981ace21 100644 --- a/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/PeripheralPins.c +++ b/variants/STM32G4xx/G431C(6-8-B)U_G441CBU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G431C(6-8-B)Ux.xml, STM32G441CBUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431CBTxZ/PeripheralPins.c b/variants/STM32G4xx/G431CBTxZ/PeripheralPins.c index 53e901ca0e..e49307e0d7 100644 --- a/variants/STM32G4xx/G431CBTxZ/PeripheralPins.c +++ b/variants/STM32G4xx/G431CBTxZ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G431CBTxZ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431CBY_G441CBY/PeripheralPins.c b/variants/STM32G4xx/G431CBY_G441CBY/PeripheralPins.c index 4994fefa13..65b7008327 100644 --- a/variants/STM32G4xx/G431CBY_G441CBY/PeripheralPins.c +++ b/variants/STM32G4xx/G431CBY_G441CBY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G431CBYx.xml, STM32G441CBYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/PeripheralPins.c b/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/PeripheralPins.c index 0edb6e1849..7f521ba7d2 100644 --- a/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/PeripheralPins.c +++ b/variants/STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G431K(6-8-B)Tx.xml, STM32G431K(6-8-B)Ux.xml * STM32G441KBTx.xml, STM32G441KBUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/PeripheralPins.c b/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/PeripheralPins.c index ea101fc6e1..288481ad3c 100644 --- a/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/PeripheralPins.c +++ b/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G431M(6-8-B)Tx.xml, STM32G441MBTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)/PeripheralPins.c b/variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)/PeripheralPins.c index 98fc6a40f6..284b801c81 100644 --- a/variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)/PeripheralPins.c +++ b/variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32G431R(6-8-B)Ix.xml, STM32G431R(6-8-B)Tx.xml * STM32G431RBTxZ.xml, STM32G441RBIx.xml * STM32G441RBTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/PeripheralPins.c b/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/PeripheralPins.c index 87c9abd8d5..fc1d9f35af 100644 --- a/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/PeripheralPins.c +++ b/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G431V(6-8-B)Tx.xml, STM32G441VBTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G471C(C-E)T/PeripheralPins.c b/variants/STM32G4xx/G471C(C-E)T/PeripheralPins.c index 8c8421d229..4fe35c8f99 100644 --- a/variants/STM32G4xx/G471C(C-E)T/PeripheralPins.c +++ b/variants/STM32G4xx/G471C(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G471C(C-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G471C(C-E)U/PeripheralPins.c b/variants/STM32G4xx/G471C(C-E)U/PeripheralPins.c index 0abdadadb4..a63f26ed26 100644 --- a/variants/STM32G4xx/G471C(C-E)U/PeripheralPins.c +++ b/variants/STM32G4xx/G471C(C-E)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G471C(C-E)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G471M(C-E)T/PeripheralPins.c b/variants/STM32G4xx/G471M(C-E)T/PeripheralPins.c index c0ffc57121..dfe5c12ffc 100644 --- a/variants/STM32G4xx/G471M(C-E)T/PeripheralPins.c +++ b/variants/STM32G4xx/G471M(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G471M(C-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G471MEY/PeripheralPins.c b/variants/STM32G4xx/G471MEY/PeripheralPins.c index c46eb9119a..36fdfb264d 100644 --- a/variants/STM32G4xx/G471MEY/PeripheralPins.c +++ b/variants/STM32G4xx/G471MEY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G471MEYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G471Q(C-E)T/PeripheralPins.c b/variants/STM32G4xx/G471Q(C-E)T/PeripheralPins.c index 49a35cd4e7..657d2970d4 100644 --- a/variants/STM32G4xx/G471Q(C-E)T/PeripheralPins.c +++ b/variants/STM32G4xx/G471Q(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G471Q(C-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G471R(C-E)T/PeripheralPins.c b/variants/STM32G4xx/G471R(C-E)T/PeripheralPins.c index 5ae6f1f801..891f154bb5 100644 --- a/variants/STM32G4xx/G471R(C-E)T/PeripheralPins.c +++ b/variants/STM32G4xx/G471R(C-E)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G471R(C-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G471V(C-E)(H-I-T)/PeripheralPins.c b/variants/STM32G4xx/G471V(C-E)(H-I-T)/PeripheralPins.c index e06863d648..afe2037210 100644 --- a/variants/STM32G4xx/G471V(C-E)(H-I-T)/PeripheralPins.c +++ b/variants/STM32G4xx/G471V(C-E)(H-I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G471V(C-E)Hx.xml, STM32G471V(C-E)Ix.xml * STM32G471V(C-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/PeripheralPins.c b/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/PeripheralPins.c index e2986831d7..ec43f3fa18 100644 --- a/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/PeripheralPins.c +++ b/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G473C(B-C-E)Tx.xml, STM32G474C(B-C-E)Tx.xml * STM32G483CETx.xml, STM32G484CETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/PeripheralPins.c b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/PeripheralPins.c index 2685c2c28a..436431c28b 100644 --- a/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/PeripheralPins.c +++ b/variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G473C(B-C-E)Ux.xml, STM32G474C(B-C-E)Ux.xml * STM32G483CEUx.xml, STM32G484CEUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/PeripheralPins.c b/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/PeripheralPins.c index 0eafed494a..fb84096147 100644 --- a/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/PeripheralPins.c +++ b/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G473M(B-C-E)Tx.xml, STM32G474M(B-C-E)Tx.xml * STM32G483METx.xml, STM32G484METx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473MEY_G474MEY_G483MEY_G484MEY/PeripheralPins.c b/variants/STM32G4xx/G473MEY_G474MEY_G483MEY_G484MEY/PeripheralPins.c index 677df1c3b8..65c74573e2 100644 --- a/variants/STM32G4xx/G473MEY_G474MEY_G483MEY_G484MEY/PeripheralPins.c +++ b/variants/STM32G4xx/G473MEY_G474MEY_G483MEY_G484MEY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G473MEYx.xml, STM32G474MEYx.xml * STM32G483MEYx.xml, STM32G484MEYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/PeripheralPins.c b/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/PeripheralPins.c index 4899458efb..0980a7bc41 100644 --- a/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/PeripheralPins.c +++ b/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G473P(B-C-E)Ix.xml, STM32G474P(B-C-E)Ix.xml * STM32G483PEIx.xml, STM32G484PEIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET/PeripheralPins.c b/variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET/PeripheralPins.c index 54193f3d04..1c05e5746b 100644 --- a/variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET/PeripheralPins.c +++ b/variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32G473Q(B-C-E)Tx.xml, STM32G473QETxZ.xml * STM32G474Q(B-C-E)Tx.xml, STM32G483QETx.xml * STM32G484QETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET/PeripheralPins.c b/variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET/PeripheralPins.c index de24b80fad..f61de4072e 100644 --- a/variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET/PeripheralPins.c +++ b/variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32G473R(B-C-E)Tx.xml, STM32G473RETxZ.xml * STM32G474R(B-C-E)Tx.xml, STM32G483RETx.xml * STM32G484RETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/PeripheralPins.c b/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/PeripheralPins.c index ca7f69eb66..34240fc285 100644 --- a/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/PeripheralPins.c +++ b/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32G474V(B-C-E)Hx.xml, STM32G474V(B-C-E)Tx.xml * STM32G483VEHx.xml, STM32G483VETx.xml * STM32G484VEHx.xml, STM32G484VETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491C(C-E)T_G4A1CET/PeripheralPins.c b/variants/STM32G4xx/G491C(C-E)T_G4A1CET/PeripheralPins.c index 140eea1124..0bb7330731 100644 --- a/variants/STM32G4xx/G491C(C-E)T_G4A1CET/PeripheralPins.c +++ b/variants/STM32G4xx/G491C(C-E)T_G4A1CET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G491C(C-E)Tx.xml, STM32G4A1CETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491C(C-E)U/PeripheralPins.c b/variants/STM32G4xx/G491C(C-E)U/PeripheralPins.c new file mode 100644 index 0000000000..c7afdc6302 --- /dev/null +++ b/variants/STM32G4xx/G491C(C-E)U/PeripheralPins.c @@ -0,0 +1,380 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32G491C(C-E)Ux.xml + * CubeMX DB release 6.0.150 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC2_IN17 + {PA_5, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 + {PA_6, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 + {PA_7, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PB_0_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PB_1_ALT1, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 + {PB_2, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 + {PB_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PB_11_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 + {PB_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PB_13, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5 + {PB_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PB_15, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 + {PC_4, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 + {PF_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PF_1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_8, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PA_14, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_5, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PC_11, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C3)}, + {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C3)}, + {PA_9, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PA_13, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PA_15, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PC_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 2, 0)}, // TIM15_CH2 + {PA_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 3, 0)}, // TIM2_CH3 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 0)}, // TIM1_CH3 + {PA_10_ALT1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 4, 0)}, // TIM2_CH4 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N + {PA_11_ALT1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 4, 0)}, // TIM1_CH4 + {PA_11_ALT2, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 1, 0)}, // TIM4_CH1 + {PA_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N + {PA_12_ALT1, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 2, 0)}, // TIM4_CH2 + {PA_12_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PA_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 3, 0)}, // TIM4_CH3 + {PA_13_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PA_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8, 2, 0)}, // TIM8_CH2 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_15_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM8, 1, 0)}, // TIM8_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, TIM20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM20, 1, 0)}, // TIM20_CH1 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_3_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_4_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N + {PB_4_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_5_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8, 1, 0)}, // TIM8_CH1 + {PB_6_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM3, 4, 0)}, // TIM3_CH4 + {PB_7_ALT1, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 2, 0)}, // TIM8_CH2 + {PB_8_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM1_COMP1, 3, 1)}, // TIM1_CH3N + {PB_9_ALT1, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 3, 0)}, // TIM8_CH3 + {PB_9_ALT3, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 1)}, // TIM15_CH1N + {PB_15_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15, 2, 0)}, // TIM15_CH2 + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 0)}, // TIM8_CH1 + {PC_10, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N + {PC_11, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N + {PC_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1, 1, 1)}, // TIM1_CH1N + {PC_13_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM8, 4, 1)}, // TIM8_CH4N + {PF_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)}, // TIM1_CH3N + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, + {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, + {PA_3_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, + {PB_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_14, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART4)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_11, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PF_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PF_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_5, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_6, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, FDCAN2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** QUADSPI *** + +#ifdef HAL_QSPI_MODULE_ENABLED +WEAK const PinMap PinMap_QUADSPI_DATA0[] = { + {PB_1, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI1_BK1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_QSPI_MODULE_ENABLED +WEAK const PinMap PinMap_QUADSPI_DATA1[] = { + {PB_0, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI1_BK1_IO1 + {PB_2, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI1_BK2_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_QSPI_MODULE_ENABLED +WEAK const PinMap PinMap_QUADSPI_DATA2[] = { + {PA_7, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI1_BK1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_QSPI_MODULE_ENABLED +WEAK const PinMap PinMap_QUADSPI_DATA3[] = { + {PA_6, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI1_BK1_IO3 + {PC_4, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI1_BK2_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_QSPI_MODULE_ENABLED +WEAK const PinMap PinMap_QUADSPI_SCLK[] = { + {PA_3, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI1_CLK + {PB_10, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_QSPI_MODULE_ENABLED +WEAK const PinMap PinMap_QUADSPI_SSEL[] = { + {PA_2, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI1_BK1_NCS + {PB_11, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI1_BK1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32G4xx/G491C(C-E)U/PinNamesVar.h b/variants/STM32G4xx/G491C(C-E)U/PinNamesVar.h new file mode 100644 index 0000000000..1b1ee448fe --- /dev/null +++ b/variants/STM32G4xx/G491C(C-E)U/PinNamesVar.h @@ -0,0 +1,77 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_7_ALT2 = PA_7 | ALT2, +PA_7_ALT3 = PA_7 | ALT3, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_11_ALT2 = PA_11 | ALT2, +PA_12_ALT1 = PA_12 | ALT1, +PA_12_ALT2 = PA_12 | ALT2, +PA_13_ALT1 = PA_13 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_4_ALT2 = PB_4 | ALT2, +PB_5_ALT1 = PB_5 | ALT1, +PB_5_ALT2 = PB_5 | ALT2, +PB_6_ALT1 = PB_6 | ALT1, +PB_6_ALT2 = PB_6 | ALT2, +PB_7_ALT1 = PB_7 | ALT1, +PB_7_ALT2 = PB_7 | ALT2, +PB_8_ALT1 = PB_8 | ALT1, +PB_8_ALT2 = PB_8 | ALT2, +PB_9_ALT1 = PB_9 | ALT1, +PB_9_ALT2 = PB_9 | ALT2, +PB_9_ALT3 = PB_9 | ALT3, +PB_11_ALT1 = PB_11 | ALT1, +PB_13_ALT1 = PB_13 | ALT1, +PB_14_ALT1 = PB_14 | ALT1, +PB_15_ALT1 = PB_15 | ALT1, +PB_15_ALT2 = PB_15 | ALT2, +PC_6_ALT1 = PC_6 | ALT1, +PC_10_ALT1 = PC_10 | ALT1, +PC_11_ALT1 = PC_11 | ALT1, +PC_13_ALT1 = PC_13 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = NC, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/boards_entry.txt b/variants/STM32G4xx/G491C(C-E)U/boards_entry.txt similarity index 69% rename from variants/STM32G4xx/G491C(C-E)U_G4A1CEU/boards_entry.txt rename to variants/STM32G4xx/G491C(C-E)U/boards_entry.txt index f650756e04..a8dd8c60c5 100644 --- a/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/boards_entry.txt +++ b/variants/STM32G4xx/G491C(C-E)U/boards_entry.txt @@ -9,7 +9,7 @@ GenG4.menu.pnum.GENERIC_G491CCUX.upload.maximum_size=262144 GenG4.menu.pnum.GENERIC_G491CCUX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G491CCUX.build.board=GENERIC_G491CCUX GenG4.menu.pnum.GENERIC_G491CCUX.build.product_line=STM32G491xx -GenG4.menu.pnum.GENERIC_G491CCUX.build.variant=STM32G4xx/G491C(C-E)U_G4A1CEU +GenG4.menu.pnum.GENERIC_G491CCUX.build.variant=STM32G4xx/G491C(C-E)U GenG4.menu.pnum.GENERIC_G491CCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G491.svd # Generic G491CEUx @@ -18,15 +18,6 @@ GenG4.menu.pnum.GENERIC_G491CEUX.upload.maximum_size=524288 GenG4.menu.pnum.GENERIC_G491CEUX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G491CEUX.build.board=GENERIC_G491CEUX GenG4.menu.pnum.GENERIC_G491CEUX.build.product_line=STM32G491xx -GenG4.menu.pnum.GENERIC_G491CEUX.build.variant=STM32G4xx/G491C(C-E)U_G4A1CEU +GenG4.menu.pnum.GENERIC_G491CEUX.build.variant=STM32G4xx/G491C(C-E)U GenG4.menu.pnum.GENERIC_G491CEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G491.svd -# Generic G4A1CEUx -GenG4.menu.pnum.GENERIC_G4A1CEUX=Generic G4A1CEUx -GenG4.menu.pnum.GENERIC_G4A1CEUX.upload.maximum_size=524288 -GenG4.menu.pnum.GENERIC_G4A1CEUX.upload.maximum_data_size=131072 -GenG4.menu.pnum.GENERIC_G4A1CEUX.build.board=GENERIC_G4A1CEUX -GenG4.menu.pnum.GENERIC_G4A1CEUX.build.product_line=STM32G4A1xx -GenG4.menu.pnum.GENERIC_G4A1CEUX.build.variant=STM32G4xx/G491C(C-E)U_G4A1CEU -GenG4.menu.pnum.GENERIC_G4A1CEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G4A1.svd - diff --git a/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/generic_clock.c b/variants/STM32G4xx/G491C(C-E)U/generic_clock.c similarity index 89% rename from variants/STM32G4xx/G491C(C-E)U_G4A1CEU/generic_clock.c rename to variants/STM32G4xx/G491C(C-E)U/generic_clock.c index 614170bda3..1e1fa9a114 100644 --- a/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/generic_clock.c +++ b/variants/STM32G4xx/G491C(C-E)U/generic_clock.c @@ -1,6 +1,6 @@ /* ******************************************************************************* - * Copyright (c) 2020-2021, STMicroelectronics + * Copyright (c) 2020, STMicroelectronics * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_G491CCUX) || defined(ARDUINO_GENERIC_G491CEUX) ||\ - defined(ARDUINO_GENERIC_G4A1CEUX) +#if defined(ARDUINO_GENERIC_G491CCUX) || defined(ARDUINO_GENERIC_G491CEUX) #include "pins_arduino.h" /** diff --git a/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/variant_generic.cpp b/variants/STM32G4xx/G491C(C-E)U/variant_generic.cpp similarity index 97% rename from variants/STM32G4xx/G491C(C-E)U_G4A1CEU/variant_generic.cpp rename to variants/STM32G4xx/G491C(C-E)U/variant_generic.cpp index 3a70218ef3..19d477c542 100644 --- a/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/variant_generic.cpp +++ b/variants/STM32G4xx/G491C(C-E)U/variant_generic.cpp @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_G491CCUX) || defined(ARDUINO_GENERIC_G491CEUX) ||\ - defined(ARDUINO_GENERIC_G4A1CEUX) +#if defined(ARDUINO_GENERIC_G491CCUX) || defined(ARDUINO_GENERIC_G491CEUX) #include "pins_arduino.h" // Digital PinName array diff --git a/variants/STM32G4xx/G491C(C-E)U/variant_generic.h b/variants/STM32G4xx/G491C(C-E)U/variant_generic.h new file mode 100644 index 0000000000..f8efdab0ab --- /dev/null +++ b/variants/STM32G4xx/G491C(C-E)U/variant_generic.h @@ -0,0 +1,208 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 PIN_A10 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 PIN_A11 +#define PB12 PIN_A12 +#define PB13 PIN_A13 +#define PB14 PIN_A14 +#define PB15 PIN_A15 +#define PC4 PIN_A16 +#define PC6 33 +#define PC10 34 +#define PC11 35 +#define PC13 36 +#define PC14 37 +#define PC15 38 +#define PF0 PIN_A17 +#define PF1 PIN_A18 +#define PG10 41 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA11_ALT2 (PA11 | ALT2) +#define PA12_ALT1 (PA12 | ALT1) +#define PA12_ALT2 (PA12 | ALT2) +#define PA13_ALT1 (PA13 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB4_ALT2 (PB4 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB5_ALT2 (PB5 | ALT2) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB7_ALT2 (PB7 | ALT2) +#define PB8_ALT1 (PB8 | ALT1) +#define PB8_ALT2 (PB8 | ALT2) +#define PB9_ALT1 (PB9 | ALT1) +#define PB9_ALT2 (PB9 | ALT2) +#define PB9_ALT3 (PB9 | ALT3) +#define PB11_ALT1 (PB11 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC6_ALT1 (PC6 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) +#define PC13_ALT1 (PC13 | ALT1) + +#define NUM_DIGITAL_PINS 42 +#define NUM_ANALOG_INPUTS 19 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA8 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA9 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 101 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA3 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA2 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_QSPI_MODULE_DISABLED) + #define HAL_QSPI_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/CMakeLists.txt b/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/CMakeLists.txt deleted file mode 100644 index 2a4d55b6b1..0000000000 --- a/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# v3.21 implemented semantic changes regarding $ -# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects -cmake_minimum_required(VERSION 3.21) - -add_library(variant INTERFACE) -add_library(variant_usage INTERFACE) - -target_include_directories(variant_usage INTERFACE - . -) - - -target_link_libraries(variant_usage INTERFACE - base_config -) - -target_link_libraries(variant INTERFACE variant_usage) - - - -add_library(variant_bin STATIC EXCLUDE_FROM_ALL - generic_clock.c - PeripheralPins.c - variant_generic.cpp -) -target_link_libraries(variant_bin PUBLIC variant_usage) - -target_link_libraries(variant INTERFACE - variant_bin -) - diff --git a/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/PeripheralPins.c b/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/PeripheralPins.c index d07db6d692..a9de59354c 100644 --- a/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/PeripheralPins.c +++ b/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G491K(C-E)Ux.xml, STM32G4A1KEUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/PeripheralPins.c b/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/PeripheralPins.c index 6f0f73d7d0..6f9904b813 100644 --- a/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/PeripheralPins.c +++ b/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32G491M(C-E)Sx.xml, STM32G491M(C-E)Tx.xml * STM32G4A1MESx.xml, STM32G4A1METx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)/PeripheralPins.c b/variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)/PeripheralPins.c index e15fb4f78f..0d8ebd1d65 100644 --- a/variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)/PeripheralPins.c +++ b/variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32G491RETxZ.xml, STM32G491REYx.xml * STM32G4A1REIx.xml, STM32G4A1RETx.xml * STM32G4A1REYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491V(C-E)T_G4A1VET/PeripheralPins.c b/variants/STM32G4xx/G491V(C-E)T_G4A1VET/PeripheralPins.c index 96f20b84f9..fb6b0cc907 100644 --- a/variants/STM32G4xx/G491V(C-E)T_G4A1VET/PeripheralPins.c +++ b/variants/STM32G4xx/G491V(C-E)T_G4A1VET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32G491V(C-E)Tx.xml, STM32G4A1VETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/PeripheralPins.c b/variants/STM32G4xx/G4A1CEU/PeripheralPins.c similarity index 99% rename from variants/STM32G4xx/G491C(C-E)U_G4A1CEU/PeripheralPins.c rename to variants/STM32G4xx/G4A1CEU/PeripheralPins.c index 0fbdbd7bcf..92d44f7e42 100644 --- a/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/PeripheralPins.c +++ b/variants/STM32G4xx/G4A1CEU/PeripheralPins.c @@ -11,8 +11,8 @@ ******************************************************************************* */ /* - * Automatically generated from STM32G491C(C-E)Ux.xml, STM32G4A1CEUx.xml - * CubeMX DB release 6.0.140 + * Automatically generated from STM32G4A1CEUx.xml + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/PinNamesVar.h b/variants/STM32G4xx/G4A1CEU/PinNamesVar.h similarity index 100% rename from variants/STM32G4xx/G491C(C-E)U_G4A1CEU/PinNamesVar.h rename to variants/STM32G4xx/G4A1CEU/PinNamesVar.h diff --git a/variants/STM32G4xx/G4A1CEU/boards_entry.txt b/variants/STM32G4xx/G4A1CEU/boards_entry.txt new file mode 100644 index 0000000000..91b04b6722 --- /dev/null +++ b/variants/STM32G4xx/G4A1CEU/boards_entry.txt @@ -0,0 +1,14 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic G4A1CEUx +GenG4.menu.pnum.GENERIC_G4A1CEUX=Generic G4A1CEUx +GenG4.menu.pnum.GENERIC_G4A1CEUX.upload.maximum_size=524288 +GenG4.menu.pnum.GENERIC_G4A1CEUX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G4A1CEUX.build.board=GENERIC_G4A1CEUX +GenG4.menu.pnum.GENERIC_G4A1CEUX.build.product_line=STM32G4A1xx +GenG4.menu.pnum.GENERIC_G4A1CEUX.build.variant=STM32G4xx/G4A1CEU +GenG4.menu.pnum.GENERIC_G4A1CEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G4A1.svd + diff --git a/variants/STM32C0xx/C092CBU_C092CC(T-U)/generic_clock.c b/variants/STM32G4xx/G4A1CEU/generic_clock.c similarity index 87% rename from variants/STM32C0xx/C092CBU_C092CC(T-U)/generic_clock.c rename to variants/STM32G4xx/G4A1CEU/generic_clock.c index a96fd6df0c..acad3748ed 100644 --- a/variants/STM32C0xx/C092CBU_C092CC(T-U)/generic_clock.c +++ b/variants/STM32G4xx/G4A1CEU/generic_clock.c @@ -10,8 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_C092CBUX) || defined(ARDUINO_GENERIC_C092CCTX) ||\ - defined(ARDUINO_GENERIC_C092CCUX) +#if defined(ARDUINO_GENERIC_G4A1CEUX) #include "pins_arduino.h" /** diff --git a/variants/STM32G4xx/G4A1CEU/variant_generic.cpp b/variants/STM32G4xx/G4A1CEU/variant_generic.cpp new file mode 100644 index 0000000000..f139c9b1b7 --- /dev/null +++ b/variants/STM32G4xx/G4A1CEU/variant_generic.cpp @@ -0,0 +1,85 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_G4A1CEUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18/A10 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_11, // D27/A11 + PB_12, // D28/A12 + PB_13, // D29/A13 + PB_14, // D30/A14 + PB_15, // D31/A15 + PC_4, // D32/A16 + PC_6, // D33 + PC_10, // D34 + PC_11, // D35 + PC_13, // D36 + PC_14, // D37 + PC_15, // D38 + PF_0, // D39/A17 + PF_1, // D40/A18 + PG_10 // D41 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 18, // A10, PB2 + 27, // A11, PB11 + 28, // A12, PB12 + 29, // A13, PB13 + 30, // A14, PB14 + 31, // A15, PB15 + 32, // A16, PC4 + 39, // A17, PF0 + 40 // A18, PF1 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32G4xx/G491C(C-E)U_G4A1CEU/variant_generic.h b/variants/STM32G4xx/G4A1CEU/variant_generic.h similarity index 100% rename from variants/STM32G4xx/G491C(C-E)U_G4A1CEU/variant_generic.h rename to variants/STM32G4xx/G4A1CEU/variant_generic.h diff --git a/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c b/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c index 3902b85f33..b0a228d10a 100644 --- a/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c +++ b/variants/STM32H5xx/H503CB(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503CBTx.xml, STM32H503CBUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H503EBY/PeripheralPins.c b/variants/STM32H5xx/H503EBY/PeripheralPins.c index 1296904e0e..b05ad04c94 100644 --- a/variants/STM32H5xx/H503EBY/PeripheralPins.c +++ b/variants/STM32H5xx/H503EBY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503EBYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H503KBU/PeripheralPins.c b/variants/STM32H5xx/H503KBU/PeripheralPins.c index 8a13c43cd8..fa68df763a 100644 --- a/variants/STM32H5xx/H503KBU/PeripheralPins.c +++ b/variants/STM32H5xx/H503KBU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503KBUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H503RBT/PeripheralPins.c b/variants/STM32H5xx/H503RBT/PeripheralPins.c index 620c23c8d3..8f31cd97c3 100644 --- a/variants/STM32H5xx/H503RBT/PeripheralPins.c +++ b/variants/STM32H5xx/H503RBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H503RBTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PeripheralPins.c b/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PeripheralPins.c index 8b33b29799..d63022c2a3 100644 --- a/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PeripheralPins.c +++ b/variants/STM32H5xx/H523C(C-E)(T-U)_H533CE(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32H523CCTx.xml, STM32H523CCUx.xml * STM32H523CETx.xml, STM32H523CEUx.xml * STM32H533CETx.xml, STM32H533CEUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H523HEY_H533HEY/PeripheralPins.c b/variants/STM32H5xx/H523HEY_H533HEY/PeripheralPins.c index 6ad4a8121a..9439de5fe6 100644 --- a/variants/STM32H5xx/H523HEY_H533HEY/PeripheralPins.c +++ b/variants/STM32H5xx/H523HEY_H533HEY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H523HEYx.xml, STM32H533HEYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H523R(C-E)T_H533RET/PeripheralPins.c b/variants/STM32H5xx/H523R(C-E)T_H533RET/PeripheralPins.c index c505cf3faf..e8025d43c4 100644 --- a/variants/STM32H5xx/H523R(C-E)T_H533RET/PeripheralPins.c +++ b/variants/STM32H5xx/H523R(C-E)T_H533RET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H523RCTx.xml, STM32H523RETx.xml * STM32H533RETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/PeripheralPins.c b/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/PeripheralPins.c index d0fbf20dd0..b502c22199 100644 --- a/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/PeripheralPins.c +++ b/variants/STM32H5xx/H523V(C-E)(I-T)_H533VE(I-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32H523VCIx.xml, STM32H523VCTx.xml * STM32H523VEIx.xml, STM32H523VETx.xml * STM32H533VEIx.xml, STM32H533VETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/PeripheralPins.c b/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/PeripheralPins.c index 7bf5c136c2..6da24984bf 100644 --- a/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/PeripheralPins.c +++ b/variants/STM32H5xx/H523Z(C-E)(J-T)_H533ZE(J-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32H523ZCJx.xml, STM32H523ZCTx.xml * STM32H523ZEJx.xml, STM32H523ZETx.xml * STM32H533ZEJx.xml, STM32H533ZETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c b/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c index 07c3e09dba..b22b04a2f0 100644 --- a/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c +++ b/variants/STM32H5xx/H562A(G-I)I/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562AGIx.xml, STM32H562AIIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c b/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c index 48641effdf..89bde9b7a2 100644 --- a/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c +++ b/variants/STM32H5xx/H562I(G-I)(K-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H562IGKx.xml, STM32H562IGTx.xml * STM32H562IIKx.xml, STM32H562IITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c index be4625b9f8..075fa283ce 100644 --- a/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c +++ b/variants/STM32H5xx/H562R(G-I)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562RGTx.xml, STM32H562RITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c b/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c index e428dd7515..128a93c5e0 100644 --- a/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c +++ b/variants/STM32H5xx/H562R(G-I)V/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562RGVx.xml, STM32H562RIVx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c index 5be6fb7a7f..eb9684f9ab 100644 --- a/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c +++ b/variants/STM32H5xx/H562V(G-I)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562VGTx.xml, STM32H562VITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c b/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c index dc857341f6..945a912574 100644 --- a/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c +++ b/variants/STM32H5xx/H562Z(G-I)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H562ZGTx.xml, STM32H562ZITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563A(G-I)I_H573AII/PeripheralPins.c b/variants/STM32H5xx/H563A(G-I)I_H573AII/PeripheralPins.c index ab9742f6d2..7e6dd5f9f2 100644 --- a/variants/STM32H5xx/H563A(G-I)I_H573AII/PeripheralPins.c +++ b/variants/STM32H5xx/H563A(G-I)I_H573AII/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H563AGIx.xml, STM32H563AIIx.xml * STM32H573AIIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PeripheralPins.c b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PeripheralPins.c index 7229e5fcc2..857020d191 100644 --- a/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563AIIxQ_H573AIIxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563AIIxQ.xml, STM32H573AIIxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/PeripheralPins.c b/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/PeripheralPins.c index 71fd1f3be4..0a524320fe 100644 --- a/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/PeripheralPins.c +++ b/variants/STM32H5xx/H563I(G-I)(K-T)_H573II(K-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32H563IGKx.xml, STM32H563IGTx.xml * STM32H563IIKx.xml, STM32H563IITx.xml * STM32H573IIKx.xml, STM32H573IITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins.c b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins.c index 549015fe61..cbdf564741 100644 --- a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563IIKxQ.xml, STM32H573IIKxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563IITxQ_H573IITxQ/PeripheralPins.c b/variants/STM32H5xx/H563IITxQ_H573IITxQ/PeripheralPins.c index f2e5df09e5..ca17633899 100644 --- a/variants/STM32H5xx/H563IITxQ_H573IITxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563IITxQ_H573IITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563IITxQ.xml, STM32H573IITxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PeripheralPins.c b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PeripheralPins.c index aeab928f78..d4b00e1af3 100644 --- a/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563MIYxQ_H573MIYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563MIYxQ.xml, STM32H573MIYxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563R(G-I)T_H573RIT/PeripheralPins.c b/variants/STM32H5xx/H563R(G-I)T_H573RIT/PeripheralPins.c index 5b9bf1f6c4..04cff8e4ea 100644 --- a/variants/STM32H5xx/H563R(G-I)T_H573RIT/PeripheralPins.c +++ b/variants/STM32H5xx/H563R(G-I)T_H573RIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H563RGTx.xml, STM32H563RITx.xml * STM32H573RITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563R(G-I)V_H573RIV/PeripheralPins.c b/variants/STM32H5xx/H563R(G-I)V_H573RIV/PeripheralPins.c index 786e31353c..58966cb2ec 100644 --- a/variants/STM32H5xx/H563R(G-I)V_H573RIV/PeripheralPins.c +++ b/variants/STM32H5xx/H563R(G-I)V_H573RIV/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H563RGVx.xml, STM32H563RIVx.xml * STM32H573RIVx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563V(G-I)T_H573VIT/PeripheralPins.c b/variants/STM32H5xx/H563V(G-I)T_H573VIT/PeripheralPins.c index 2fc06a010c..1c20589146 100644 --- a/variants/STM32H5xx/H563V(G-I)T_H573VIT/PeripheralPins.c +++ b/variants/STM32H5xx/H563V(G-I)T_H573VIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H563VGTx.xml, STM32H563VITx.xml * STM32H573VITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c b/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c index c2142164c9..e73c9ea671 100644 --- a/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563VITxQ_H573VITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563VITxQ.xml, STM32H573VITxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PeripheralPins.c b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PeripheralPins.c index 4cfcbdab1b..a86f886067 100644 --- a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PeripheralPins.c +++ b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H563ZGTx.xml, STM32H563ZITx.xml * STM32H573ZITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c b/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c index 6ff1d49e7a..f707fb7bad 100644 --- a/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c +++ b/variants/STM32H5xx/H563ZITxQ_H573ZITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H563ZITxQ.xml, STM32H573ZITxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/PeripheralPins.c b/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/PeripheralPins.c index 4067978279..82e28e11d5 100644 --- a/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/PeripheralPins.c +++ b/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32H723VGHx.xml, STM32H723VGTx.xml * STM32H730VBHx.xml, STM32H730VBTx.xml * STM32H733VGHx.xml, STM32H733VGTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H723Z(E-G)I_H730ZBI_H733ZGI/PeripheralPins.c b/variants/STM32H7xx/H723Z(E-G)I_H730ZBI_H733ZGI/PeripheralPins.c index 97158f7494..f32828c7ce 100644 --- a/variants/STM32H7xx/H723Z(E-G)I_H730ZBI_H733ZGI/PeripheralPins.c +++ b/variants/STM32H7xx/H723Z(E-G)I_H730ZBI_H733ZGI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H723ZEIx.xml, STM32H723ZGIx.xml * STM32H730ZBIx.xml, STM32H733ZGIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/PeripheralPins.c b/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/PeripheralPins.c index 04479c8fa5..c4197c34d0 100644 --- a/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/PeripheralPins.c +++ b/variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H723ZETx.xml, STM32H723ZGTx.xml * STM32H730ZBTx.xml, STM32H733ZGTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/PeripheralPins.c b/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/PeripheralPins.c index 07efd49f4a..03172e32c7 100644 --- a/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/PeripheralPins.c +++ b/variants/STM32H7xx/H725A(E-G)I_H730ABIxQ_H735AGI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725AEIx.xml, STM32H725AGIx.xml * STM32H730ABIxQ.xml, STM32H735AGIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/PeripheralPins.c b/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/PeripheralPins.c index 91c6fffb30..01f6d24706 100644 --- a/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/PeripheralPins.c +++ b/variants/STM32H7xx/H725I(E-G)K_H730IBKxQ_H735IGK/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725IEKx.xml, STM32H725IGKx.xml * STM32H730IBKxQ.xml, STM32H735IGKx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/PeripheralPins.c b/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/PeripheralPins.c index a5ace505fc..ffd7a11944 100644 --- a/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/PeripheralPins.c +++ b/variants/STM32H7xx/H725I(E-G)T_H730IBTxQ_H735IGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725IETx.xml, STM32H725IGTx.xml * STM32H730IBTxQ.xml, STM32H735IGTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725R(E-G)V_H735RGV/PeripheralPins.c b/variants/STM32H7xx/H725R(E-G)V_H735RGV/PeripheralPins.c index 7a28f863da..960789b94f 100644 --- a/variants/STM32H7xx/H725R(E-G)V_H735RGV/PeripheralPins.c +++ b/variants/STM32H7xx/H725R(E-G)V_H735RGV/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725REVx.xml, STM32H725RGVx.xml * STM32H735RGVx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725V(E-G)H_H735VGH/PeripheralPins.c b/variants/STM32H7xx/H725V(E-G)H_H735VGH/PeripheralPins.c index 1f04549ef1..5549c7ac2c 100644 --- a/variants/STM32H7xx/H725V(E-G)H_H735VGH/PeripheralPins.c +++ b/variants/STM32H7xx/H725V(E-G)H_H735VGH/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725VEHx.xml, STM32H725VGHx.xml * STM32H735VGHx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725V(E-G)T_H735VGT/PeripheralPins.c b/variants/STM32H7xx/H725V(E-G)T_H735VGT/PeripheralPins.c index b8c7560959..38711e8e99 100644 --- a/variants/STM32H7xx/H725V(E-G)T_H735VGT/PeripheralPins.c +++ b/variants/STM32H7xx/H725V(E-G)T_H735VGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725VETx.xml, STM32H725VGTx.xml * STM32H735VGTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725VGY_H735VGY/PeripheralPins.c b/variants/STM32H7xx/H725VGY_H735VGY/PeripheralPins.c index 2886cc14d0..2098032fcc 100644 --- a/variants/STM32H7xx/H725VGY_H735VGY/PeripheralPins.c +++ b/variants/STM32H7xx/H725VGY_H735VGY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H725VGYx.xml, STM32H735VGYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H725Z(E-G)T_H735ZGT/PeripheralPins.c b/variants/STM32H7xx/H725Z(E-G)T_H735ZGT/PeripheralPins.c index ee9bcaceee..a61816c9f9 100644 --- a/variants/STM32H7xx/H725Z(E-G)T_H735ZGT/PeripheralPins.c +++ b/variants/STM32H7xx/H725Z(E-G)T_H735ZGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H725ZETx.xml, STM32H725ZGTx.xml * STM32H735ZGTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742A(G-I)I_H743A(G-I)I_H753AII/PeripheralPins.c b/variants/STM32H7xx/H742A(G-I)I_H743A(G-I)I_H753AII/PeripheralPins.c index a34b77ebdb..ed91cf615a 100644 --- a/variants/STM32H7xx/H742A(G-I)I_H743A(G-I)I_H753AII/PeripheralPins.c +++ b/variants/STM32H7xx/H742A(G-I)I_H743A(G-I)I_H753AII/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H742A(G-I)Ix.xml, STM32H743A(G-I)Ix.xml * STM32H753AIIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742B(G-I)T_H743B(G-I)T_H753BIT/PeripheralPins.c b/variants/STM32H7xx/H742B(G-I)T_H743B(G-I)T_H753BIT/PeripheralPins.c index 3b6325efdc..f0552557c5 100644 --- a/variants/STM32H7xx/H742B(G-I)T_H743B(G-I)T_H753BIT/PeripheralPins.c +++ b/variants/STM32H7xx/H742B(G-I)T_H743B(G-I)T_H753BIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H742B(G-I)Tx.xml, STM32H743BGTx.xml * STM32H743BITx.xml, STM32H753BITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PeripheralPins.c b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PeripheralPins.c index 53cb7cfa56..29257fb4fe 100644 --- a/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PeripheralPins.c +++ b/variants/STM32H7xx/H742I(G-I)(K-T)_H743I(G-I)(K-T)_H750IB(K-T)_H753II(K-T)/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32H743IIKx.xml, STM32H743IITx.xml * STM32H750IBKx.xml, STM32H750IBTx.xml * STM32H753IIKx.xml, STM32H753IITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/PeripheralPins.c b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/PeripheralPins.c index e0196c01e5..3708b88058 100644 --- a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/PeripheralPins.c +++ b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32H743V(G-I)Hx.xml, STM32H743VGTx.xml * STM32H743VITx.xml, STM32H750VBTx.xml * STM32H753VIHx.xml, STM32H753VITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins.c b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins.c index 337474cf84..2c38296153 100644 --- a/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins.c +++ b/variants/STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH/PeripheralPins.c @@ -17,7 +17,7 @@ * STM32H747XIHx.xml, STM32H750XBHx.xml * STM32H753XIHx.xml, STM32H755XIHx.xml * STM32H757XIHx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/PeripheralPins.c b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/PeripheralPins.c index 05d07d1502..f5d50daa19 100644 --- a/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/PeripheralPins.c +++ b/variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32H747IGTx.xml, STM32H747IITx.xml * STM32H750ZBTx.xml, STM32H753ZITx.xml * STM32H757AIIx.xml, STM32H757IITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H745B(G-I)T_H755BIT/PeripheralPins.c b/variants/STM32H7xx/H745B(G-I)T_H755BIT/PeripheralPins.c index 185df99550..86ca474a2d 100644 --- a/variants/STM32H7xx/H745B(G-I)T_H755BIT/PeripheralPins.c +++ b/variants/STM32H7xx/H745B(G-I)T_H755BIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H745BGTx.xml, STM32H745BITx.xml * STM32H755BITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H745I(G-I)K_H755IIK/PeripheralPins.c b/variants/STM32H7xx/H745I(G-I)K_H755IIK/PeripheralPins.c index 6a2d9d7fde..714552d409 100644 --- a/variants/STM32H7xx/H745I(G-I)K_H755IIK/PeripheralPins.c +++ b/variants/STM32H7xx/H745I(G-I)K_H755IIK/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H745IGKx.xml, STM32H745IIKx.xml * STM32H755IIKx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H745I(G-I)T_H755IIT/PeripheralPins.c b/variants/STM32H7xx/H745I(G-I)T_H755IIT/PeripheralPins.c index 44c1751342..4a42ac8e32 100644 --- a/variants/STM32H7xx/H745I(G-I)T_H755IIT/PeripheralPins.c +++ b/variants/STM32H7xx/H745I(G-I)T_H755IIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H745IGTx.xml, STM32H745IITx.xml * STM32H755IITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/PeripheralPins.c b/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/PeripheralPins.c index 24882855e4..66184282e5 100644 --- a/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/PeripheralPins.c +++ b/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H745ZGTx.xml, STM32H745ZITx.xml * STM32H755ZITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H747B(G-I)T_H757BIT/PeripheralPins.c b/variants/STM32H7xx/H747B(G-I)T_H757BIT/PeripheralPins.c index 5a66615415..26504d8238 100644 --- a/variants/STM32H7xx/H747B(G-I)T_H757BIT/PeripheralPins.c +++ b/variants/STM32H7xx/H747B(G-I)T_H757BIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H747BGTx.xml, STM32H747BITx.xml * STM32H757BITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H747ZIY_H757ZIY/PeripheralPins.c b/variants/STM32H7xx/H747ZIY_H757ZIY/PeripheralPins.c index fcea711ca5..69a3a78e99 100644 --- a/variants/STM32H7xx/H747ZIY_H757ZIY/PeripheralPins.c +++ b/variants/STM32H7xx/H747ZIY_H757ZIY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H747ZIYx.xml, STM32H757ZIYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/PeripheralPins.c index 1be00260aa..3b5cfbf79b 100644 --- a/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3A(G-I)IxQ_H7B0ABIxQ_H7B3AIIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H7A3A(G-I)IxQ.xml, STM32H7B0ABIxQ.xml * STM32H7B3AIIxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3I(G-I)(K-T)_H7B0IBT_H7B3II(K-T)/PeripheralPins.c b/variants/STM32H7xx/H7A3I(G-I)(K-T)_H7B0IBT_H7B3II(K-T)/PeripheralPins.c index 05019e170b..d86106e0e7 100644 --- a/variants/STM32H7xx/H7A3I(G-I)(K-T)_H7B0IBT_H7B3II(K-T)/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3I(G-I)(K-T)_H7B0IBT_H7B3II(K-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32H7A3I(G-I)Kx.xml, STM32H7A3I(G-I)Tx.xml * STM32H7B0IBTx.xml, STM32H7B3IIKx.xml * STM32H7B3IITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/PeripheralPins.c index 42f31524f0..4785027c2a 100644 --- a/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3I(G-I)KxQ_H7B0IBKxQ_H7B3IIKxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H7A3I(G-I)KxQ.xml, STM32H7B0IBKxQ.xml * STM32H7B3IIKxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/PeripheralPins.c index 2f04788fb1..134461adac 100644 --- a/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3I(G-I)TxQ_H7B3IITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3I(G-I)TxQ.xml, STM32H7B3IITxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/PeripheralPins.c index 7602ef4e49..ad8be6b981 100644 --- a/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3L(G-I)HxQ_H7B3LIHxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3L(G-I)HxQ.xml, STM32H7B3LIHxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3N(G-I)H_H7B3NIH/PeripheralPins.c b/variants/STM32H7xx/H7A3N(G-I)H_H7B3NIH/PeripheralPins.c index 57c8691d6b..b49dae0a92 100644 --- a/variants/STM32H7xx/H7A3N(G-I)H_H7B3NIH/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3N(G-I)H_H7B3NIH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3N(G-I)Hx.xml, STM32H7B3NIHx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/PeripheralPins.c index f20277a7de..d1cb8d7d0f 100644 --- a/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3QIYxQ_H7B3QIYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3QIYxQ.xml, STM32H7B3QIYxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3R(G-I)T_H7B0RBT_H7B3RIT/PeripheralPins.c b/variants/STM32H7xx/H7A3R(G-I)T_H7B0RBT_H7B3RIT/PeripheralPins.c index 77cb386b29..24259f1dae 100644 --- a/variants/STM32H7xx/H7A3R(G-I)T_H7B0RBT_H7B3RIT/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3R(G-I)T_H7B0RBT_H7B3RIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H7A3R(G-I)Tx.xml, STM32H7B0RBTx.xml * STM32H7B3RITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T)/PeripheralPins.c b/variants/STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T)/PeripheralPins.c index 2514bb16ed..8db9e16cc1 100644 --- a/variants/STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T)/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3V(G-I)(H-T)_H7B0VBT_H7B3VI(H-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32H7A3V(G-I)Hx.xml, STM32H7A3V(G-I)Tx.xml * STM32H7B0VBTx.xml, STM32H7B3VIHx.xml * STM32H7B3VITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/PeripheralPins.c index 1700b4debb..3bc4ece848 100644 --- a/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3V(G-I)HxQ_H7B3VIHxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3V(G-I)HxQ.xml, STM32H7B3VIHxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/PeripheralPins.c index 28284a334f..e4efb8f881 100644 --- a/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3V(G-I)TxQ_H7B3VITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3V(G-I)TxQ.xml, STM32H7B3VITxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3Z(G-I)T_H7B0ZBT_H7B3ZIT/PeripheralPins.c b/variants/STM32H7xx/H7A3Z(G-I)T_H7B0ZBT_H7B3ZIT/PeripheralPins.c index ba25c4f38a..a066a4f78e 100644 --- a/variants/STM32H7xx/H7A3Z(G-I)T_H7B0ZBT_H7B3ZIT/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3Z(G-I)T_H7B0ZBT_H7B3ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32H7A3Z(G-I)Tx.xml, STM32H7B0ZBTx.xml * STM32H7B3ZITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/PeripheralPins.c b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/PeripheralPins.c index c19b53c97f..69c93bd53e 100644 --- a/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/PeripheralPins.c +++ b/variants/STM32H7xx/H7A3Z(G-I)TxQ_H7B3ZITxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32H7A3Z(G-I)TxQ.xml, STM32H7B3ZITxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010C6T/PeripheralPins.c b/variants/STM32L0xx/L010C6T/PeripheralPins.c index a903aff461..2ef4f9fdae 100644 --- a/variants/STM32L0xx/L010C6T/PeripheralPins.c +++ b/variants/STM32L0xx/L010C6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L010C6Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/PeripheralPins.c b/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/PeripheralPins.c index 86f5afcda4..b397873726 100644 --- a/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/PeripheralPins.c +++ b/variants/STM32L0xx/L010F4P_L011F(3-4)P_L021F4P/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L010F4Px.xml, STM32L011F(3-4)Px.xml * STM32L021F4Px.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/PeripheralPins.c b/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/PeripheralPins.c index f4c0083d60..5f18fcf36f 100644 --- a/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/PeripheralPins.c +++ b/variants/STM32L0xx/L010K4T_L011K(3-4)T_L021K4T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L010K4Tx.xml, STM32L011K(3-4)Tx.xml * STM32L021K4Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010K8T/PeripheralPins.c b/variants/STM32L0xx/L010K8T/PeripheralPins.c index e732d625d2..7ac594dde7 100644 --- a/variants/STM32L0xx/L010K8T/PeripheralPins.c +++ b/variants/STM32L0xx/L010K8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L010K8Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010R8T/PeripheralPins.c b/variants/STM32L0xx/L010R8T/PeripheralPins.c index 0f35c2dd79..60ef7324e6 100644 --- a/variants/STM32L0xx/L010R8T/PeripheralPins.c +++ b/variants/STM32L0xx/L010R8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L010R8Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L010RBT/PeripheralPins.c b/variants/STM32L0xx/L010RBT/PeripheralPins.c index 309c8db9e3..5e173f143e 100644 --- a/variants/STM32L0xx/L010RBT/PeripheralPins.c +++ b/variants/STM32L0xx/L010RBT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L010RBTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L011D(3-4)P_L021D4P/PeripheralPins.c b/variants/STM32L0xx/L011D(3-4)P_L021D4P/PeripheralPins.c index 611856ce75..11fb9eeec1 100644 --- a/variants/STM32L0xx/L011D(3-4)P_L021D4P/PeripheralPins.c +++ b/variants/STM32L0xx/L011D(3-4)P_L021D4P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L011D(3-4)Px.xml, STM32L021D4Px.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L011E(3-4)Y/PeripheralPins.c b/variants/STM32L0xx/L011E(3-4)Y/PeripheralPins.c index 2d7ed36d7e..926e3617c5 100644 --- a/variants/STM32L0xx/L011E(3-4)Y/PeripheralPins.c +++ b/variants/STM32L0xx/L011E(3-4)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L011E(3-4)Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L011F(3-4)U_L021F4U/PeripheralPins.c b/variants/STM32L0xx/L011F(3-4)U_L021F4U/PeripheralPins.c index 4bd5a1d1ee..098b9e6623 100644 --- a/variants/STM32L0xx/L011F(3-4)U_L021F4U/PeripheralPins.c +++ b/variants/STM32L0xx/L011F(3-4)U_L021F4U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L011F(3-4)Ux.xml, STM32L021F4Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L011G(3-4)U_L021G4U/PeripheralPins.c b/variants/STM32L0xx/L011G(3-4)U_L021G4U/PeripheralPins.c index 9d17c6c0c2..05ecbd6e5c 100644 --- a/variants/STM32L0xx/L011G(3-4)U_L021G4U/PeripheralPins.c +++ b/variants/STM32L0xx/L011G(3-4)U_L021G4U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L011G(3-4)Ux.xml, STM32L021G4Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L011K(3-4)U_L021K4U/PeripheralPins.c b/variants/STM32L0xx/L011K(3-4)U_L021K4U/PeripheralPins.c index df46b17c4c..666c8ea24b 100644 --- a/variants/STM32L0xx/L011K(3-4)U_L021K4U/PeripheralPins.c +++ b/variants/STM32L0xx/L011K(3-4)U_L021K4U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L011K(3-4)Ux.xml, STM32L021K4Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/PeripheralPins.c b/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/PeripheralPins.c index f66396200c..b55a35541b 100644 --- a/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/PeripheralPins.c +++ b/variants/STM32L0xx/L031C(4-6)(T-U)_L041C4T_L041C6(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L031C(4-6)Tx.xml, STM32L031C(4-6)Ux.xml * STM32L041C(4-6)Tx.xml, STM32L041C6Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/PeripheralPins.c b/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/PeripheralPins.c index 485b8eba56..ae2de58f60 100644 --- a/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/PeripheralPins.c +++ b/variants/STM32L0xx/L031E(4-6)Y_L041E6Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031E(4-6)Yx.xml, STM32L041E6Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031F(4-6)P_L041F6P/PeripheralPins.c b/variants/STM32L0xx/L031F(4-6)P_L041F6P/PeripheralPins.c index fa3792a79e..f504188d69 100644 --- a/variants/STM32L0xx/L031F(4-6)P_L041F6P/PeripheralPins.c +++ b/variants/STM32L0xx/L031F(4-6)P_L041F6P/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031F(4-6)Px.xml, STM32L041F6Px.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031G(4-6)U_L041G6U/PeripheralPins.c b/variants/STM32L0xx/L031G(4-6)U_L041G6U/PeripheralPins.c index 96353dd0af..2d28e8ac31 100644 --- a/variants/STM32L0xx/L031G(4-6)U_L041G6U/PeripheralPins.c +++ b/variants/STM32L0xx/L031G(4-6)U_L041G6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031G(4-6)Ux.xml, STM32L041G6Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031G6UxS_L041G6UxS/PeripheralPins.c b/variants/STM32L0xx/L031G6UxS_L041G6UxS/PeripheralPins.c index a6d4ec7d93..b3458518e2 100644 --- a/variants/STM32L0xx/L031G6UxS_L041G6UxS/PeripheralPins.c +++ b/variants/STM32L0xx/L031G6UxS_L041G6UxS/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031G6UxS.xml, STM32L041G6UxS.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031K(4-6)T_L041K6T/PeripheralPins.c b/variants/STM32L0xx/L031K(4-6)T_L041K6T/PeripheralPins.c index 7d7bfcca0b..f5f871f512 100644 --- a/variants/STM32L0xx/L031K(4-6)T_L041K6T/PeripheralPins.c +++ b/variants/STM32L0xx/L031K(4-6)T_L041K6T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031K(4-6)Tx.xml, STM32L041K6Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L031K(4-6)U_L041K6U/PeripheralPins.c b/variants/STM32L0xx/L031K(4-6)U_L041K6U/PeripheralPins.c index 93db6e2703..e30f94502a 100644 --- a/variants/STM32L0xx/L031K(4-6)U_L041K6U/PeripheralPins.c +++ b/variants/STM32L0xx/L031K(4-6)U_L041K6U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L031K(4-6)Ux.xml, STM32L041K6Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051C(6-8)(T-U)/PeripheralPins.c b/variants/STM32L0xx/L051C(6-8)(T-U)/PeripheralPins.c index b6abf40145..7b94aa6d58 100644 --- a/variants/STM32L0xx/L051C(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32L0xx/L051C(6-8)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051C(6-8)Tx.xml, STM32L051C(6-8)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051K(6-8)T/PeripheralPins.c b/variants/STM32L0xx/L051K(6-8)T/PeripheralPins.c index 69d10057f5..a65c6e92fc 100644 --- a/variants/STM32L0xx/L051K(6-8)T/PeripheralPins.c +++ b/variants/STM32L0xx/L051K(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051K(6-8)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051K(6-8)U/PeripheralPins.c b/variants/STM32L0xx/L051K(6-8)U/PeripheralPins.c index 4c13e43890..4f882387d5 100644 --- a/variants/STM32L0xx/L051K(6-8)U/PeripheralPins.c +++ b/variants/STM32L0xx/L051K(6-8)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051K(6-8)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051R(6-8)H/PeripheralPins.c b/variants/STM32L0xx/L051R(6-8)H/PeripheralPins.c index 149b3350de..084c36b44a 100644 --- a/variants/STM32L0xx/L051R(6-8)H/PeripheralPins.c +++ b/variants/STM32L0xx/L051R(6-8)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051R(6-8)Hx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051R(6-8)T/PeripheralPins.c b/variants/STM32L0xx/L051R(6-8)T/PeripheralPins.c index c513430aec..939a7b3264 100644 --- a/variants/STM32L0xx/L051R(6-8)T/PeripheralPins.c +++ b/variants/STM32L0xx/L051R(6-8)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051R(6-8)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L051T(6-8)Y/PeripheralPins.c b/variants/STM32L0xx/L051T(6-8)Y/PeripheralPins.c index a0beda6f50..2d88eea1d2 100644 --- a/variants/STM32L0xx/L051T(6-8)Y/PeripheralPins.c +++ b/variants/STM32L0xx/L051T(6-8)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L051T(6-8)Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/PeripheralPins.c b/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/PeripheralPins.c index 74a70e11f9..cbc6051586 100644 --- a/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/PeripheralPins.c +++ b/variants/STM32L0xx/L052C(6-8)(T-U)_L053C(6-8)(T-U)_L062C8U_L063C8(T-U)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32L053C(6-8)Tx.xml, STM32L053C(6-8)Ux.xml * STM32L062C8Ux.xml, STM32L063C8Tx.xml * STM32L063C8Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052K(6-8)T_L062K8T/PeripheralPins.c b/variants/STM32L0xx/L052K(6-8)T_L062K8T/PeripheralPins.c index 3fab0324a8..07e35bac40 100644 --- a/variants/STM32L0xx/L052K(6-8)T_L062K8T/PeripheralPins.c +++ b/variants/STM32L0xx/L052K(6-8)T_L062K8T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L052K(6-8)Tx.xml, STM32L062K8Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052K(6-8)U_L062K8U/PeripheralPins.c b/variants/STM32L0xx/L052K(6-8)U_L062K8U/PeripheralPins.c index c4cbb8d11e..95eea83201 100644 --- a/variants/STM32L0xx/L052K(6-8)U_L062K8U/PeripheralPins.c +++ b/variants/STM32L0xx/L052K(6-8)U_L062K8U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L052K(6-8)Ux.xml, STM32L062K8Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/PeripheralPins.c b/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/PeripheralPins.c index 40d16a6c75..a79b6a33a5 100644 --- a/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/PeripheralPins.c +++ b/variants/STM32L0xx/L052R(6-8)H_L053R(6-8)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L052R(6-8)Hx.xml, STM32L053R(6-8)Hx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T/PeripheralPins.c b/variants/STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T/PeripheralPins.c index 9d78b936e4..6b04a56203 100644 --- a/variants/STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T/PeripheralPins.c +++ b/variants/STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L052R(6-8)Tx.xml, STM32L053R(6-8)Tx.xml * STM32L063R8Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/PeripheralPins.c b/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/PeripheralPins.c index c6219bf0c9..f2492443ac 100644 --- a/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/PeripheralPins.c +++ b/variants/STM32L0xx/L052T6Y_L052T8(F-Y)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L052T(6-8)Yx.xml, STM32L052T8Fx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071C(8-B-Z)(T-U)_L081CBT_L081CZ(T-U)/PeripheralPins.c b/variants/STM32L0xx/L071C(8-B-Z)(T-U)_L081CBT_L081CZ(T-U)/PeripheralPins.c index cf9cbb6511..37ed673dd1 100644 --- a/variants/STM32L0xx/L071C(8-B-Z)(T-U)_L081CBT_L081CZ(T-U)/PeripheralPins.c +++ b/variants/STM32L0xx/L071C(8-B-Z)(T-U)_L081CBT_L081CZ(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L071C(B-Z)Tx.xml, STM32L071C(B-Z)Ux.xml * STM32L071C8Tx.xml, STM32L071C8Ux.xml * STM32L081C(B-Z)Tx.xml, STM32L081CZUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071C(B-Z)Y/PeripheralPins.c b/variants/STM32L0xx/L071C(B-Z)Y/PeripheralPins.c index 8df24617fd..d5c8dc5b00 100644 --- a/variants/STM32L0xx/L071C(B-Z)Y/PeripheralPins.c +++ b/variants/STM32L0xx/L071C(B-Z)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L071C(B-Z)Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071K(8-B-Z)U_L081KZU/PeripheralPins.c b/variants/STM32L0xx/L071K(8-B-Z)U_L081KZU/PeripheralPins.c index b57e938bef..ab5be3de6b 100644 --- a/variants/STM32L0xx/L071K(8-B-Z)U_L081KZU/PeripheralPins.c +++ b/variants/STM32L0xx/L071K(8-B-Z)U_L081KZU/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L071K(B-Z)Ux.xml, STM32L071K8Ux.xml * STM32L081KZUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071K(B-Z)T_L081KZT/PeripheralPins.c b/variants/STM32L0xx/L071K(B-Z)T_L081KZT/PeripheralPins.c index 7f5a50fbb3..e41b8ff91b 100644 --- a/variants/STM32L0xx/L071K(B-Z)T_L081KZT/PeripheralPins.c +++ b/variants/STM32L0xx/L071K(B-Z)T_L081KZT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L071K(B-Z)Tx.xml, STM32L081KZTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071R(B-Z)H/PeripheralPins.c b/variants/STM32L0xx/L071R(B-Z)H/PeripheralPins.c index d5e4aaff38..16fc5168cd 100644 --- a/variants/STM32L0xx/L071R(B-Z)H/PeripheralPins.c +++ b/variants/STM32L0xx/L071R(B-Z)H/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L071R(B-Z)Hx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071R(B-Z)T/PeripheralPins.c b/variants/STM32L0xx/L071R(B-Z)T/PeripheralPins.c index 6eafeeca25..6f4aa28a54 100644 --- a/variants/STM32L0xx/L071R(B-Z)T/PeripheralPins.c +++ b/variants/STM32L0xx/L071R(B-Z)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L071R(B-Z)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L071V(8-B-Z)(I-T)/PeripheralPins.c b/variants/STM32L0xx/L071V(8-B-Z)(I-T)/PeripheralPins.c index 5c6e3a3c11..591218cc58 100644 --- a/variants/STM32L0xx/L071V(8-B-Z)(I-T)/PeripheralPins.c +++ b/variants/STM32L0xx/L071V(8-B-Z)(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L071V(B-Z)Ix.xml, STM32L071V(B-Z)Tx.xml * STM32L071V8Ix.xml, STM32L071V8Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/PeripheralPins.c b/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/PeripheralPins.c index 97322ac815..4f2bf5d0d6 100644 --- a/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/PeripheralPins.c +++ b/variants/STM32L0xx/L072C(B-Z)(T-U)_L073C(B-Z)(T-U)_L082CZU_L083CBT_L083CZ(T-U)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32L073C(B-Z)Tx.xml, STM32L073C(B-Z)Ux.xml * STM32L082CZUx.xml, STM32L083C(B-Z)Tx.xml * STM32L083CZUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072CBY_L072CZ(E-Y)_L073CZY_L082CZY/PeripheralPins.c b/variants/STM32L0xx/L072CBY_L072CZ(E-Y)_L073CZY_L082CZY/PeripheralPins.c index 32539c20d9..4596e1040c 100644 --- a/variants/STM32L0xx/L072CBY_L072CZ(E-Y)_L073CZY_L082CZY/PeripheralPins.c +++ b/variants/STM32L0xx/L072CBY_L072CZ(E-Y)_L073CZY_L082CZY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L072C(B-Z)Yx.xml, STM32L072CZEx.xml * STM32L073CZYx.xml, STM32L082CZYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072K(B-Z)T_L082K(B-Z)T/PeripheralPins.c b/variants/STM32L0xx/L072K(B-Z)T_L082K(B-Z)T/PeripheralPins.c index 44cd71cc6c..f8f1705c85 100644 --- a/variants/STM32L0xx/L072K(B-Z)T_L082K(B-Z)T/PeripheralPins.c +++ b/variants/STM32L0xx/L072K(B-Z)T_L082K(B-Z)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L072K(B-Z)Tx.xml, STM32L082K(B-Z)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/PeripheralPins.c b/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/PeripheralPins.c index 6069ad838e..742b29c5da 100644 --- a/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/PeripheralPins.c +++ b/variants/STM32L0xx/L072K(B-Z)U_L082K(B-Z)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L072K(B-Z)Ux.xml, STM32L082K(B-Z)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/PeripheralPins.c b/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/PeripheralPins.c index 1c1fa274ef..ab4a689d7a 100644 --- a/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/PeripheralPins.c +++ b/variants/STM32L0xx/L072R(B-Z)(H-I)_L073RBH_L073RZ(H-I)_L083R(B-Z)H/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L072R(B-Z)Hx.xml, STM32L072R(B-Z)Ix.xml * STM32L073R(B-Z)Hx.xml, STM32L073RZIx.xml * STM32L083R(B-Z)Hx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T/PeripheralPins.c b/variants/STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T/PeripheralPins.c index 13e884599e..a60064550e 100644 --- a/variants/STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T/PeripheralPins.c +++ b/variants/STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L072R(B-Z)Tx.xml, STM32L073R(B-Z)Tx.xml * STM32L083R(B-Z)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/PeripheralPins.c b/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/PeripheralPins.c index 192df23415..a5b3307172 100644 --- a/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/PeripheralPins.c +++ b/variants/STM32L0xx/L072V(8-B-Z)(I-T)_L073V(8-B-Z)(I-T)_L083V(8-B-Z)(I-T)/PeripheralPins.c @@ -17,7 +17,7 @@ * STM32L073V8Ix.xml, STM32L073V8Tx.xml * STM32L083V(B-Z)Ix.xml, STM32L083V(B-Z)Tx.xml * STM32L083V8Ix.xml, STM32L083V8Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/PeripheralPins.c b/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/PeripheralPins.c index 82f6a0d3ae..8e60ec4c0d 100644 --- a/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A)/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32L151C(6-8-B)Ux.xml, STM32L151C(6-8-B)UxA.xml * STM32L152C(6-8-B)Tx.xml, STM32L152C(6-8-B)TxA.xml * STM32L152C(6-8-B)Ux.xml, STM32L152C(6-8-B)UxA.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/PeripheralPins.c b/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/PeripheralPins.c index 04b89ef1a9..ea59b115f3 100644 --- a/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L100R(8-B)Tx(A)_L151R(6-8-B)Tx(A)_L152R(6-8-B)Tx(A)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L100R(8-B)Tx.xml, STM32L100R(8-B)TxA.xml * STM32L151R(6-8-B)Tx.xml, STM32L151R(6-8-B)TxA.xml * STM32L152R(6-8-B)Tx.xml, STM32L152R(6-8-B)TxA.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L100RCT/PeripheralPins.c b/variants/STM32L1xx/L100RCT/PeripheralPins.c index 6dbe47fb4c..af23714b0f 100644 --- a/variants/STM32L1xx/L100RCT/PeripheralPins.c +++ b/variants/STM32L1xx/L100RCT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L100RCTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151CC(T-U)_L152CC(T-U)/PeripheralPins.c b/variants/STM32L1xx/L151CC(T-U)_L152CC(T-U)/PeripheralPins.c index 1f37ae69e3..38969f7611 100644 --- a/variants/STM32L1xx/L151CC(T-U)_L152CC(T-U)/PeripheralPins.c +++ b/variants/STM32L1xx/L151CC(T-U)_L152CC(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151CCTx.xml, STM32L151CCUx.xml * STM32L152CCTx.xml, STM32L152CCUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151QCH_L152QCH_L162QCH/PeripheralPins.c b/variants/STM32L1xx/L151QCH_L152QCH_L162QCH/PeripheralPins.c index d9f0c7a823..5029cfeeb4 100644 --- a/variants/STM32L1xx/L151QCH_L152QCH_L162QCH/PeripheralPins.c +++ b/variants/STM32L1xx/L151QCH_L152QCH_L162QCH/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151QCHx.xml, STM32L152QCHx.xml * STM32L162QCHx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151QDH_L152QDH_L162QDH/PeripheralPins.c b/variants/STM32L1xx/L151QDH_L152QDH_L162QDH/PeripheralPins.c index 2e8b6a0707..4e70674806 100644 --- a/variants/STM32L1xx/L151QDH_L152QDH_L162QDH/PeripheralPins.c +++ b/variants/STM32L1xx/L151QDH_L152QDH_L162QDH/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151QDHx.xml, STM32L152QDHx.xml * STM32L162QDHx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151QEH_L152QEH/PeripheralPins.c b/variants/STM32L1xx/L151QEH_L152QEH/PeripheralPins.c index 74227e3d0c..8c7919ce6b 100644 --- a/variants/STM32L1xx/L151QEH_L152QEH/PeripheralPins.c +++ b/variants/STM32L1xx/L151QEH_L152QEH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L151QEHx.xml, STM32L152QEHx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/PeripheralPins.c b/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/PeripheralPins.c index 8733654c37..bd7269164f 100644 --- a/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L151R(6-8-B)Hx(A)_L152R(6-8-B)Hx(A)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151R(6-8-B)Hx.xml, STM32L151R(6-8-B)HxA.xml * STM32L152R(6-8-B)Hx.xml, STM32L152R(6-8-B)HxA.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/PeripheralPins.c b/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/PeripheralPins.c index a464a00d65..e3e17c42d6 100644 --- a/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L151RC(T-Y)x(A)_L151UCY_L152RCTx(A)_L152UCY_L162RCTx(A)/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32L152RCTx.xml, STM32L152RCTxA.xml * STM32L152UCYx.xml, STM32L162RCTx.xml * STM32L162RCTxA.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151RD(T-Y)_L152RD(T-Y)_L162RD(T-Y)/PeripheralPins.c b/variants/STM32L1xx/L151RD(T-Y)_L152RD(T-Y)_L162RD(T-Y)/PeripheralPins.c index df44ed8ebb..3eb12206dc 100644 --- a/variants/STM32L1xx/L151RD(T-Y)_L152RD(T-Y)_L162RD(T-Y)/PeripheralPins.c +++ b/variants/STM32L1xx/L151RD(T-Y)_L152RD(T-Y)_L162RD(T-Y)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L151RDTx.xml, STM32L151RDYx.xml * STM32L152RDTx.xml, STM32L152RDYx.xml * STM32L162RDTx.xml, STM32L162RDYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151RET_L152RET_L162RET/PeripheralPins.c b/variants/STM32L1xx/L151RET_L152RET_L162RET/PeripheralPins.c index 26e679bfc4..ba3428a5c7 100644 --- a/variants/STM32L1xx/L151RET_L152RET_L162RET/PeripheralPins.c +++ b/variants/STM32L1xx/L151RET_L152RET_L162RET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151RETx.xml, STM32L152RETx.xml * STM32L162RETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/PeripheralPins.c b/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/PeripheralPins.c index 8dd7c36fd7..1d975f4cce 100644 --- a/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L151V(8-B)(H-T)x(A)_L152V(8-B)(H-T)x(A)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32L151V(8-B)Tx.xml, STM32L151V(8-B)TxA.xml * STM32L152V(8-B)Hx.xml, STM32L152V(8-B)HxA.xml * STM32L152V(8-B)Tx.xml, STM32L152V(8-B)TxA.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/PeripheralPins.c b/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/PeripheralPins.c index 39ac8c2165..50abd22fdc 100644 --- a/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/PeripheralPins.c +++ b/variants/STM32L1xx/L151VC(H-T)x(A)_L152VC(H-T)x(A)_L162VC(H-T)x(A)/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32L152VCTx.xml, STM32L152VCTxA.xml * STM32L162VCHx.xml, STM32L162VCTx.xml * STM32L162VCTxA.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151VD(T-Y)xX_L151VE(T-Y)_L152VDTxX_L152VE(T-Y)_L162VDYxX_L162VE(T-Y)/PeripheralPins.c b/variants/STM32L1xx/L151VD(T-Y)xX_L151VE(T-Y)_L152VDTxX_L152VE(T-Y)_L162VDYxX_L162VE(T-Y)/PeripheralPins.c index 9875f90193..1d40907918 100644 --- a/variants/STM32L1xx/L151VD(T-Y)xX_L151VE(T-Y)_L152VDTxX_L152VE(T-Y)_L162VDYxX_L162VE(T-Y)/PeripheralPins.c +++ b/variants/STM32L1xx/L151VD(T-Y)xX_L151VE(T-Y)_L152VDTxX_L152VE(T-Y)_L162VDYxX_L162VE(T-Y)/PeripheralPins.c @@ -16,7 +16,7 @@ * STM32L152VDTxX.xml, STM32L152VETx.xml * STM32L152VEYx.xml, STM32L162VDYxX.xml * STM32L162VETx.xml, STM32L162VEYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151VDT_L152VDT_L162VDT/PeripheralPins.c b/variants/STM32L1xx/L151VDT_L152VDT_L162VDT/PeripheralPins.c index d6ddd9d6f6..504aab081b 100644 --- a/variants/STM32L1xx/L151VDT_L152VDT_L162VDT/PeripheralPins.c +++ b/variants/STM32L1xx/L151VDT_L152VDT_L162VDT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151VDTx.xml, STM32L152VDTx.xml * STM32L162VDTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151ZCT_L152ZCT_L162ZCT/PeripheralPins.c b/variants/STM32L1xx/L151ZCT_L152ZCT_L162ZCT/PeripheralPins.c index ac4f6da612..4a89844d16 100644 --- a/variants/STM32L1xx/L151ZCT_L152ZCT_L162ZCT/PeripheralPins.c +++ b/variants/STM32L1xx/L151ZCT_L152ZCT_L162ZCT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151ZCTx.xml, STM32L152ZCTx.xml * STM32L162ZCTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151ZDT_L152ZDT_L162ZDT/PeripheralPins.c b/variants/STM32L1xx/L151ZDT_L152ZDT_L162ZDT/PeripheralPins.c index 2488a754dd..832630f1e4 100644 --- a/variants/STM32L1xx/L151ZDT_L152ZDT_L162ZDT/PeripheralPins.c +++ b/variants/STM32L1xx/L151ZDT_L152ZDT_L162ZDT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151ZDTx.xml, STM32L152ZDTx.xml * STM32L162ZDTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L1xx/L151ZET_L152ZET_L162ZET/PeripheralPins.c b/variants/STM32L1xx/L151ZET_L152ZET_L162ZET/PeripheralPins.c index 8168c172e2..fb763e414f 100644 --- a/variants/STM32L1xx/L151ZET_L152ZET_L162ZET/PeripheralPins.c +++ b/variants/STM32L1xx/L151ZET_L152ZET_L162ZET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L151ZETx.xml, STM32L152ZETx.xml * STM32L162ZETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PeripheralPins.c b/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PeripheralPins.c index d1bb9c65ee..0d48b0c685 100644 --- a/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L412C(8-B)(T-U)_L422CB(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L412C8Tx.xml, STM32L412C8Ux.xml * STM32L412CBTx.xml, STM32L412CBUx.xml * STM32L422CBTx.xml, STM32L422CBUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412CB(T-U)xP/PeripheralPins.c b/variants/STM32L4xx/L412CB(T-U)xP/PeripheralPins.c index 72c3977ce1..c8ec4038e3 100644 --- a/variants/STM32L4xx/L412CB(T-U)xP/PeripheralPins.c +++ b/variants/STM32L4xx/L412CB(T-U)xP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L412CBTxP.xml, STM32L412CBUxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PeripheralPins.c b/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PeripheralPins.c index 740b09fb0d..3685c61afd 100644 --- a/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L412K8Tx.xml, STM32L412K8Ux.xml * STM32L412KBTx.xml, STM32L412KBUx.xml * STM32L422KBTx.xml, STM32L422KBUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PeripheralPins.c b/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PeripheralPins.c index b933bfa8af..9783eb0baf 100644 --- a/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L412R(8-B)(I-T)_L422RB(I-T)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L412R8Ix.xml, STM32L412R8Tx.xml * STM32L412RBIx.xml, STM32L412RBTx.xml * STM32L422RBIx.xml, STM32L422RBTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412RB(I-T)xP/PeripheralPins.c b/variants/STM32L4xx/L412RB(I-T)xP/PeripheralPins.c index dde91dcf2b..859fc3d15f 100644 --- a/variants/STM32L4xx/L412RB(I-T)xP/PeripheralPins.c +++ b/variants/STM32L4xx/L412RB(I-T)xP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L412RBIxP.xml, STM32L412RBTxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PeripheralPins.c b/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PeripheralPins.c index bfff490db4..00a5a7ef3e 100644 --- a/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PeripheralPins.c +++ b/variants/STM32L4xx/L412T(8-B)Y_L422TBY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L412T8Yx.xml, STM32L412TBYx.xml * STM32L422TBYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L412TBYxP/PeripheralPins.c b/variants/STM32L4xx/L412TBYxP/PeripheralPins.c index 9d61667598..55ca58a759 100644 --- a/variants/STM32L4xx/L412TBYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L412TBYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L412TBYxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L431C(B-C)(T-U)/PeripheralPins.c b/variants/STM32L4xx/L431C(B-C)(T-U)/PeripheralPins.c index 98528aea73..a078126c92 100644 --- a/variants/STM32L4xx/L431C(B-C)(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L431C(B-C)(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L431C(B-C)Tx.xml, STM32L431C(B-C)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L431C(B-C)Y/PeripheralPins.c b/variants/STM32L4xx/L431C(B-C)Y/PeripheralPins.c index 1f50505f58..46251e06be 100644 --- a/variants/STM32L4xx/L431C(B-C)Y/PeripheralPins.c +++ b/variants/STM32L4xx/L431C(B-C)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L431C(B-C)Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L431K(B-C)U/PeripheralPins.c b/variants/STM32L4xx/L431K(B-C)U/PeripheralPins.c index 3bd27e30e7..2ab0419c20 100644 --- a/variants/STM32L4xx/L431K(B-C)U/PeripheralPins.c +++ b/variants/STM32L4xx/L431K(B-C)U/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L431K(B-C)Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PeripheralPins.c b/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PeripheralPins.c index 3c213bb47b..4eb2212e6d 100644 --- a/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PeripheralPins.c +++ b/variants/STM32L4xx/L431R(B-C)(I-T-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L431R(B-C)Ix.xml, STM32L431R(B-C)Tx.xml * STM32L431R(B-C)Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L431VC(I-T)/PeripheralPins.c b/variants/STM32L4xx/L431VC(I-T)/PeripheralPins.c index e617cf47cd..619f0fddef 100644 --- a/variants/STM32L4xx/L431VC(I-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L431VC(I-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L431VCIx.xml, STM32L431VCTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L432K(B-C)U_L442KCU/PeripheralPins.c b/variants/STM32L4xx/L432K(B-C)U_L442KCU/PeripheralPins.c index 7b199c1fba..1696b6ec2c 100644 --- a/variants/STM32L4xx/L432K(B-C)U_L442KCU/PeripheralPins.c +++ b/variants/STM32L4xx/L432K(B-C)U_L442KCU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L432K(B-C)Ux.xml, STM32L442KCUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PeripheralPins.c b/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PeripheralPins.c index 4e60396a8e..dd87ff612e 100644 --- a/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L433C(B-C)Tx.xml, STM32L433C(B-C)Ux.xml * STM32L443CCTx.xml, STM32L443CCUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c b/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c index 14c81ae1b4..6e856a9607 100644 --- a/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c +++ b/variants/STM32L4xx/L433C(B-C)Y_L443CC(F-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L433C(B-C)Yx.xml, STM32L443CCFx.xml * STM32L443CCYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PeripheralPins.c b/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PeripheralPins.c index 8aefafb665..f180f12d26 100644 --- a/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PeripheralPins.c +++ b/variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L433R(B-C)Ix.xml, STM32L433R(B-C)Tx.xml * STM32L433R(B-C)Yx.xml, STM32L443RCIx.xml * STM32L443RCTx.xml, STM32L443RCYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L433RCTxP/PeripheralPins.c b/variants/STM32L4xx/L433RCTxP/PeripheralPins.c index 5dfaf57790..6ec65c1693 100644 --- a/variants/STM32L4xx/L433RCTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L433RCTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L433RCTxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PeripheralPins.c b/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PeripheralPins.c index eba36aac48..e3573fa31d 100644 --- a/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L433VC(I-T)_L443VC(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L433VCIx.xml, STM32L433VCTx.xml * STM32L443VCIx.xml, STM32L443VCTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L451CCU_L451CE(T-U)/PeripheralPins.c b/variants/STM32L4xx/L451CCU_L451CE(T-U)/PeripheralPins.c index f89b191294..adee1b8fe1 100644 --- a/variants/STM32L4xx/L451CCU_L451CE(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L451CCU_L451CE(T-U)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L451C(C-E)Ux.xml, STM32L451CETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PeripheralPins.c b/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PeripheralPins.c index 63392763ef..18f112ad7c 100644 --- a/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PeripheralPins.c +++ b/variants/STM32L4xx/L451R(C-E)(I-T-Y)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L451R(C-E)Ix.xml, STM32L451R(C-E)Tx.xml * STM32L451R(C-E)Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L451V(C-E)(I-T)/PeripheralPins.c b/variants/STM32L4xx/L451V(C-E)(I-T)/PeripheralPins.c index 458db21d6c..4833480916 100644 --- a/variants/STM32L4xx/L451V(C-E)(I-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L451V(C-E)(I-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L451V(C-E)Ix.xml, STM32L451V(C-E)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PeripheralPins.c b/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PeripheralPins.c index dcee5c4a0e..f80fba7b54 100644 --- a/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L452CCU_L452CE(T-U)x(P)_L462CE(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L452C(C-E)Ux.xml, STM32L452CETx.xml * STM32L452CETxP.xml, STM32L462CETx.xml * STM32L462CEUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PeripheralPins.c b/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PeripheralPins.c index f0fdc597b6..6765cbe55e 100644 --- a/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PeripheralPins.c +++ b/variants/STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32L452R(C-E)Yx.xml, STM32L452REYxP.xml * STM32L462REIx.xml, STM32L462RETx.xml * STM32L462REYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L452RETxP/PeripheralPins.c b/variants/STM32L4xx/L452RETxP/PeripheralPins.c index ab91fea0ba..5d34e501c3 100644 --- a/variants/STM32L4xx/L452RETxP/PeripheralPins.c +++ b/variants/STM32L4xx/L452RETxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L452RETxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PeripheralPins.c b/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PeripheralPins.c index 2e1b0c461f..bae1c86542 100644 --- a/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L452V(C-E)(I-T)_L462VE(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L452V(C-E)Ix.xml, STM32L452V(C-E)Tx.xml * STM32L462VEIx.xml, STM32L462VETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L471Q(E-G)I/PeripheralPins.c b/variants/STM32L4xx/L471Q(E-G)I/PeripheralPins.c index 63fadac966..c73e569119 100644 --- a/variants/STM32L4xx/L471Q(E-G)I/PeripheralPins.c +++ b/variants/STM32L4xx/L471Q(E-G)I/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L471Q(E-G)Ix.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L471R(E-G)T/PeripheralPins.c b/variants/STM32L4xx/L471R(E-G)T/PeripheralPins.c index 38dcc2b15a..a709a7c016 100644 --- a/variants/STM32L4xx/L471R(E-G)T/PeripheralPins.c +++ b/variants/STM32L4xx/L471R(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L471R(E-G)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L471V(E-G)T/PeripheralPins.c b/variants/STM32L4xx/L471V(E-G)T/PeripheralPins.c index c72bf3c399..9ee28e3c28 100644 --- a/variants/STM32L4xx/L471V(E-G)T/PeripheralPins.c +++ b/variants/STM32L4xx/L471V(E-G)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L471V(E-G)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L471Z(E-G)(J-T)/PeripheralPins.c b/variants/STM32L4xx/L471Z(E-G)(J-T)/PeripheralPins.c index 59ba498167..d8cc1f9565 100644 --- a/variants/STM32L4xx/L471Z(E-G)(J-T)/PeripheralPins.c +++ b/variants/STM32L4xx/L471Z(E-G)(J-T)/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L471Z(E-G)Jx.xml, STM32L471Z(E-G)Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PeripheralPins.c b/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PeripheralPins.c index 99ebc0a2d8..11d04d3b88 100644 --- a/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PeripheralPins.c +++ b/variants/STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L475R(C-E-G)Tx.xml, STM32L476R(C-E-G)Tx.xml * STM32L486RGTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PeripheralPins.c b/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PeripheralPins.c index f0eb4b1152..f9fc1afa0a 100644 --- a/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PeripheralPins.c +++ b/variants/STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L475V(C-E-G)Tx.xml, STM32L476V(C-E-G)Tx.xml * STM32L486VGTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PeripheralPins.c b/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PeripheralPins.c index 25078f6a0a..e295750f00 100644 --- a/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PeripheralPins.c +++ b/variants/STM32L4xx/L476J(E-G)Y_L485J(C-E)Y_L486JGY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L476J(E-G)Yx.xml, STM32L485J(C-E)Yx.xml * STM32L486JGYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476JGYxP/PeripheralPins.c b/variants/STM32L4xx/L476JGYxP/PeripheralPins.c index 65bbb9daa7..fe3ea2b743 100644 --- a/variants/STM32L4xx/L476JGYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L476JGYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L476JGYxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476M(E-G)Y/PeripheralPins.c b/variants/STM32L4xx/L476M(E-G)Y/PeripheralPins.c index c21c7a3e77..083cd8ba6e 100644 --- a/variants/STM32L4xx/L476M(E-G)Y/PeripheralPins.c +++ b/variants/STM32L4xx/L476M(E-G)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L476M(E-G)Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PeripheralPins.c b/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PeripheralPins.c index 9db5c22bc3..92054701e7 100644 --- a/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PeripheralPins.c +++ b/variants/STM32L4xx/L476QEI_L476QGIx(P)_L486QGI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L476Q(E-G)Ix.xml, STM32L476QGIxP.xml * STM32L486QGIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476VGYxP/PeripheralPins.c b/variants/STM32L4xx/L476VGYxP/PeripheralPins.c index dc099d9852..5a240592b1 100644 --- a/variants/STM32L4xx/L476VGYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L476VGYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L476VGYxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PeripheralPins.c b/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PeripheralPins.c index 67c8b30299..7177927d46 100644 --- a/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PeripheralPins.c +++ b/variants/STM32L4xx/L476ZET_L476ZG(J-T)_L486ZGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L476Z(E-G)Tx.xml, STM32L476ZGJx.xml * STM32L486ZGTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L476ZGTxP/PeripheralPins.c b/variants/STM32L4xx/L476ZGTxP/PeripheralPins.c index cd9dedac01..6531bb6d1a 100644 --- a/variants/STM32L4xx/L476ZGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L476ZGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L476ZGTxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PeripheralPins.c b/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PeripheralPins.c index 57cd4fdb98..9c7ed15684 100644 --- a/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PeripheralPins.c +++ b/variants/STM32L4xx/L496A(E-G)I_L4A6AGI/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496A(E-G)Ix.xml, STM32L4A6AGIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PeripheralPins.c b/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PeripheralPins.c index 3ed585f837..a0498818cb 100644 --- a/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496AGIxP_L4A6AGIxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496AGIxP.xml, STM32L4A6AGIxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PeripheralPins.c b/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PeripheralPins.c index 08613996dd..19e3c27e4b 100644 --- a/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PeripheralPins.c +++ b/variants/STM32L4xx/L496QEI_L496QGIx(S)_L4A6QGI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L496Q(E-G)Ix.xml, STM32L496QGIxS.xml * STM32L4A6QGIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PeripheralPins.c b/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PeripheralPins.c index 895fba91a3..a1f0196269 100644 --- a/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496QGIxP_L4A6QGIxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496QGIxP.xml, STM32L4A6QGIxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PeripheralPins.c b/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PeripheralPins.c index fa84d47524..9f6c56bf3a 100644 --- a/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PeripheralPins.c +++ b/variants/STM32L4xx/L496R(E-G)T_L4A6RGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496R(E-G)Tx.xml, STM32L4A6RGTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496RGTxP/PeripheralPins.c b/variants/STM32L4xx/L496RGTxP/PeripheralPins.c index 3ccf8d6830..db7dbf2fac 100644 --- a/variants/STM32L4xx/L496RGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496RGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496RGTxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PeripheralPins.c b/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PeripheralPins.c index 2a891ef668..6fae04e458 100644 --- a/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PeripheralPins.c +++ b/variants/STM32L4xx/L496V(E-G)T_L4A6VGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496V(E-G)Tx.xml, STM32L4A6VGTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PeripheralPins.c b/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PeripheralPins.c index c2857ca0fc..6902d09ce0 100644 --- a/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496VGTxP_L4A6VGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496VGTxP.xml, STM32L4A6VGTxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496VGY_L4A6VGY/PeripheralPins.c b/variants/STM32L4xx/L496VGY_L4A6VGY/PeripheralPins.c index b260e6805d..23abd93f78 100644 --- a/variants/STM32L4xx/L496VGY_L4A6VGY/PeripheralPins.c +++ b/variants/STM32L4xx/L496VGY_L4A6VGY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496VGYx.xml, STM32L4A6VGYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PeripheralPins.c b/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PeripheralPins.c index e8685a640a..37695288f5 100644 --- a/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496VGYxP_L4A6VGYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496VGYxP.xml, STM32L4A6VGYxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496WGYxP/PeripheralPins.c b/variants/STM32L4xx/L496WGYxP/PeripheralPins.c index 1aae3f7df5..56351d6984 100644 --- a/variants/STM32L4xx/L496WGYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496WGYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496WGYxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PeripheralPins.c b/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PeripheralPins.c index aa47ba7ee7..f54bf90b10 100644 --- a/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PeripheralPins.c +++ b/variants/STM32L4xx/L496Z(E-G)T_L4A6ZGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496Z(E-G)Tx.xml, STM32L4A6ZGTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PeripheralPins.c b/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PeripheralPins.c index f5fac1fc0c..75a7425655 100644 --- a/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L496ZGTxP_L4A6ZGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L496ZGTxP.xml, STM32L4A6ZGTxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c b/variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c index a0e54c4a65..0e5f0fc30f 100644 --- a/variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4A6RGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4A6RGTxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c b/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c index b239ee939f..3846a16519 100644 --- a/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5A(G-E)I_L4Q5AGI/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5A(G-E)Ix.xml, STM32L4Q5AGIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c b/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c index 6f7c00215a..9b086e2f05 100644 --- a/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5AGIxP_L4Q5AGIxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5AGIxP.xml, STM32L4Q5AGIxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PeripheralPins.c b/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PeripheralPins.c index 321b436874..cfede01332 100644 --- a/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5C(E-G)(T-U)_L4Q5CG(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4P5C(G-E)Tx.xml, STM32L4P5C(G-E)Ux.xml * STM32L4Q5CGTx.xml, STM32L4Q5CGUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PeripheralPins.c b/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PeripheralPins.c index f35ddc74b5..7c6bb54078 100644 --- a/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5CG(T-U)xP_L4Q5CG(T-U)xP/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4P5CGTxP.xml, STM32L4P5CGUxP.xml * STM32L4Q5CGTxP.xml, STM32L4Q5CGUxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c b/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c index 0167a92972..c5adf3e021 100644 --- a/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5Q(G-E)I_L4Q5QGI/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5Q(G-E)Ix.xml, STM32L4Q5QGIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c b/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c index 7a6cc8a5ce..208d26cfc8 100644 --- a/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5QGIx(P-S)_L4Q5QGIxP/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4P5QGIxP.xml, STM32L4P5QGIxS.xml * STM32L4Q5QGIxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PeripheralPins.c b/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PeripheralPins.c index 5b72cc48d0..6a6bb4be5a 100644 --- a/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5R(G-E)T_L4Q5RGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5R(G-E)Tx.xml, STM32L4Q5RGTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c b/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c index 3937c8e811..a38e85a580 100644 --- a/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5RGTxP_L4Q5RGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5RGTxP.xml, STM32L4Q5RGTxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c b/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c index 5005b6059e..6fac0e8f26 100644 --- a/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5V(G-E)T_L4Q5VGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5V(G-E)Tx.xml, STM32L4Q5VGTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c b/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c index 9bd18dfbf2..a3e2d9a5b9 100644 --- a/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5V(G-E)Y_L4Q5VGY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5V(G-E)Yx.xml, STM32L4Q5VGYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c b/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c index 792ad794b5..eb01804fad 100644 --- a/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5VGTxP_L4Q5VGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5VGTxP.xml, STM32L4Q5VGTxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c b/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c index 0c114822c0..3dc6559831 100644 --- a/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5VGYxP_L4Q5VGYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5VGYxP.xml, STM32L4Q5VGYxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c b/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c index 4dce32e6b7..95753617f4 100644 --- a/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5Z(G-E)T_L4Q5ZGT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5Z(G-E)Tx.xml, STM32L4Q5ZGTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c b/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c index 0e13c8286f..f296c43fe0 100644 --- a/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4P5ZGTxP_L4Q5ZGTxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4P5ZGTxP.xml, STM32L4Q5ZGTxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PeripheralPins.c b/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PeripheralPins.c index 9bea3f735a..2f1fe0959e 100644 --- a/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5AGI_L4R5AIIx(P)_L4R7AII_L4S5AII_L4S7AII/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32L4R5A(G-I)Ix.xml, STM32L4R5AIIxP.xml * STM32L4R7AIIx.xml, STM32L4S5AIIx.xml * STM32L4S7AIIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PeripheralPins.c b/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PeripheralPins.c index 03fe4d2b54..e0eb229820 100644 --- a/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5QGIx(S)_L4R5QIIx(P)_L4S5QII/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4R5Q(G-I)Ix.xml, STM32L4R5QGIxS.xml * STM32L4R5QIIxP.xml, STM32L4S5QIIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PeripheralPins.c b/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PeripheralPins.c index f98e4f7352..2963eadb76 100644 --- a/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4R5V(G-I)Tx.xml, STM32L4R7VITx.xml * STM32L4S5VITx.xml, STM32L4S7VITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PeripheralPins.c b/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PeripheralPins.c index 707a113c05..e5b1991587 100644 --- a/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4R5Z(G-I)Tx.xml, STM32L4R7ZITx.xml * STM32L4S5ZITx.xml, STM32L4S7ZITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PeripheralPins.c b/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PeripheralPins.c index b2f9ef7059..450d85b387 100644 --- a/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L4R5Z(G-I)Yx.xml, STM32L4R9Z(G-I)Yx.xml * STM32L4S5ZIYx.xml, STM32L4S9ZIYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c b/variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c index 659827b24d..8769032867 100644 --- a/variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4R5ZITxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R5ZITxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PeripheralPins.c b/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PeripheralPins.c index 4b0122cd21..8a49181013 100644 --- a/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PeripheralPins.c +++ b/variants/STM32L4xx/L4R9A(G-I)I_L4S9AII/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R9A(G-I)Ix.xml, STM32L4S9AIIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PeripheralPins.c b/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PeripheralPins.c index 538c663fbc..4c1c1e6e73 100644 --- a/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PeripheralPins.c +++ b/variants/STM32L4xx/L4R9V(G-I)T_L4S9VIT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R9V(G-I)Tx.xml, STM32L4S9VITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c b/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c index 68eddfe798..62f1a3258b 100644 --- a/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c +++ b/variants/STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R9Z(G-I)Jx.xml, STM32L4S9ZIJx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c b/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c index fa13c44c1a..68e49c6cc0 100644 --- a/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c +++ b/variants/STM32L4xx/L4R9Z(G-I)T_L4S9ZIT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R9Z(G-I)Tx.xml, STM32L4S9ZITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c b/variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c index cb4d71b513..c973553aaa 100644 --- a/variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c +++ b/variants/STM32L4xx/L4R9ZIYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L4R9ZIYxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552C(C-E)(T-U)_L562CE(T-U)/PeripheralPins.c b/variants/STM32L5xx/L552C(C-E)(T-U)_L562CE(T-U)/PeripheralPins.c index 19d2962f26..bc39299c17 100644 --- a/variants/STM32L5xx/L552C(C-E)(T-U)_L562CE(T-U)/PeripheralPins.c +++ b/variants/STM32L5xx/L552C(C-E)(T-U)_L562CE(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L552C(C-E)Tx.xml, STM32L552C(C-E)Ux.xml * STM32L562CETx.xml, STM32L562CEUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552CE(T-U)xP_L562CE(T-U)xP/PeripheralPins.c b/variants/STM32L5xx/L552CE(T-U)xP_L562CE(T-U)xP/PeripheralPins.c index a9e77aa46d..24f19f6259 100644 --- a/variants/STM32L5xx/L552CE(T-U)xP_L562CE(T-U)xP/PeripheralPins.c +++ b/variants/STM32L5xx/L552CE(T-U)xP_L562CE(T-U)xP/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32L552CETxP.xml, STM32L552CEUxP.xml * STM32L562CETxP.xml, STM32L562CEUxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552MEYxP_L562MEYxP/PeripheralPins.c b/variants/STM32L5xx/L552MEYxP_L562MEYxP/PeripheralPins.c index 3a5cf5382c..c26d46e63a 100644 --- a/variants/STM32L5xx/L552MEYxP_L562MEYxP/PeripheralPins.c +++ b/variants/STM32L5xx/L552MEYxP_L562MEYxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552MEYxP.xml, STM32L562MEYxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552MEYxQ_L562MEYxQ/PeripheralPins.c b/variants/STM32L5xx/L552MEYxQ_L562MEYxQ/PeripheralPins.c index c3d6870fa2..02a4024503 100644 --- a/variants/STM32L5xx/L552MEYxQ_L562MEYxQ/PeripheralPins.c +++ b/variants/STM32L5xx/L552MEYxQ_L562MEYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552MEYxQ.xml, STM32L562MEYxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins.c b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins.c index 4bc52d1e19..41055a67d1 100644 --- a/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins.c +++ b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552Q(C-E)IxQ.xml, STM32L562QEIxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552QEI_L562QEI/PeripheralPins.c b/variants/STM32L5xx/L552QEI_L562QEI/PeripheralPins.c index 0b36322065..158569fd52 100644 --- a/variants/STM32L5xx/L552QEI_L562QEI/PeripheralPins.c +++ b/variants/STM32L5xx/L552QEI_L562QEI/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552QEIx.xml, STM32L562QEIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552QEIxP_L562QEIxP/PeripheralPins.c b/variants/STM32L5xx/L552QEIxP_L562QEIxP/PeripheralPins.c index 73c53c0f0f..48b3a8bdba 100644 --- a/variants/STM32L5xx/L552QEIxP_L562QEIxP/PeripheralPins.c +++ b/variants/STM32L5xx/L552QEIxP_L562QEIxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552QEIxP.xml, STM32L562QEIxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552R(C-E)T_L562RET/PeripheralPins.c b/variants/STM32L5xx/L552R(C-E)T_L562RET/PeripheralPins.c index 6e7065768b..aad03a3834 100644 --- a/variants/STM32L5xx/L552R(C-E)T_L562RET/PeripheralPins.c +++ b/variants/STM32L5xx/L552R(C-E)T_L562RET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552R(C-E)Tx.xml, STM32L562RETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552RETxP_L562RETxP/PeripheralPins.c b/variants/STM32L5xx/L552RETxP_L562RETxP/PeripheralPins.c index fe0287ab18..29c456b43a 100644 --- a/variants/STM32L5xx/L552RETxP_L562RETxP/PeripheralPins.c +++ b/variants/STM32L5xx/L552RETxP_L562RETxP/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552RETxP.xml, STM32L562RETxP.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552RETxQ_L562RETxQ/PeripheralPins.c b/variants/STM32L5xx/L552RETxQ_L562RETxQ/PeripheralPins.c index fcae870da3..5c6d1d1235 100644 --- a/variants/STM32L5xx/L552RETxQ_L562RETxQ/PeripheralPins.c +++ b/variants/STM32L5xx/L552RETxQ_L562RETxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552RETxQ.xml, STM32L562RETxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552V(C-E)TxQ_L562VETxQ/PeripheralPins.c b/variants/STM32L5xx/L552V(C-E)TxQ_L562VETxQ/PeripheralPins.c index 5b7162bb09..e3f9cf6b3c 100644 --- a/variants/STM32L5xx/L552V(C-E)TxQ_L562VETxQ/PeripheralPins.c +++ b/variants/STM32L5xx/L552V(C-E)TxQ_L562VETxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552V(C-E)TxQ.xml, STM32L562VETxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552VET_L562VET/PeripheralPins.c b/variants/STM32L5xx/L552VET_L562VET/PeripheralPins.c index 869d0bae9e..814f6b122f 100644 --- a/variants/STM32L5xx/L552VET_L562VET/PeripheralPins.c +++ b/variants/STM32L5xx/L552VET_L562VET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552VETx.xml, STM32L562VETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ/PeripheralPins.c b/variants/STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ/PeripheralPins.c index a7db7427c3..0a86046ae4 100644 --- a/variants/STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ/PeripheralPins.c +++ b/variants/STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552Z(C-E)TxQ.xml, STM32L562ZETxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32L5xx/L552ZET_L562ZET/PeripheralPins.c b/variants/STM32L5xx/L552ZET_L562ZET/PeripheralPins.c index 94e7716317..5722f20c0c 100644 --- a/variants/STM32L5xx/L552ZET_L562ZET/PeripheralPins.c +++ b/variants/STM32L5xx/L552ZET_L562ZET/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32L552ZETx.xml, STM32L562ZETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP151AA(B-D)_MP151CA(B-D)_MP151DA(B-D)_MP151FA(B-D)/PeripheralPins.c b/variants/STM32MP1xx/MP151AA(B-D)_MP151CA(B-D)_MP151DA(B-D)_MP151FA(B-D)/PeripheralPins.c index 62ab2c6a13..ffc97f97ec 100644 --- a/variants/STM32MP1xx/MP151AA(B-D)_MP151CA(B-D)_MP151DA(B-D)_MP151FA(B-D)/PeripheralPins.c +++ b/variants/STM32MP1xx/MP151AA(B-D)_MP151CA(B-D)_MP151DA(B-D)_MP151FA(B-D)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32MP151CABx.xml, STM32MP151CADx.xml * STM32MP151DABx.xml, STM32MP151DADx.xml * STM32MP151FABx.xml, STM32MP151FADx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP151AAA_MP151CAA_MP151DAA_MP151FAA/PeripheralPins.c b/variants/STM32MP1xx/MP151AAA_MP151CAA_MP151DAA_MP151FAA/PeripheralPins.c index f4f8cf013a..25cad2c752 100644 --- a/variants/STM32MP1xx/MP151AAA_MP151CAA_MP151DAA_MP151FAA/PeripheralPins.c +++ b/variants/STM32MP1xx/MP151AAA_MP151CAA_MP151DAA_MP151FAA/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32MP151AAAx.xml, STM32MP151CAAx.xml * STM32MP151DAAx.xml, STM32MP151FAAx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP151AAC_MP151CAC_MP151DAC_MP151FAC/PeripheralPins.c b/variants/STM32MP1xx/MP151AAC_MP151CAC_MP151DAC_MP151FAC/PeripheralPins.c index b7fccb933d..3516b5b9e2 100644 --- a/variants/STM32MP1xx/MP151AAC_MP151CAC_MP151DAC_MP151FAC/PeripheralPins.c +++ b/variants/STM32MP1xx/MP151AAC_MP151CAC_MP151DAC_MP151FAC/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32MP151AACx.xml, STM32MP151CACx.xml * STM32MP151DACx.xml, STM32MP151FACx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP153AA(B-D)_MP153CA(B-D)_MP153DA(B-D)_MP153FA(B-D)_MP157AA(B-D)_MP157CA(B-D)_MP157DA(B-D)_MP157FA(B-D)/PeripheralPins.c b/variants/STM32MP1xx/MP153AA(B-D)_MP153CA(B-D)_MP153DA(B-D)_MP153FA(B-D)_MP157AA(B-D)_MP157CA(B-D)_MP157DA(B-D)_MP157FA(B-D)/PeripheralPins.c index 1401c1adf3..fc1e306ab8 100644 --- a/variants/STM32MP1xx/MP153AA(B-D)_MP153CA(B-D)_MP153DA(B-D)_MP153FA(B-D)_MP157AA(B-D)_MP157CA(B-D)_MP157DA(B-D)_MP157FA(B-D)/PeripheralPins.c +++ b/variants/STM32MP1xx/MP153AA(B-D)_MP153CA(B-D)_MP153DA(B-D)_MP153FA(B-D)_MP157AA(B-D)_MP157CA(B-D)_MP157DA(B-D)_MP157FA(B-D)/PeripheralPins.c @@ -19,7 +19,7 @@ * STM32MP157CABx.xml, STM32MP157CADx.xml * STM32MP157DABx.xml, STM32MP157DADx.xml * STM32MP157FABx.xml, STM32MP157FADx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP153AAA_MP153CAA_MP153DAA_MP153FAA_MP157AAA_MP157CAA_MP157DAA_MP157FAA/PeripheralPins.c b/variants/STM32MP1xx/MP153AAA_MP153CAA_MP153DAA_MP153FAA_MP157AAA_MP157CAA_MP157DAA_MP157FAA/PeripheralPins.c index 5c4ce046f0..9f76b81093 100644 --- a/variants/STM32MP1xx/MP153AAA_MP153CAA_MP153DAA_MP153FAA_MP157AAA_MP157CAA_MP157DAA_MP157FAA/PeripheralPins.c +++ b/variants/STM32MP1xx/MP153AAA_MP153CAA_MP153DAA_MP153FAA_MP157AAA_MP157CAA_MP157DAA_MP157FAA/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32MP153DAAx.xml, STM32MP153FAAx.xml * STM32MP157AAAx.xml, STM32MP157CAAx.xml * STM32MP157DAAx.xml, STM32MP157FAAx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/PeripheralPins.c b/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/PeripheralPins.c index 2d1855187e..092a5fd601 100644 --- a/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/PeripheralPins.c +++ b/variants/STM32MP1xx/MP153AAC_MP153CAC_MP153DAC_MP153FAC_MP157AAC_MP157CAC_MP157DAC_MP157FAC/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32MP153DACx.xml, STM32MP153FACx.xml * STM32MP157AACx.xml, STM32MP157CACx.xml * STM32MP157DACx.xml, STM32MP157FACx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U031C(6-8)(T-U)/PeripheralPins.c b/variants/STM32U0xx/U031C(6-8)(T-U)/PeripheralPins.c index d3adb0dc52..609c2988d4 100644 --- a/variants/STM32U0xx/U031C(6-8)(T-U)/PeripheralPins.c +++ b/variants/STM32U0xx/U031C(6-8)(T-U)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U031C6Tx.xml, STM32U031C6Ux.xml * STM32U031C8Tx.xml, STM32U031C8Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U031F(4-6-8)P/PeripheralPins.c b/variants/STM32U0xx/U031F(4-6-8)P/PeripheralPins.c index 223c0be2dc..ba7f325a6a 100644 --- a/variants/STM32U0xx/U031F(4-6-8)P/PeripheralPins.c +++ b/variants/STM32U0xx/U031F(4-6-8)P/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U031F4Px.xml, STM32U031F6Px.xml * STM32U031F8Px.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U031G(6-8)Y/PeripheralPins.c b/variants/STM32U0xx/U031G(6-8)Y/PeripheralPins.c index 9299bb4e3c..69c50ec91d 100644 --- a/variants/STM32U0xx/U031G(6-8)Y/PeripheralPins.c +++ b/variants/STM32U0xx/U031G(6-8)Y/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U031G6Yx.xml, STM32U031G8Yx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U031K(4-6-8)U/PeripheralPins.c b/variants/STM32U0xx/U031K(4-6-8)U/PeripheralPins.c index 5445fe5e8d..bdd349db86 100644 --- a/variants/STM32U0xx/U031K(4-6-8)U/PeripheralPins.c +++ b/variants/STM32U0xx/U031K(4-6-8)U/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U031K4Ux.xml, STM32U031K6Ux.xml * STM32U031K8Ux.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U031R(6-8)(I-T)/PeripheralPins.c b/variants/STM32U0xx/U031R(6-8)(I-T)/PeripheralPins.c index 41848f1e09..334cc35d71 100644 --- a/variants/STM32U0xx/U031R(6-8)(I-T)/PeripheralPins.c +++ b/variants/STM32U0xx/U031R(6-8)(I-T)/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U031R6Ix.xml, STM32U031R6Tx.xml * STM32U031R8Ix.xml, STM32U031R8Tx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)/PeripheralPins.c b/variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)/PeripheralPins.c index 9e10e5dcb5..f7df0dcf18 100644 --- a/variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)/PeripheralPins.c +++ b/variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32U073CBTx.xml, STM32U073CBUx.xml * STM32U073CCTx.xml, STM32U073CCUx.xml * STM32U083CCTx.xml, STM32U083CCUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073H(8-B-C)Y_U083HCY/PeripheralPins.c b/variants/STM32U0xx/U073H(8-B-C)Y_U083HCY/PeripheralPins.c index 4b842ae521..3334532d5e 100644 --- a/variants/STM32U0xx/U073H(8-B-C)Y_U083HCY/PeripheralPins.c +++ b/variants/STM32U0xx/U073H(8-B-C)Y_U083HCY/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U073H8Yx.xml, STM32U073HBYx.xml * STM32U073HCYx.xml, STM32U083HCYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073K(8-B-C)U_U083KCU/PeripheralPins.c b/variants/STM32U0xx/U073K(8-B-C)U_U083KCU/PeripheralPins.c index 970c541519..ccf9dc686d 100644 --- a/variants/STM32U0xx/U073K(8-B-C)U_U083KCU/PeripheralPins.c +++ b/variants/STM32U0xx/U073K(8-B-C)U_U083KCU/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U073K8Ux.xml, STM32U073KBUx.xml * STM32U073KCUx.xml, STM32U083KCUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073M(8-B-C)I_U083MCI/PeripheralPins.c b/variants/STM32U0xx/U073M(8-B-C)I_U083MCI/PeripheralPins.c index dacd6d9002..dcf567b4cc 100644 --- a/variants/STM32U0xx/U073M(8-B-C)I_U083MCI/PeripheralPins.c +++ b/variants/STM32U0xx/U073M(8-B-C)I_U083MCI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U073M8Ix.xml, STM32U073MBIx.xml * STM32U073MCIx.xml, STM32U083MCIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073M(8-B-C)T_U083MCT/PeripheralPins.c b/variants/STM32U0xx/U073M(8-B-C)T_U083MCT/PeripheralPins.c index 2b4c40f15f..571e3ffe21 100644 --- a/variants/STM32U0xx/U073M(8-B-C)T_U083MCT/PeripheralPins.c +++ b/variants/STM32U0xx/U073M(8-B-C)T_U083MCT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U073M8Tx.xml, STM32U073MBTx.xml * STM32U073MCTx.xml, STM32U083MCTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)/PeripheralPins.c b/variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)/PeripheralPins.c index e2f8e92908..9d7feb0726 100644 --- a/variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)/PeripheralPins.c +++ b/variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32U073RBIx.xml, STM32U073RBTx.xml * STM32U073RCIx.xml, STM32U073RCTx.xml * STM32U083RCIx.xml, STM32U083RCTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375C(E-G)(T-U)_U385CG(T-U)/PeripheralPins.c b/variants/STM32U3xx/U375C(E-G)(T-U)_U385CG(T-U)/PeripheralPins.c index ac1b77c923..3082de66ba 100644 --- a/variants/STM32U3xx/U375C(E-G)(T-U)_U385CG(T-U)/PeripheralPins.c +++ b/variants/STM32U3xx/U375C(E-G)(T-U)_U385CG(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U375CETx.xml, STM32U375CEUx.xml * STM32U375CGTx.xml, STM32U375CGUx.xml * STM32U385CGTx.xml, STM32U385CGUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375C(E-G)(T-U)_U385CG(T-U)/boards_entry.txt b/variants/STM32U3xx/U375C(E-G)(T-U)_U385CG(T-U)/boards_entry.txt index b1e951d53b..6984b6454c 100644 --- a/variants/STM32U3xx/U375C(E-G)(T-U)_U385CG(T-U)/boards_entry.txt +++ b/variants/STM32U3xx/U375C(E-G)(T-U)_U385CG(T-U)/boards_entry.txt @@ -10,7 +10,7 @@ GenU3.menu.pnum.GENERIC_U375CETX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375CETX.build.board=GENERIC_U375CETX GenU3.menu.pnum.GENERIC_U375CETX.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375CETX.build.variant=STM32U3xx/U375C(E-G)(T-U)_U385CG(T-U) -GenU3.menu.pnum.GENERIC_U375CETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375CETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375CEUx GenU3.menu.pnum.GENERIC_U375CEUX=Generic U375CEUx @@ -19,7 +19,7 @@ GenU3.menu.pnum.GENERIC_U375CEUX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375CEUX.build.board=GENERIC_U375CEUX GenU3.menu.pnum.GENERIC_U375CEUX.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375CEUX.build.variant=STM32U3xx/U375C(E-G)(T-U)_U385CG(T-U) -GenU3.menu.pnum.GENERIC_U375CEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375CEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375CGTx GenU3.menu.pnum.GENERIC_U375CGTX=Generic U375CGTx @@ -28,7 +28,7 @@ GenU3.menu.pnum.GENERIC_U375CGTX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375CGTX.build.board=GENERIC_U375CGTX GenU3.menu.pnum.GENERIC_U375CGTX.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375CGTX.build.variant=STM32U3xx/U375C(E-G)(T-U)_U385CG(T-U) -GenU3.menu.pnum.GENERIC_U375CGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375CGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375CGUx GenU3.menu.pnum.GENERIC_U375CGUX=Generic U375CGUx @@ -37,7 +37,7 @@ GenU3.menu.pnum.GENERIC_U375CGUX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375CGUX.build.board=GENERIC_U375CGUX GenU3.menu.pnum.GENERIC_U375CGUX.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375CGUX.build.variant=STM32U3xx/U375C(E-G)(T-U)_U385CG(T-U) -GenU3.menu.pnum.GENERIC_U375CGUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375CGUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U385CGTx GenU3.menu.pnum.GENERIC_U385CGTX=Generic U385CGTx @@ -46,7 +46,7 @@ GenU3.menu.pnum.GENERIC_U385CGTX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U385CGTX.build.board=GENERIC_U385CGTX GenU3.menu.pnum.GENERIC_U385CGTX.build.product_line=STM32U385xx GenU3.menu.pnum.GENERIC_U385CGTX.build.variant=STM32U3xx/U375C(E-G)(T-U)_U385CG(T-U) -GenU3.menu.pnum.GENERIC_U385CGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U385CGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd # Generic U385CGUx GenU3.menu.pnum.GENERIC_U385CGUX=Generic U385CGUx @@ -55,5 +55,5 @@ GenU3.menu.pnum.GENERIC_U385CGUX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U385CGUX.build.board=GENERIC_U385CGUX GenU3.menu.pnum.GENERIC_U385CGUX.build.product_line=STM32U385xx GenU3.menu.pnum.GENERIC_U385CGUX.build.variant=STM32U3xx/U375C(E-G)(T-U)_U385CG(T-U) -GenU3.menu.pnum.GENERIC_U385CGUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U385CGUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd diff --git a/variants/STM32U3xx/U375C(E-G)(T-U)xQ_U385CG(T-U)xQ/PeripheralPins.c b/variants/STM32U3xx/U375C(E-G)(T-U)xQ_U385CG(T-U)xQ/PeripheralPins.c index 7de8df160e..b4b841847f 100644 --- a/variants/STM32U3xx/U375C(E-G)(T-U)xQ_U385CG(T-U)xQ/PeripheralPins.c +++ b/variants/STM32U3xx/U375C(E-G)(T-U)xQ_U385CG(T-U)xQ/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U375CETxQ.xml, STM32U375CEUxQ.xml * STM32U375CGTxQ.xml, STM32U375CGUxQ.xml * STM32U385CGTxQ.xml, STM32U385CGUxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375C(E-G)(T-U)xQ_U385CG(T-U)xQ/boards_entry.txt b/variants/STM32U3xx/U375C(E-G)(T-U)xQ_U385CG(T-U)xQ/boards_entry.txt index 77de4bdd85..d28bfde641 100644 --- a/variants/STM32U3xx/U375C(E-G)(T-U)xQ_U385CG(T-U)xQ/boards_entry.txt +++ b/variants/STM32U3xx/U375C(E-G)(T-U)xQ_U385CG(T-U)xQ/boards_entry.txt @@ -10,7 +10,7 @@ GenU3.menu.pnum.GENERIC_U375CETXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375CETXQ.build.board=GENERIC_U375CETXQ GenU3.menu.pnum.GENERIC_U375CETXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375CETXQ.build.variant=STM32U3xx/U375C(E-G)(T-U)xQ_U385CG(T-U)xQ -GenU3.menu.pnum.GENERIC_U375CETXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375CETXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375CEUxQ GenU3.menu.pnum.GENERIC_U375CEUXQ=Generic U375CEUxQ @@ -19,7 +19,7 @@ GenU3.menu.pnum.GENERIC_U375CEUXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375CEUXQ.build.board=GENERIC_U375CEUXQ GenU3.menu.pnum.GENERIC_U375CEUXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375CEUXQ.build.variant=STM32U3xx/U375C(E-G)(T-U)xQ_U385CG(T-U)xQ -GenU3.menu.pnum.GENERIC_U375CEUXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375CEUXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375CGTxQ GenU3.menu.pnum.GENERIC_U375CGTXQ=Generic U375CGTxQ @@ -28,7 +28,7 @@ GenU3.menu.pnum.GENERIC_U375CGTXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375CGTXQ.build.board=GENERIC_U375CGTXQ GenU3.menu.pnum.GENERIC_U375CGTXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375CGTXQ.build.variant=STM32U3xx/U375C(E-G)(T-U)xQ_U385CG(T-U)xQ -GenU3.menu.pnum.GENERIC_U375CGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375CGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375CGUxQ GenU3.menu.pnum.GENERIC_U375CGUXQ=Generic U375CGUxQ @@ -37,7 +37,7 @@ GenU3.menu.pnum.GENERIC_U375CGUXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375CGUXQ.build.board=GENERIC_U375CGUXQ GenU3.menu.pnum.GENERIC_U375CGUXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375CGUXQ.build.variant=STM32U3xx/U375C(E-G)(T-U)xQ_U385CG(T-U)xQ -GenU3.menu.pnum.GENERIC_U375CGUXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375CGUXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U385CGTxQ GenU3.menu.pnum.GENERIC_U385CGTXQ=Generic U385CGTxQ @@ -46,7 +46,7 @@ GenU3.menu.pnum.GENERIC_U385CGTXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U385CGTXQ.build.board=GENERIC_U385CGTXQ GenU3.menu.pnum.GENERIC_U385CGTXQ.build.product_line=STM32U385xx GenU3.menu.pnum.GENERIC_U385CGTXQ.build.variant=STM32U3xx/U375C(E-G)(T-U)xQ_U385CG(T-U)xQ -GenU3.menu.pnum.GENERIC_U385CGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U385CGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd # Generic U385CGUxQ GenU3.menu.pnum.GENERIC_U385CGUXQ=Generic U385CGUxQ @@ -55,5 +55,5 @@ GenU3.menu.pnum.GENERIC_U385CGUXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U385CGUXQ.build.board=GENERIC_U385CGUXQ GenU3.menu.pnum.GENERIC_U385CGUXQ.build.product_line=STM32U385xx GenU3.menu.pnum.GENERIC_U385CGUXQ.build.variant=STM32U3xx/U375C(E-G)(T-U)xQ_U385CG(T-U)xQ -GenU3.menu.pnum.GENERIC_U385CGUXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U385CGUXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd diff --git a/variants/STM32U3xx/U375C(E-G)YxQ_U385CGYxQ/PeripheralPins.c b/variants/STM32U3xx/U375C(E-G)YxQ_U385CGYxQ/PeripheralPins.c index 82bc012871..a19def4914 100644 --- a/variants/STM32U3xx/U375C(E-G)YxQ_U385CGYxQ/PeripheralPins.c +++ b/variants/STM32U3xx/U375C(E-G)YxQ_U385CGYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375CEYxQ.xml, STM32U375CGYxQ.xml * STM32U385CGYxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375C(E-G)YxQ_U385CGYxQ/boards_entry.txt b/variants/STM32U3xx/U375C(E-G)YxQ_U385CGYxQ/boards_entry.txt index e7890b3920..6e8d8536c0 100644 --- a/variants/STM32U3xx/U375C(E-G)YxQ_U385CGYxQ/boards_entry.txt +++ b/variants/STM32U3xx/U375C(E-G)YxQ_U385CGYxQ/boards_entry.txt @@ -10,7 +10,7 @@ GenU3.menu.pnum.GENERIC_U375CEYXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375CEYXQ.build.board=GENERIC_U375CEYXQ GenU3.menu.pnum.GENERIC_U375CEYXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375CEYXQ.build.variant=STM32U3xx/U375C(E-G)YxQ_U385CGYxQ -GenU3.menu.pnum.GENERIC_U375CEYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375CEYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375CGYxQ GenU3.menu.pnum.GENERIC_U375CGYXQ=Generic U375CGYxQ @@ -19,7 +19,7 @@ GenU3.menu.pnum.GENERIC_U375CGYXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375CGYXQ.build.board=GENERIC_U375CGYXQ GenU3.menu.pnum.GENERIC_U375CGYXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375CGYXQ.build.variant=STM32U3xx/U375C(E-G)YxQ_U385CGYxQ -GenU3.menu.pnum.GENERIC_U375CGYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375CGYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U385CGYxQ GenU3.menu.pnum.GENERIC_U385CGYXQ=Generic U385CGYxQ @@ -28,5 +28,5 @@ GenU3.menu.pnum.GENERIC_U385CGYXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U385CGYXQ.build.board=GENERIC_U385CGYXQ GenU3.menu.pnum.GENERIC_U385CGYXQ.build.product_line=STM32U385xx GenU3.menu.pnum.GENERIC_U385CGYXQ.build.variant=STM32U3xx/U375C(E-G)YxQ_U385CGYxQ -GenU3.menu.pnum.GENERIC_U385CGYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U385CGYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd diff --git a/variants/STM32U3xx/U375K(E-G)U_U385KGU/PeripheralPins.c b/variants/STM32U3xx/U375K(E-G)U_U385KGU/PeripheralPins.c index fd1b963afa..d34ad5a78e 100644 --- a/variants/STM32U3xx/U375K(E-G)U_U385KGU/PeripheralPins.c +++ b/variants/STM32U3xx/U375K(E-G)U_U385KGU/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375KEUx.xml, STM32U375KGUx.xml * STM32U385KGUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375K(E-G)U_U385KGU/boards_entry.txt b/variants/STM32U3xx/U375K(E-G)U_U385KGU/boards_entry.txt index 1b5b2846ac..c7c597a9fc 100644 --- a/variants/STM32U3xx/U375K(E-G)U_U385KGU/boards_entry.txt +++ b/variants/STM32U3xx/U375K(E-G)U_U385KGU/boards_entry.txt @@ -10,7 +10,7 @@ GenU3.menu.pnum.GENERIC_U375KEUX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375KEUX.build.board=GENERIC_U375KEUX GenU3.menu.pnum.GENERIC_U375KEUX.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375KEUX.build.variant=STM32U3xx/U375K(E-G)U_U385KGU -GenU3.menu.pnum.GENERIC_U375KEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375KEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375KGUx GenU3.menu.pnum.GENERIC_U375KGUX=Generic U375KGUx @@ -19,7 +19,7 @@ GenU3.menu.pnum.GENERIC_U375KGUX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375KGUX.build.board=GENERIC_U375KGUX GenU3.menu.pnum.GENERIC_U375KGUX.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375KGUX.build.variant=STM32U3xx/U375K(E-G)U_U385KGU -GenU3.menu.pnum.GENERIC_U375KGUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375KGUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U385KGUx GenU3.menu.pnum.GENERIC_U385KGUX=Generic U385KGUx @@ -28,5 +28,5 @@ GenU3.menu.pnum.GENERIC_U385KGUX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U385KGUX.build.board=GENERIC_U385KGUX GenU3.menu.pnum.GENERIC_U385KGUX.build.product_line=STM32U385xx GenU3.menu.pnum.GENERIC_U385KGUX.build.variant=STM32U3xx/U375K(E-G)U_U385KGU -GenU3.menu.pnum.GENERIC_U385KGUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U385KGUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd diff --git a/variants/STM32U3xx/U375R(E-G)I_U385RGI/PeripheralPins.c b/variants/STM32U3xx/U375R(E-G)I_U385RGI/PeripheralPins.c index 490740a2c8..90dfd5835e 100644 --- a/variants/STM32U3xx/U375R(E-G)I_U385RGI/PeripheralPins.c +++ b/variants/STM32U3xx/U375R(E-G)I_U385RGI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375REIx.xml, STM32U375RGIx.xml * STM32U385RGIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375R(E-G)I_U385RGI/boards_entry.txt b/variants/STM32U3xx/U375R(E-G)I_U385RGI/boards_entry.txt index 4e3e7eead0..2d40422f32 100644 --- a/variants/STM32U3xx/U375R(E-G)I_U385RGI/boards_entry.txt +++ b/variants/STM32U3xx/U375R(E-G)I_U385RGI/boards_entry.txt @@ -10,7 +10,7 @@ GenU3.menu.pnum.GENERIC_U375REIX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375REIX.build.board=GENERIC_U375REIX GenU3.menu.pnum.GENERIC_U375REIX.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375REIX.build.variant=STM32U3xx/U375R(E-G)I_U385RGI -GenU3.menu.pnum.GENERIC_U375REIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375REIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375RGIx GenU3.menu.pnum.GENERIC_U375RGIX=Generic U375RGIx @@ -19,7 +19,7 @@ GenU3.menu.pnum.GENERIC_U375RGIX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375RGIX.build.board=GENERIC_U375RGIX GenU3.menu.pnum.GENERIC_U375RGIX.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375RGIX.build.variant=STM32U3xx/U375R(E-G)I_U385RGI -GenU3.menu.pnum.GENERIC_U375RGIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375RGIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U385RGIx GenU3.menu.pnum.GENERIC_U385RGIX=Generic U385RGIx @@ -28,5 +28,5 @@ GenU3.menu.pnum.GENERIC_U385RGIX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U385RGIX.build.board=GENERIC_U385RGIX GenU3.menu.pnum.GENERIC_U385RGIX.build.product_line=STM32U385xx GenU3.menu.pnum.GENERIC_U385RGIX.build.variant=STM32U3xx/U375R(E-G)I_U385RGI -GenU3.menu.pnum.GENERIC_U385RGIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U385RGIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd diff --git a/variants/STM32U3xx/U375R(E-G)IxQ_U385RGIxQ/PeripheralPins.c b/variants/STM32U3xx/U375R(E-G)IxQ_U385RGIxQ/PeripheralPins.c index 3eab360215..28d1740b19 100644 --- a/variants/STM32U3xx/U375R(E-G)IxQ_U385RGIxQ/PeripheralPins.c +++ b/variants/STM32U3xx/U375R(E-G)IxQ_U385RGIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375REIxQ.xml, STM32U375RGIxQ.xml * STM32U385RGIxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375R(E-G)IxQ_U385RGIxQ/boards_entry.txt b/variants/STM32U3xx/U375R(E-G)IxQ_U385RGIxQ/boards_entry.txt index e6febf7d45..1d2a705069 100644 --- a/variants/STM32U3xx/U375R(E-G)IxQ_U385RGIxQ/boards_entry.txt +++ b/variants/STM32U3xx/U375R(E-G)IxQ_U385RGIxQ/boards_entry.txt @@ -10,7 +10,7 @@ GenU3.menu.pnum.GENERIC_U375REIXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375REIXQ.build.board=GENERIC_U375REIXQ GenU3.menu.pnum.GENERIC_U375REIXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375REIXQ.build.variant=STM32U3xx/U375R(E-G)IxQ_U385RGIxQ -GenU3.menu.pnum.GENERIC_U375REIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375REIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375RGIxQ GenU3.menu.pnum.GENERIC_U375RGIXQ=Generic U375RGIxQ @@ -19,7 +19,7 @@ GenU3.menu.pnum.GENERIC_U375RGIXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375RGIXQ.build.board=GENERIC_U375RGIXQ GenU3.menu.pnum.GENERIC_U375RGIXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375RGIXQ.build.variant=STM32U3xx/U375R(E-G)IxQ_U385RGIxQ -GenU3.menu.pnum.GENERIC_U375RGIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375RGIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U385RGIxQ GenU3.menu.pnum.GENERIC_U385RGIXQ=Generic U385RGIxQ @@ -28,5 +28,5 @@ GenU3.menu.pnum.GENERIC_U385RGIXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U385RGIXQ.build.board=GENERIC_U385RGIXQ GenU3.menu.pnum.GENERIC_U385RGIXQ.build.product_line=STM32U385xx GenU3.menu.pnum.GENERIC_U385RGIXQ.build.variant=STM32U3xx/U375R(E-G)IxQ_U385RGIxQ -GenU3.menu.pnum.GENERIC_U385RGIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U385RGIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd diff --git a/variants/STM32U3xx/U375R(E-G)T_U385RGT/PeripheralPins.c b/variants/STM32U3xx/U375R(E-G)T_U385RGT/PeripheralPins.c index 4367d3f7fb..b85b1e95c9 100644 --- a/variants/STM32U3xx/U375R(E-G)T_U385RGT/PeripheralPins.c +++ b/variants/STM32U3xx/U375R(E-G)T_U385RGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375RETx.xml, STM32U375RGTx.xml * STM32U385RGTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375R(E-G)T_U385RGT/boards_entry.txt b/variants/STM32U3xx/U375R(E-G)T_U385RGT/boards_entry.txt index 8338c24ada..4a4d1241dc 100644 --- a/variants/STM32U3xx/U375R(E-G)T_U385RGT/boards_entry.txt +++ b/variants/STM32U3xx/U375R(E-G)T_U385RGT/boards_entry.txt @@ -10,7 +10,7 @@ GenU3.menu.pnum.GENERIC_U375RETX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375RETX.build.board=GENERIC_U375RETX GenU3.menu.pnum.GENERIC_U375RETX.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375RETX.build.variant=STM32U3xx/U375R(E-G)T_U385RGT -GenU3.menu.pnum.GENERIC_U375RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375RGTx GenU3.menu.pnum.GENERIC_U375RGTX=Generic U375RGTx @@ -19,7 +19,7 @@ GenU3.menu.pnum.GENERIC_U375RGTX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375RGTX.build.board=GENERIC_U375RGTX GenU3.menu.pnum.GENERIC_U375RGTX.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375RGTX.build.variant=STM32U3xx/U375R(E-G)T_U385RGT -GenU3.menu.pnum.GENERIC_U375RGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375RGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U385RGTx GenU3.menu.pnum.GENERIC_U385RGTX=Generic U385RGTx @@ -28,5 +28,5 @@ GenU3.menu.pnum.GENERIC_U385RGTX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U385RGTX.build.board=GENERIC_U385RGTX GenU3.menu.pnum.GENERIC_U385RGTX.build.product_line=STM32U385xx GenU3.menu.pnum.GENERIC_U385RGTX.build.variant=STM32U3xx/U375R(E-G)T_U385RGT -GenU3.menu.pnum.GENERIC_U385RGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U385RGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd diff --git a/variants/STM32U3xx/U375R(E-G)TxQ_U385RGTxQ/PeripheralPins.c b/variants/STM32U3xx/U375R(E-G)TxQ_U385RGTxQ/PeripheralPins.c index a3b4764083..e4c7ec513d 100644 --- a/variants/STM32U3xx/U375R(E-G)TxQ_U385RGTxQ/PeripheralPins.c +++ b/variants/STM32U3xx/U375R(E-G)TxQ_U385RGTxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375RETxQ.xml, STM32U375RGTxQ.xml * STM32U385RGTxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375R(E-G)TxQ_U385RGTxQ/boards_entry.txt b/variants/STM32U3xx/U375R(E-G)TxQ_U385RGTxQ/boards_entry.txt index 28b65ac28d..4a77b4015c 100644 --- a/variants/STM32U3xx/U375R(E-G)TxQ_U385RGTxQ/boards_entry.txt +++ b/variants/STM32U3xx/U375R(E-G)TxQ_U385RGTxQ/boards_entry.txt @@ -10,7 +10,7 @@ GenU3.menu.pnum.GENERIC_U375RETXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375RETXQ.build.board=GENERIC_U375RETXQ GenU3.menu.pnum.GENERIC_U375RETXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375RETXQ.build.variant=STM32U3xx/U375R(E-G)TxQ_U385RGTxQ -GenU3.menu.pnum.GENERIC_U375RETXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375RETXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375RGTxQ GenU3.menu.pnum.GENERIC_U375RGTXQ=Generic U375RGTxQ @@ -19,7 +19,7 @@ GenU3.menu.pnum.GENERIC_U375RGTXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375RGTXQ.build.board=GENERIC_U375RGTXQ GenU3.menu.pnum.GENERIC_U375RGTXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375RGTXQ.build.variant=STM32U3xx/U375R(E-G)TxQ_U385RGTxQ -GenU3.menu.pnum.GENERIC_U375RGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375RGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U385RGTxQ GenU3.menu.pnum.GENERIC_U385RGTXQ=Generic U385RGTxQ @@ -28,5 +28,5 @@ GenU3.menu.pnum.GENERIC_U385RGTXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U385RGTXQ.build.board=GENERIC_U385RGTXQ GenU3.menu.pnum.GENERIC_U385RGTXQ.build.product_line=STM32U385xx GenU3.menu.pnum.GENERIC_U385RGTXQ.build.variant=STM32U3xx/U375R(E-G)TxQ_U385RGTxQ -GenU3.menu.pnum.GENERIC_U385RGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U385RGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd diff --git a/variants/STM32U3xx/U375R(E-G)YxG_U385RGYxG/PeripheralPins.c b/variants/STM32U3xx/U375R(E-G)YxG_U385RGYxG/PeripheralPins.c index 05ae4fccf9..122740616e 100644 --- a/variants/STM32U3xx/U375R(E-G)YxG_U385RGYxG/PeripheralPins.c +++ b/variants/STM32U3xx/U375R(E-G)YxG_U385RGYxG/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375REYxG.xml, STM32U375RGYxG.xml * STM32U385RGYxG.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375R(E-G)YxG_U385RGYxG/boards_entry.txt b/variants/STM32U3xx/U375R(E-G)YxG_U385RGYxG/boards_entry.txt index 7142fb15e4..ee715c8e7c 100644 --- a/variants/STM32U3xx/U375R(E-G)YxG_U385RGYxG/boards_entry.txt +++ b/variants/STM32U3xx/U375R(E-G)YxG_U385RGYxG/boards_entry.txt @@ -10,7 +10,7 @@ GenU3.menu.pnum.GENERIC_U375REYXG.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375REYXG.build.board=GENERIC_U375REYXG GenU3.menu.pnum.GENERIC_U375REYXG.build.product_line=STM32U385xx GenU3.menu.pnum.GENERIC_U375REYXG.build.variant=STM32U3xx/U375R(E-G)YxG_U385RGYxG -GenU3.menu.pnum.GENERIC_U375REYXG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375REYXG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375RGYxG GenU3.menu.pnum.GENERIC_U375RGYXG=Generic U375RGYxG @@ -19,7 +19,7 @@ GenU3.menu.pnum.GENERIC_U375RGYXG.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375RGYXG.build.board=GENERIC_U375RGYXG GenU3.menu.pnum.GENERIC_U375RGYXG.build.product_line=STM32U385xx GenU3.menu.pnum.GENERIC_U375RGYXG.build.variant=STM32U3xx/U375R(E-G)YxG_U385RGYxG -GenU3.menu.pnum.GENERIC_U375RGYXG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375RGYXG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U385RGYxG GenU3.menu.pnum.GENERIC_U385RGYXG=Generic U385RGYxG @@ -28,5 +28,5 @@ GenU3.menu.pnum.GENERIC_U385RGYXG.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U385RGYXG.build.board=GENERIC_U385RGYXG GenU3.menu.pnum.GENERIC_U385RGYXG.build.product_line= GenU3.menu.pnum.GENERIC_U385RGYXG.build.variant=STM32U3xx/U375R(E-G)YxG_U385RGYxG -GenU3.menu.pnum.GENERIC_U385RGYXG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U385RGYXG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd diff --git a/variants/STM32U3xx/U375R(E-G)YxQ_U385RGYxQ/PeripheralPins.c b/variants/STM32U3xx/U375R(E-G)YxQ_U385RGYxQ/PeripheralPins.c index 4d409c2861..32b74c79e1 100644 --- a/variants/STM32U3xx/U375R(E-G)YxQ_U385RGYxQ/PeripheralPins.c +++ b/variants/STM32U3xx/U375R(E-G)YxQ_U385RGYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375REYxQ.xml, STM32U375RGYxQ.xml * STM32U385RGYxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375R(E-G)YxQ_U385RGYxQ/boards_entry.txt b/variants/STM32U3xx/U375R(E-G)YxQ_U385RGYxQ/boards_entry.txt index 4f0b7eee60..8e14a9317e 100644 --- a/variants/STM32U3xx/U375R(E-G)YxQ_U385RGYxQ/boards_entry.txt +++ b/variants/STM32U3xx/U375R(E-G)YxQ_U385RGYxQ/boards_entry.txt @@ -10,7 +10,7 @@ GenU3.menu.pnum.GENERIC_U375REYXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375REYXQ.build.board=GENERIC_U375REYXQ GenU3.menu.pnum.GENERIC_U375REYXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375REYXQ.build.variant=STM32U3xx/U375R(E-G)YxQ_U385RGYxQ -GenU3.menu.pnum.GENERIC_U375REYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375REYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375RGYxQ GenU3.menu.pnum.GENERIC_U375RGYXQ=Generic U375RGYxQ @@ -19,7 +19,7 @@ GenU3.menu.pnum.GENERIC_U375RGYXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375RGYXQ.build.board=GENERIC_U375RGYXQ GenU3.menu.pnum.GENERIC_U375RGYXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375RGYXQ.build.variant=STM32U3xx/U375R(E-G)YxQ_U385RGYxQ -GenU3.menu.pnum.GENERIC_U375RGYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375RGYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U385RGYxQ GenU3.menu.pnum.GENERIC_U385RGYXQ=Generic U385RGYxQ @@ -28,5 +28,5 @@ GenU3.menu.pnum.GENERIC_U385RGYXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U385RGYXQ.build.board=GENERIC_U385RGYXQ GenU3.menu.pnum.GENERIC_U385RGYXQ.build.product_line=STM32U385xx GenU3.menu.pnum.GENERIC_U385RGYXQ.build.variant=STM32U3xx/U375R(E-G)YxQ_U385RGYxQ -GenU3.menu.pnum.GENERIC_U385RGYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U385RGYXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd diff --git a/variants/STM32U3xx/U375V(E-G)I_U385VGI/PeripheralPins.c b/variants/STM32U3xx/U375V(E-G)I_U385VGI/PeripheralPins.c index fc66a07a4c..d017571c2e 100644 --- a/variants/STM32U3xx/U375V(E-G)I_U385VGI/PeripheralPins.c +++ b/variants/STM32U3xx/U375V(E-G)I_U385VGI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375VEIx.xml, STM32U375VGIx.xml * STM32U385VGIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375V(E-G)I_U385VGI/boards_entry.txt b/variants/STM32U3xx/U375V(E-G)I_U385VGI/boards_entry.txt index 17ef321149..7c8bff3e85 100644 --- a/variants/STM32U3xx/U375V(E-G)I_U385VGI/boards_entry.txt +++ b/variants/STM32U3xx/U375V(E-G)I_U385VGI/boards_entry.txt @@ -10,7 +10,7 @@ GenU3.menu.pnum.GENERIC_U375VEIX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375VEIX.build.board=GENERIC_U375VEIX GenU3.menu.pnum.GENERIC_U375VEIX.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375VEIX.build.variant=STM32U3xx/U375V(E-G)I_U385VGI -GenU3.menu.pnum.GENERIC_U375VEIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375VEIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375VGIx GenU3.menu.pnum.GENERIC_U375VGIX=Generic U375VGIx @@ -19,7 +19,7 @@ GenU3.menu.pnum.GENERIC_U375VGIX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375VGIX.build.board=GENERIC_U375VGIX GenU3.menu.pnum.GENERIC_U375VGIX.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375VGIX.build.variant=STM32U3xx/U375V(E-G)I_U385VGI -GenU3.menu.pnum.GENERIC_U375VGIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375VGIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U385VGIx GenU3.menu.pnum.GENERIC_U385VGIX=Generic U385VGIx @@ -28,5 +28,5 @@ GenU3.menu.pnum.GENERIC_U385VGIX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U385VGIX.build.board=GENERIC_U385VGIX GenU3.menu.pnum.GENERIC_U385VGIX.build.product_line=STM32U385xx GenU3.menu.pnum.GENERIC_U385VGIX.build.variant=STM32U3xx/U375V(E-G)I_U385VGI -GenU3.menu.pnum.GENERIC_U385VGIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U385VGIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd diff --git a/variants/STM32U3xx/U375V(E-G)IxQ_U385VGIxQ/PeripheralPins.c b/variants/STM32U3xx/U375V(E-G)IxQ_U385VGIxQ/PeripheralPins.c index 89252a6047..466213143e 100644 --- a/variants/STM32U3xx/U375V(E-G)IxQ_U385VGIxQ/PeripheralPins.c +++ b/variants/STM32U3xx/U375V(E-G)IxQ_U385VGIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375VEIxQ.xml, STM32U375VGIxQ.xml * STM32U385VGIxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375V(E-G)IxQ_U385VGIxQ/boards_entry.txt b/variants/STM32U3xx/U375V(E-G)IxQ_U385VGIxQ/boards_entry.txt index 78f2da523c..ff499f3b16 100644 --- a/variants/STM32U3xx/U375V(E-G)IxQ_U385VGIxQ/boards_entry.txt +++ b/variants/STM32U3xx/U375V(E-G)IxQ_U385VGIxQ/boards_entry.txt @@ -10,7 +10,7 @@ GenU3.menu.pnum.GENERIC_U375VEIXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375VEIXQ.build.board=GENERIC_U375VEIXQ GenU3.menu.pnum.GENERIC_U375VEIXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375VEIXQ.build.variant=STM32U3xx/U375V(E-G)IxQ_U385VGIxQ -GenU3.menu.pnum.GENERIC_U375VEIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375VEIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375VGIxQ GenU3.menu.pnum.GENERIC_U375VGIXQ=Generic U375VGIxQ @@ -19,7 +19,7 @@ GenU3.menu.pnum.GENERIC_U375VGIXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375VGIXQ.build.board=GENERIC_U375VGIXQ GenU3.menu.pnum.GENERIC_U375VGIXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375VGIXQ.build.variant=STM32U3xx/U375V(E-G)IxQ_U385VGIxQ -GenU3.menu.pnum.GENERIC_U375VGIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375VGIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U385VGIxQ GenU3.menu.pnum.GENERIC_U385VGIXQ=Generic U385VGIxQ @@ -28,5 +28,5 @@ GenU3.menu.pnum.GENERIC_U385VGIXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U385VGIXQ.build.board=GENERIC_U385VGIXQ GenU3.menu.pnum.GENERIC_U385VGIXQ.build.product_line=STM32U385xx GenU3.menu.pnum.GENERIC_U385VGIXQ.build.variant=STM32U3xx/U375V(E-G)IxQ_U385VGIxQ -GenU3.menu.pnum.GENERIC_U385VGIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U385VGIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd diff --git a/variants/STM32U3xx/U375V(E-G)T_U385VGT/PeripheralPins.c b/variants/STM32U3xx/U375V(E-G)T_U385VGT/PeripheralPins.c index fe712b5db7..5c466556c5 100644 --- a/variants/STM32U3xx/U375V(E-G)T_U385VGT/PeripheralPins.c +++ b/variants/STM32U3xx/U375V(E-G)T_U385VGT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375VETx.xml, STM32U375VGTx.xml * STM32U385VGTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375V(E-G)T_U385VGT/boards_entry.txt b/variants/STM32U3xx/U375V(E-G)T_U385VGT/boards_entry.txt index cd4f2bf04f..9cffa2aa6d 100644 --- a/variants/STM32U3xx/U375V(E-G)T_U385VGT/boards_entry.txt +++ b/variants/STM32U3xx/U375V(E-G)T_U385VGT/boards_entry.txt @@ -10,7 +10,7 @@ GenU3.menu.pnum.GENERIC_U375VETX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375VETX.build.board=GENERIC_U375VETX GenU3.menu.pnum.GENERIC_U375VETX.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375VETX.build.variant=STM32U3xx/U375V(E-G)T_U385VGT -GenU3.menu.pnum.GENERIC_U375VETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375VETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375VGTx GenU3.menu.pnum.GENERIC_U375VGTX=Generic U375VGTx @@ -19,7 +19,7 @@ GenU3.menu.pnum.GENERIC_U375VGTX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375VGTX.build.board=GENERIC_U375VGTX GenU3.menu.pnum.GENERIC_U375VGTX.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375VGTX.build.variant=STM32U3xx/U375V(E-G)T_U385VGT -GenU3.menu.pnum.GENERIC_U375VGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375VGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U385VGTx GenU3.menu.pnum.GENERIC_U385VGTX=Generic U385VGTx @@ -28,5 +28,5 @@ GenU3.menu.pnum.GENERIC_U385VGTX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U385VGTX.build.board=GENERIC_U385VGTX GenU3.menu.pnum.GENERIC_U385VGTX.build.product_line=STM32U385xx GenU3.menu.pnum.GENERIC_U385VGTX.build.variant=STM32U3xx/U375V(E-G)T_U385VGT -GenU3.menu.pnum.GENERIC_U385VGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U385VGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd diff --git a/variants/STM32U3xx/U375V(E-G)TxQ_U385VGTxQ/PeripheralPins.c b/variants/STM32U3xx/U375V(E-G)TxQ_U385VGTxQ/PeripheralPins.c index b754e84853..67a085880a 100644 --- a/variants/STM32U3xx/U375V(E-G)TxQ_U385VGTxQ/PeripheralPins.c +++ b/variants/STM32U3xx/U375V(E-G)TxQ_U385VGTxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U375VETxQ.xml, STM32U375VGTxQ.xml * STM32U385VGTxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U3xx/U375V(E-G)TxQ_U385VGTxQ/boards_entry.txt b/variants/STM32U3xx/U375V(E-G)TxQ_U385VGTxQ/boards_entry.txt index efe041e2fa..2de10ed987 100644 --- a/variants/STM32U3xx/U375V(E-G)TxQ_U385VGTxQ/boards_entry.txt +++ b/variants/STM32U3xx/U375V(E-G)TxQ_U385VGTxQ/boards_entry.txt @@ -10,7 +10,7 @@ GenU3.menu.pnum.GENERIC_U375VETXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375VETXQ.build.board=GENERIC_U375VETXQ GenU3.menu.pnum.GENERIC_U375VETXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375VETXQ.build.variant=STM32U3xx/U375V(E-G)TxQ_U385VGTxQ -GenU3.menu.pnum.GENERIC_U375VETXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375VETXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375VGTxQ GenU3.menu.pnum.GENERIC_U375VGTXQ=Generic U375VGTxQ @@ -19,7 +19,7 @@ GenU3.menu.pnum.GENERIC_U375VGTXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375VGTXQ.build.board=GENERIC_U375VGTXQ GenU3.menu.pnum.GENERIC_U375VGTXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375VGTXQ.build.variant=STM32U3xx/U375V(E-G)TxQ_U385VGTxQ -GenU3.menu.pnum.GENERIC_U375VGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375VGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U385VGTxQ GenU3.menu.pnum.GENERIC_U385VGTXQ=Generic U385VGTxQ @@ -28,5 +28,5 @@ GenU3.menu.pnum.GENERIC_U385VGTXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U385VGTXQ.build.board=GENERIC_U385VGTXQ GenU3.menu.pnum.GENERIC_U385VGTXQ.build.product_line=STM32U385xx GenU3.menu.pnum.GENERIC_U385VGTXQ.build.variant=STM32U3xx/U375V(E-G)TxQ_U385VGTxQ -GenU3.menu.pnum.GENERIC_U385VGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U385VGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd diff --git a/variants/STM32U5xx/U535C(B-C-E)(T-U)_U545CE(T-U)/PeripheralPins.c b/variants/STM32U5xx/U535C(B-C-E)(T-U)_U545CE(T-U)/PeripheralPins.c index 5c04bd1070..43dbf104bb 100644 --- a/variants/STM32U5xx/U535C(B-C-E)(T-U)_U545CE(T-U)/PeripheralPins.c +++ b/variants/STM32U5xx/U535C(B-C-E)(T-U)_U545CE(T-U)/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32U535CCTx.xml, STM32U535CCUx.xml * STM32U535CETx.xml, STM32U535CEUx.xml * STM32U545CETx.xml, STM32U545CEUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535C(B-C-E)(T-U)xQ_U545CE(T-U)xQ/PeripheralPins.c b/variants/STM32U5xx/U535C(B-C-E)(T-U)xQ_U545CE(T-U)xQ/PeripheralPins.c index 05ba3dabae..53c57a8c2e 100644 --- a/variants/STM32U5xx/U535C(B-C-E)(T-U)xQ_U545CE(T-U)xQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535C(B-C-E)(T-U)xQ_U545CE(T-U)xQ/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32U535CCTxQ.xml, STM32U535CCUxQ.xml * STM32U535CETxQ.xml, STM32U535CEUxQ.xml * STM32U545CETxQ.xml, STM32U545CEUxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535JEYxQ_U545JEYxQ/PeripheralPins.c b/variants/STM32U5xx/U535JEYxQ_U545JEYxQ/PeripheralPins.c index 476b05f758..239dd23bd5 100644 --- a/variants/STM32U5xx/U535JEYxQ_U545JEYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535JEYxQ_U545JEYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U535JEYxQ.xml, STM32U545JEYxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c b/variants/STM32U5xx/U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c index 9433c897cd..bd1f20b3ef 100644 --- a/variants/STM32U5xx/U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535N(C-E)YxQ_U545NEYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535NCYxQ.xml, STM32U535NEYxQ.xml * STM32U545NEYxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535R(B-C-E)I_U545REI/PeripheralPins.c b/variants/STM32U5xx/U535R(B-C-E)I_U545REI/PeripheralPins.c index 3d9d546299..d602627a51 100644 --- a/variants/STM32U5xx/U535R(B-C-E)I_U545REI/PeripheralPins.c +++ b/variants/STM32U5xx/U535R(B-C-E)I_U545REI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535RBIx.xml, STM32U535RCIx.xml * STM32U535REIx.xml, STM32U545REIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535R(B-C-E)IxQ_U545REIxQ/PeripheralPins.c b/variants/STM32U5xx/U535R(B-C-E)IxQ_U545REIxQ/PeripheralPins.c index 8e35a25d53..6d2119b103 100644 --- a/variants/STM32U5xx/U535R(B-C-E)IxQ_U545REIxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535R(B-C-E)IxQ_U545REIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535RBIxQ.xml, STM32U535RCIxQ.xml * STM32U535REIxQ.xml, STM32U545REIxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535R(B-C-E)T_U545RET/PeripheralPins.c b/variants/STM32U5xx/U535R(B-C-E)T_U545RET/PeripheralPins.c index 0280b0334f..51ca131bbd 100644 --- a/variants/STM32U5xx/U535R(B-C-E)T_U545RET/PeripheralPins.c +++ b/variants/STM32U5xx/U535R(B-C-E)T_U545RET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535RBTx.xml, STM32U535RCTx.xml * STM32U535RETx.xml, STM32U545RETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535R(B-C-E)TxQ_U545RETxQ/PeripheralPins.c b/variants/STM32U5xx/U535R(B-C-E)TxQ_U545RETxQ/PeripheralPins.c index b318ed6fbd..f287e27d22 100644 --- a/variants/STM32U5xx/U535R(B-C-E)TxQ_U545RETxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535R(B-C-E)TxQ_U545RETxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535RBTxQ.xml, STM32U535RCTxQ.xml * STM32U535RETxQ.xml, STM32U545RETxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535V(C-E)I_U545VEI/PeripheralPins.c b/variants/STM32U5xx/U535V(C-E)I_U545VEI/PeripheralPins.c index 534490a910..b06cc9024c 100644 --- a/variants/STM32U5xx/U535V(C-E)I_U545VEI/PeripheralPins.c +++ b/variants/STM32U5xx/U535V(C-E)I_U545VEI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535VCIx.xml, STM32U535VEIx.xml * STM32U545VEIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c b/variants/STM32U5xx/U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c index 8bc03a5d5e..c6bc88f37c 100644 --- a/variants/STM32U5xx/U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535V(C-E)IxQ_U545VEIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535VCIxQ.xml, STM32U535VEIxQ.xml * STM32U545VEIxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535V(C-E)T_U545VET/PeripheralPins.c b/variants/STM32U5xx/U535V(C-E)T_U545VET/PeripheralPins.c index 64e5137c67..2172c1a08f 100644 --- a/variants/STM32U5xx/U535V(C-E)T_U545VET/PeripheralPins.c +++ b/variants/STM32U5xx/U535V(C-E)T_U545VET/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535VCTx.xml, STM32U535VETx.xml * STM32U545VETx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c b/variants/STM32U5xx/U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c index 3e1826f98a..042487934e 100644 --- a/variants/STM32U5xx/U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U535V(C-E)TxQ_U545VETxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U535VCTxQ.xml, STM32U535VETxQ.xml * STM32U545VETxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575A(G-I)I_U585AII/PeripheralPins.c b/variants/STM32U5xx/U575A(G-I)I_U585AII/PeripheralPins.c index f50c379abf..626461bb74 100644 --- a/variants/STM32U5xx/U575A(G-I)I_U585AII/PeripheralPins.c +++ b/variants/STM32U5xx/U575A(G-I)I_U585AII/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575AGIx.xml, STM32U575AIIx.xml * STM32U585AIIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c b/variants/STM32U5xx/U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c index 9c6e219f0a..9967d1555f 100644 --- a/variants/STM32U5xx/U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575A(G-I)IxQ_U585AIIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575AGIxQ.xml, STM32U575AIIxQ.xml * STM32U585AIIxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins.c b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins.c index 14d15d32e8..65f09027a3 100644 --- a/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins.c +++ b/variants/STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U)/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U575CGTx.xml, STM32U575CGUx.xml * STM32U575CITx.xml, STM32U575CIUx.xml * STM32U585CITx.xml, STM32U585CIUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575C(G-I)(T-U)xQ_U585CI(T-U)xQ/PeripheralPins.c b/variants/STM32U5xx/U575C(G-I)(T-U)xQ_U585CI(T-U)xQ/PeripheralPins.c index 05f88b1501..840d81632b 100644 --- a/variants/STM32U5xx/U575C(G-I)(T-U)xQ_U585CI(T-U)xQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575C(G-I)(T-U)xQ_U585CI(T-U)xQ/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U575CGTxQ.xml, STM32U575CGUxQ.xml * STM32U575CITxQ.xml, STM32U575CIUxQ.xml * STM32U585CITxQ.xml, STM32U585CIUxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c b/variants/STM32U5xx/U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c index 697a4a4b2c..e40bafac2e 100644 --- a/variants/STM32U5xx/U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575O(G-I)YxQ_U585OIYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575OGYxQ.xml, STM32U575OIYxQ.xml * STM32U585OIYxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575Q(G-I)I_U585QII/PeripheralPins.c b/variants/STM32U5xx/U575Q(G-I)I_U585QII/PeripheralPins.c index 9afa68b9f0..91b6af8a25 100644 --- a/variants/STM32U5xx/U575Q(G-I)I_U585QII/PeripheralPins.c +++ b/variants/STM32U5xx/U575Q(G-I)I_U585QII/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575QGIx.xml, STM32U575QIIx.xml * STM32U585QIIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c b/variants/STM32U5xx/U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c index 6771ee771d..1edb9503d2 100644 --- a/variants/STM32U5xx/U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575Q(G-I)IxQ_U585QIIxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575QGIxQ.xml, STM32U575QIIxQ.xml * STM32U585QIIxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575R(G-I)T_U585RIT/PeripheralPins.c b/variants/STM32U5xx/U575R(G-I)T_U585RIT/PeripheralPins.c index 17691a7051..f971230397 100644 --- a/variants/STM32U5xx/U575R(G-I)T_U585RIT/PeripheralPins.c +++ b/variants/STM32U5xx/U575R(G-I)T_U585RIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575RGTx.xml, STM32U575RITx.xml * STM32U585RITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c b/variants/STM32U5xx/U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c index d0cc962942..413b028c04 100644 --- a/variants/STM32U5xx/U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575R(G-I)TxQ_U585RITxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575RGTxQ.xml, STM32U575RITxQ.xml * STM32U585RITxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575V(G-I)T_U585VIT/PeripheralPins.c b/variants/STM32U5xx/U575V(G-I)T_U585VIT/PeripheralPins.c index 1414c43370..1253a59669 100644 --- a/variants/STM32U5xx/U575V(G-I)T_U585VIT/PeripheralPins.c +++ b/variants/STM32U5xx/U575V(G-I)T_U585VIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575VGTx.xml, STM32U575VITx.xml * STM32U585VITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c b/variants/STM32U5xx/U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c index 67e3f45dd7..4946e1fdef 100644 --- a/variants/STM32U5xx/U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575V(G-I)TxQ_U585VITxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575VGTxQ.xml, STM32U575VITxQ.xml * STM32U585VITxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575Z(G-I)T_U585ZIT/PeripheralPins.c b/variants/STM32U5xx/U575Z(G-I)T_U585ZIT/PeripheralPins.c index a41e47019a..fe98b2fdfd 100644 --- a/variants/STM32U5xx/U575Z(G-I)T_U585ZIT/PeripheralPins.c +++ b/variants/STM32U5xx/U575Z(G-I)T_U585ZIT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575ZGTx.xml, STM32U575ZITx.xml * STM32U585ZITx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c b/variants/STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c index 1044f8568c..78c70702bf 100644 --- a/variants/STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U575ZGTxQ.xml, STM32U575ZITxQ.xml * STM32U585ZITxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595A(I-J)H_U5A5AJH/PeripheralPins.c b/variants/STM32U5xx/U595A(I-J)H_U5A5AJH/PeripheralPins.c index d047292efe..1056993558 100644 --- a/variants/STM32U5xx/U595A(I-J)H_U5A5AJH/PeripheralPins.c +++ b/variants/STM32U5xx/U595A(I-J)H_U5A5AJH/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595AIHx.xml, STM32U595AJHx.xml * STM32U5A5AJHx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c b/variants/STM32U5xx/U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c index 03164a7e59..ffafc77a91 100644 --- a/variants/STM32U5xx/U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595A(I-J)HxQ_U5A5AJHxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595AIHxQ.xml, STM32U595AJHxQ.xml * STM32U5A5AJHxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Q(I-J)I_U5A5QJI/PeripheralPins.c b/variants/STM32U5xx/U595Q(I-J)I_U5A5QJI/PeripheralPins.c index afa448747d..6ff183ea25 100644 --- a/variants/STM32U5xx/U595Q(I-J)I_U5A5QJI/PeripheralPins.c +++ b/variants/STM32U5xx/U595Q(I-J)I_U5A5QJI/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595QIIx.xml, STM32U595QJIx.xml * STM32U5A5QJIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/PeripheralPins.c b/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/PeripheralPins.c index 1280190aef..300856b3da 100644 --- a/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595Q(I-J)IxQ_U5A5Q(I-J)IxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595QIIxQ.xml, STM32U595QJIxQ.xml * STM32U5A5QIIxQ.xml, STM32U5A5QJIxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595R(I-J)T_U5A5RJT/PeripheralPins.c b/variants/STM32U5xx/U595R(I-J)T_U5A5RJT/PeripheralPins.c index bfa2976097..cd40f9d55f 100644 --- a/variants/STM32U5xx/U595R(I-J)T_U5A5RJT/PeripheralPins.c +++ b/variants/STM32U5xx/U595R(I-J)T_U5A5RJT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595RITx.xml, STM32U595RJTx.xml * STM32U5A5RJTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c b/variants/STM32U5xx/U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c index 066e6c154a..5bec1c091d 100644 --- a/variants/STM32U5xx/U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595R(I-J)TxQ_U5A5RJTxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595RITxQ.xml, STM32U595RJTxQ.xml * STM32U5A5RJTxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595V(I-J)T_U599VJT_U5A5VJT/PeripheralPins.c b/variants/STM32U5xx/U595V(I-J)T_U599VJT_U5A5VJT/PeripheralPins.c index efeecbd928..35b01cc9d8 100644 --- a/variants/STM32U5xx/U595V(I-J)T_U599VJT_U5A5VJT/PeripheralPins.c +++ b/variants/STM32U5xx/U595V(I-J)T_U599VJT_U5A5VJT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595VITx.xml, STM32U595VJTx.xml * STM32U599VJTx.xml, STM32U5A5VJTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595V(I-J)TxQ_U599V(I-J)TxQ_U5A5VJTxQ_U5A9VJTxQ/PeripheralPins.c b/variants/STM32U5xx/U595V(I-J)TxQ_U599V(I-J)TxQ_U5A5VJTxQ_U5A9VJTxQ/PeripheralPins.c index b9b7ab4f36..e5df35d7d3 100644 --- a/variants/STM32U5xx/U595V(I-J)TxQ_U599V(I-J)TxQ_U5A5VJTxQ_U5A9VJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595V(I-J)TxQ_U599V(I-J)TxQ_U5A5VJTxQ_U5A9VJTxQ/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U595VITxQ.xml, STM32U595VJTxQ.xml * STM32U599VITxQ.xml, STM32U599VJTxQ.xml * STM32U5A5VJTxQ.xml, STM32U5A9VJTxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Z(I-J)T_U5A5ZJT/PeripheralPins.c b/variants/STM32U5xx/U595Z(I-J)T_U5A5ZJT/PeripheralPins.c index be9ce02d2e..1f263cdfe6 100644 --- a/variants/STM32U5xx/U595Z(I-J)T_U5A5ZJT/PeripheralPins.c +++ b/variants/STM32U5xx/U595Z(I-J)T_U5A5ZJT/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595ZITx.xml, STM32U595ZJTx.xml * STM32U5A5ZJTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/PeripheralPins.c b/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/PeripheralPins.c index 5f01faf05b..6443e38a03 100644 --- a/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595Z(I-J)TxQ_U599Z(I-J)TxQ_U5A5ZJTxQ_U5A9ZJTxQ/PeripheralPins.c @@ -14,7 +14,7 @@ * Automatically generated from STM32U595ZITxQ.xml, STM32U595ZJTxQ.xml * STM32U599ZITxQ.xml, STM32U599ZJTxQ.xml * STM32U5A5ZJTxQ.xml, STM32U5A9ZJTxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c b/variants/STM32U5xx/U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c index 94afcbb5fb..70afd54894 100644 --- a/variants/STM32U5xx/U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U595Z(I-J)YxQ_U5A5ZJYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U595ZIYxQ.xml, STM32U595ZJYxQ.xml * STM32U5A5ZJYxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U599BJYxQ_U5A9BJYxQ/PeripheralPins.c b/variants/STM32U5xx/U599BJYxQ_U5A9BJYxQ/PeripheralPins.c index 4ca75feb46..0b723f8bb9 100644 --- a/variants/STM32U5xx/U599BJYxQ_U5A9BJYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U599BJYxQ_U5A9BJYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U599BJYxQ.xml, STM32U5A9BJYxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c b/variants/STM32U5xx/U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c index f75cce4d28..a34cff953d 100644 --- a/variants/STM32U5xx/U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U599N(I-J)HxQ_U5A9NJHxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U599NIHxQ.xml, STM32U599NJHxQ.xml * STM32U5A9NJHxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c b/variants/STM32U5xx/U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c index 46610656ba..e55ab79c55 100644 --- a/variants/STM32U5xx/U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U599Z(I-J)YxQ_U5A9ZJYxQ/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32U599ZIYxQ.xml, STM32U599ZJYxQ.xml * STM32U5A9ZJYxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F7V(I-J)T/PeripheralPins.c b/variants/STM32U5xx/U5F7V(I-J)T/PeripheralPins.c index b35321b5d9..3600ce6465 100644 --- a/variants/STM32U5xx/U5F7V(I-J)T/PeripheralPins.c +++ b/variants/STM32U5xx/U5F7V(I-J)T/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5F7VITx.xml, STM32U5F7VJTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F7V(I-J)TxQ/PeripheralPins.c b/variants/STM32U5xx/U5F7V(I-J)TxQ/PeripheralPins.c index a83a59649e..b6ae911a57 100644 --- a/variants/STM32U5xx/U5F7V(I-J)TxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F7V(I-J)TxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5F7VITxQ.xml, STM32U5F7VJTxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c index 116c0c8219..07661d8db6 100644 --- a/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F9BJYxQ_U5G9BJYxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5F9BJYxQ.xml, STM32U5G9BJYxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F9NJHxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9NJHxQ/PeripheralPins.c index b4f8be299c..c23f31abb6 100644 --- a/variants/STM32U5xx/U5F9NJHxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F9NJHxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5F9NJHxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F9V(I-J)TxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9V(I-J)TxQ/PeripheralPins.c index a9f4c287aa..dda5e94ea8 100644 --- a/variants/STM32U5xx/U5F9V(I-J)TxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F9V(I-J)TxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5F9VITxQ.xml, STM32U5F9VJTxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F9Z(I-J)JxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9Z(I-J)JxQ/PeripheralPins.c index 9e4e412b3f..ac1f82f76a 100644 --- a/variants/STM32U5xx/U5F9Z(I-J)JxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F9Z(I-J)JxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5F9ZIJxQ.xml, STM32U5F9ZJJxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5F9Z(I-J)TxQ/PeripheralPins.c b/variants/STM32U5xx/U5F9Z(I-J)TxQ/PeripheralPins.c index 74779e1160..29d6082451 100644 --- a/variants/STM32U5xx/U5F9Z(I-J)TxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5F9Z(I-J)TxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5F9ZITxQ.xml, STM32U5F9ZJTxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5G7VJT/PeripheralPins.c b/variants/STM32U5xx/U5G7VJT/PeripheralPins.c index bc0c24a76e..173cb4af39 100644 --- a/variants/STM32U5xx/U5G7VJT/PeripheralPins.c +++ b/variants/STM32U5xx/U5G7VJT/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5G7VJTx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5G7VJTxQ/PeripheralPins.c b/variants/STM32U5xx/U5G7VJTxQ/PeripheralPins.c index ab38b6d307..7d30a4c729 100644 --- a/variants/STM32U5xx/U5G7VJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5G7VJTxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5G7VJTxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5G9NJHxQ/PeripheralPins.c b/variants/STM32U5xx/U5G9NJHxQ/PeripheralPins.c index 60768fb0a4..8fa8b3c22e 100644 --- a/variants/STM32U5xx/U5G9NJHxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5G9NJHxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5G9NJHxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5G9VJTxQ/PeripheralPins.c b/variants/STM32U5xx/U5G9VJTxQ/PeripheralPins.c index 84153049e1..b645ee38dd 100644 --- a/variants/STM32U5xx/U5G9VJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5G9VJTxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5G9VJTxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5G9ZJJxQ/PeripheralPins.c b/variants/STM32U5xx/U5G9ZJJxQ/PeripheralPins.c index e46bbfdab6..c4adb5bff1 100644 --- a/variants/STM32U5xx/U5G9ZJJxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5G9ZJJxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5G9ZJJxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32U5xx/U5G9ZJTxQ/PeripheralPins.c b/variants/STM32U5xx/U5G9ZJTxQ/PeripheralPins.c index fe66f1f19a..cc85bc1828 100644 --- a/variants/STM32U5xx/U5G9ZJTxQ/PeripheralPins.c +++ b/variants/STM32U5xx/U5G9ZJTxQ/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32U5G9ZJTxQ.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBAxx/WBA5MMGH/boards_entry.txt b/variants/STM32WBAxx/WBA5MMGH/boards_entry.txt index 4e6eaa3e21..f4f02cc1ac 100644 --- a/variants/STM32WBAxx/WBA5MMGH/boards_entry.txt +++ b/variants/STM32WBAxx/WBA5MMGH/boards_entry.txt @@ -10,4 +10,5 @@ GenWBA.menu.pnum.GENERIC_WBA5MMGHX.upload.maximum_data_size=131072 GenWBA.menu.pnum.GENERIC_WBA5MMGHX.build.board=GENERIC_WBA5MMGHX GenWBA.menu.pnum.GENERIC_WBA5MMGHX.build.product_line=STM32WBA5Mxx GenWBA.menu.pnum.GENERIC_WBA5MMGHX.build.variant=STM32WBAxx/WBA5MMGH +GenWBA.menu.pnum.GENERIC_WBA5MMGHX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WBAxx/STM32WBA55.svd diff --git a/variants/STM32WBxx/WB10CCU/PeripheralPins.c b/variants/STM32WBxx/WB10CCU/PeripheralPins.c index acb8575ce5..d26a3b9f6a 100644 --- a/variants/STM32WBxx/WB10CCU/PeripheralPins.c +++ b/variants/STM32WBxx/WB10CCU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB10CCUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB15CCU/PeripheralPins.c b/variants/STM32WBxx/WB15CCU/PeripheralPins.c index 7bf5d064a9..9edc646701 100644 --- a/variants/STM32WBxx/WB15CCU/PeripheralPins.c +++ b/variants/STM32WBxx/WB15CCU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB15CCUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB15CCUxE/PeripheralPins.c b/variants/STM32WBxx/WB15CCUxE/PeripheralPins.c index e9ad838876..beef66a57e 100644 --- a/variants/STM32WBxx/WB15CCUxE/PeripheralPins.c +++ b/variants/STM32WBxx/WB15CCUxE/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB15CCUxE.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB15CCY/PeripheralPins.c b/variants/STM32WBxx/WB15CCY/PeripheralPins.c index eb9306e897..6afbce3570 100644 --- a/variants/STM32WBxx/WB15CCY/PeripheralPins.c +++ b/variants/STM32WBxx/WB15CCY/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB15CCYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB1MMCH/PeripheralPins.c b/variants/STM32WBxx/WB1MMCH/PeripheralPins.c index 7af3cd5305..cc0eb167d4 100644 --- a/variants/STM32WBxx/WB1MMCH/PeripheralPins.c +++ b/variants/STM32WBxx/WB1MMCH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB1MMCHx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB30CEUxA_WB50CGU/PeripheralPins.c b/variants/STM32WBxx/WB30CEUxA_WB50CGU/PeripheralPins.c index fcc8b394e7..9916bc5c27 100644 --- a/variants/STM32WBxx/WB30CEUxA_WB50CGU/PeripheralPins.c +++ b/variants/STM32WBxx/WB30CEUxA_WB50CGU/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB30CEUxA.xml, STM32WB50CGUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PeripheralPins.c b/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PeripheralPins.c index 65acb022b7..34020432d9 100644 --- a/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PeripheralPins.c +++ b/variants/STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32WB35C(C-E)UxA.xml, STM32WB55CCUx.xml * STM32WB55CEUx.xml, STM32WB55CGUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c b/variants/STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c index 47194d9d79..5bb3aa972f 100644 --- a/variants/STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c +++ b/variants/STM32WBxx/WB55R(C-E-G)V/PeripheralPins.c @@ -13,7 +13,7 @@ /* * Automatically generated from STM32WB55RCVx.xml, STM32WB55REVx.xml * STM32WB55RGVx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PeripheralPins.c b/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PeripheralPins.c index bd363424ce..03d9c4152d 100644 --- a/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PeripheralPins.c +++ b/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32WB55VEQx.xml, STM32WB55VEYx.xml * STM32WB55VGQx.xml, STM32WB55VGYx.xml * STM32WB55VYYx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/boards_entry.txt b/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/boards_entry.txt index a9e0f5840b..bf427f75bf 100644 --- a/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/boards_entry.txt +++ b/variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY/boards_entry.txt @@ -24,7 +24,7 @@ GenWB.menu.pnum.GENERIC_WB55VCYX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic WB55VEQx GenWB.menu.pnum.GENERIC_WB55VEQX=Generic WB55VEQx GenWB.menu.pnum.GENERIC_WB55VEQX.upload.maximum_size=524288 -GenWB.menu.pnum.GENERIC_WB55VEQX.upload.maximum_data_size=131072 +GenWB.menu.pnum.GENERIC_WB55VEQX.upload.maximum_data_size=262144 GenWB.menu.pnum.GENERIC_WB55VEQX.build.board=GENERIC_WB55VEQX GenWB.menu.pnum.GENERIC_WB55VEQX.build.product_line=STM32WB55xx GenWB.menu.pnum.GENERIC_WB55VEQX.build.variant=STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY @@ -42,7 +42,7 @@ GenWB.menu.pnum.GENERIC_WB55VEYX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic WB55VGQx GenWB.menu.pnum.GENERIC_WB55VGQX=Generic WB55VGQx GenWB.menu.pnum.GENERIC_WB55VGQX.upload.maximum_size=1048576 -GenWB.menu.pnum.GENERIC_WB55VGQX.upload.maximum_data_size=131072 +GenWB.menu.pnum.GENERIC_WB55VGQX.upload.maximum_data_size=262144 GenWB.menu.pnum.GENERIC_WB55VGQX.build.board=GENERIC_WB55VGQX GenWB.menu.pnum.GENERIC_WB55VGQX.build.product_line=STM32WB55xx GenWB.menu.pnum.GENERIC_WB55VGQX.build.variant=STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY diff --git a/variants/STM32WBxx/WB5MMGH/PeripheralPins.c b/variants/STM32WBxx/WB5MMGH/PeripheralPins.c index 0eb8ac0e23..dca4ee2f23 100644 --- a/variants/STM32WBxx/WB5MMGH/PeripheralPins.c +++ b/variants/STM32WBxx/WB5MMGH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WB5MMGHx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/PeripheralPins.c b/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/PeripheralPins.c index 7f67350081..60f3199d52 100644 --- a/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/PeripheralPins.c +++ b/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32WLE4C8Ux.xml, STM32WLE4CBUx.xml * STM32WLE4CCUx.xml, STM32WLE5C8Ux.xml * STM32WLE5CBUx.xml, STM32WLE5CCUx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I/PeripheralPins.c b/variants/STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I/PeripheralPins.c index 883c9cf3a3..7d0069371f 100644 --- a/variants/STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I/PeripheralPins.c +++ b/variants/STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I/PeripheralPins.c @@ -15,7 +15,7 @@ * STM32WLE4J8Ix.xml, STM32WLE4JBIx.xml * STM32WLE4JCIx.xml, STM32WLE5J8Ix.xml * STM32WLE5JBIx.xml, STM32WLE5JCIx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" diff --git a/variants/STM32WLxx/WL5MOCH/PeripheralPins.c b/variants/STM32WLxx/WL5MOCH/PeripheralPins.c index 1985f6516e..534041bc14 100644 --- a/variants/STM32WLxx/WL5MOCH/PeripheralPins.c +++ b/variants/STM32WLxx/WL5MOCH/PeripheralPins.c @@ -12,7 +12,7 @@ */ /* * Automatically generated from STM32WL5MOCHx.xml - * CubeMX DB release 6.0.140 + * CubeMX DB release 6.0.150 */ #if !defined(CUSTOM_PERIPHERAL_PINS) #include "Arduino.h" From e50f9fc5c1de3bede5cc033c375a4da4bebd2deb Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 21 Aug 2025 11:48:12 +0200 Subject: [PATCH 04/18] chore: update cmake after variants update Signed-off-by: Frederic Pillon --- cmake/boards_db.cmake | 788 +++++++++++++++++- .../STM32C0xx/C092C(B-C)(T-U)/CMakeLists.txt | 31 + .../C092RBT_C092RC(I-T)/CMakeLists.txt | 32 + variants/STM32G4xx/G491C(C-E)U/CMakeLists.txt | 31 + variants/STM32G4xx/G4A1CEU/CMakeLists.txt | 31 + 5 files changed, 904 insertions(+), 9 deletions(-) create mode 100644 variants/STM32C0xx/C092C(B-C)(T-U)/CMakeLists.txt create mode 100644 variants/STM32C0xx/C092RBT_C092RC(I-T)/CMakeLists.txt create mode 100644 variants/STM32G4xx/G491C(C-E)U/CMakeLists.txt create mode 100644 variants/STM32G4xx/G4A1CEU/CMakeLists.txt diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake index 45b9f43f7c..4f46d938e2 100644 --- a/cmake/boards_db.cmake +++ b/cmake/boards_db.cmake @@ -7621,7 +7621,7 @@ target_compile_options(GENERIC_C071RBTX_usb_none INTERFACE # GENERIC_C092CBTX # ----------------------------------------------------------------------------- -set(GENERIC_C092CBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)") +set(GENERIC_C092CBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092C(B-C)(T-U)") set(GENERIC_C092CBTX_MAXSIZE 131072) set(GENERIC_C092CBTX_MAXDATASIZE 30720) set(GENERIC_C092CBTX_MCU cortex-m0plus) @@ -7688,10 +7688,220 @@ target_compile_options(GENERIC_C092CBTX_usb_none INTERFACE "SHELL:" ) +# GENERIC_C092CBUX +# ----------------------------------------------------------------------------- + +set(GENERIC_C092CBUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092C(B-C)(T-U)") +set(GENERIC_C092CBUX_MAXSIZE 131072) +set(GENERIC_C092CBUX_MAXDATASIZE 30720) +set(GENERIC_C092CBUX_MCU cortex-m0plus) +set(GENERIC_C092CBUX_FPCONF "-") +add_library(GENERIC_C092CBUX INTERFACE) +target_compile_options(GENERIC_C092CBUX INTERFACE + "SHELL:-DSTM32C092xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_C092CBUX_MCU} +) +target_compile_definitions(GENERIC_C092CBUX INTERFACE + "STM32C0xx" + "ARDUINO_GENERIC_C092CBUX" + "BOARD_NAME=\"GENERIC_C092CBUX\"" + "BOARD_ID=GENERIC_C092CBUX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_C092CBUX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ + ${GENERIC_C092CBUX_VARIANT_PATH} +) + +target_link_options(GENERIC_C092CBUX INTERFACE + "LINKER:--default-script=${GENERIC_C092CBUX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=30720" + "SHELL: " + -mcpu=${GENERIC_C092CBUX_MCU} +) + +add_library(GENERIC_C092CBUX_serial_disabled INTERFACE) +target_compile_options(GENERIC_C092CBUX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_C092CBUX_serial_generic INTERFACE) +target_compile_options(GENERIC_C092CBUX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_C092CBUX_serial_none INTERFACE) +target_compile_options(GENERIC_C092CBUX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_C092CBUX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C092CBUX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C092CBUX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C092CBUX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C092CBUX_usb_HID INTERFACE) +target_compile_options(GENERIC_C092CBUX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C092CBUX_usb_none INTERFACE) +target_compile_options(GENERIC_C092CBUX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_C092CCTX +# ----------------------------------------------------------------------------- + +set(GENERIC_C092CCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092C(B-C)(T-U)") +set(GENERIC_C092CCTX_MAXSIZE 262144) +set(GENERIC_C092CCTX_MAXDATASIZE 30720) +set(GENERIC_C092CCTX_MCU cortex-m0plus) +set(GENERIC_C092CCTX_FPCONF "-") +add_library(GENERIC_C092CCTX INTERFACE) +target_compile_options(GENERIC_C092CCTX INTERFACE + "SHELL:-DSTM32C092xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_C092CCTX_MCU} +) +target_compile_definitions(GENERIC_C092CCTX INTERFACE + "STM32C0xx" + "ARDUINO_GENERIC_C092CCTX" + "BOARD_NAME=\"GENERIC_C092CCTX\"" + "BOARD_ID=GENERIC_C092CCTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_C092CCTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ + ${GENERIC_C092CCTX_VARIANT_PATH} +) + +target_link_options(GENERIC_C092CCTX INTERFACE + "LINKER:--default-script=${GENERIC_C092CCTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=30720" + "SHELL: " + -mcpu=${GENERIC_C092CCTX_MCU} +) + +add_library(GENERIC_C092CCTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_C092CCTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_C092CCTX_serial_generic INTERFACE) +target_compile_options(GENERIC_C092CCTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_C092CCTX_serial_none INTERFACE) +target_compile_options(GENERIC_C092CCTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_C092CCTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C092CCTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C092CCTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C092CCTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C092CCTX_usb_HID INTERFACE) +target_compile_options(GENERIC_C092CCTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C092CCTX_usb_none INTERFACE) +target_compile_options(GENERIC_C092CCTX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_C092CCUX +# ----------------------------------------------------------------------------- + +set(GENERIC_C092CCUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092C(B-C)(T-U)") +set(GENERIC_C092CCUX_MAXSIZE 262144) +set(GENERIC_C092CCUX_MAXDATASIZE 30720) +set(GENERIC_C092CCUX_MCU cortex-m0plus) +set(GENERIC_C092CCUX_FPCONF "-") +add_library(GENERIC_C092CCUX INTERFACE) +target_compile_options(GENERIC_C092CCUX INTERFACE + "SHELL:-DSTM32C092xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_C092CCUX_MCU} +) +target_compile_definitions(GENERIC_C092CCUX INTERFACE + "STM32C0xx" + "ARDUINO_GENERIC_C092CCUX" + "BOARD_NAME=\"GENERIC_C092CCUX\"" + "BOARD_ID=GENERIC_C092CCUX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_C092CCUX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ + ${GENERIC_C092CCUX_VARIANT_PATH} +) + +target_link_options(GENERIC_C092CCUX INTERFACE + "LINKER:--default-script=${GENERIC_C092CCUX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=30720" + "SHELL: " + -mcpu=${GENERIC_C092CCUX_MCU} +) + +add_library(GENERIC_C092CCUX_serial_disabled INTERFACE) +target_compile_options(GENERIC_C092CCUX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_C092CCUX_serial_generic INTERFACE) +target_compile_options(GENERIC_C092CCUX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_C092CCUX_serial_none INTERFACE) +target_compile_options(GENERIC_C092CCUX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_C092CCUX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C092CCUX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C092CCUX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C092CCUX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C092CCUX_usb_HID INTERFACE) +target_compile_options(GENERIC_C092CCUX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C092CCUX_usb_none INTERFACE) +target_compile_options(GENERIC_C092CCUX_usb_none INTERFACE + "SHELL:" +) + # GENERIC_C092RBTX # ----------------------------------------------------------------------------- -set(GENERIC_C092RBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)") +set(GENERIC_C092RBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092RBT_C092RC(I-T)") set(GENERIC_C092RBTX_MAXSIZE 131072) set(GENERIC_C092RBTX_MAXDATASIZE 30720) set(GENERIC_C092RBTX_MCU cortex-m0plus) @@ -7761,7 +7971,7 @@ target_compile_options(GENERIC_C092RBTX_usb_none INTERFACE # GENERIC_C092RCIX # ----------------------------------------------------------------------------- -set(GENERIC_C092RCIX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)") +set(GENERIC_C092RCIX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092RBT_C092RC(I-T)") set(GENERIC_C092RCIX_MAXSIZE 262144) set(GENERIC_C092RCIX_MAXDATASIZE 30720) set(GENERIC_C092RCIX_MCU cortex-m0plus) @@ -7831,7 +8041,7 @@ target_compile_options(GENERIC_C092RCIX_usb_none INTERFACE # GENERIC_C092RCTX # ----------------------------------------------------------------------------- -set(GENERIC_C092RCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)") +set(GENERIC_C092RCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092RBT_C092RC(I-T)") set(GENERIC_C092RCTX_MAXSIZE 262144) set(GENERIC_C092RCTX_MAXDATASIZE 30720) set(GENERIC_C092RCTX_MCU cortex-m0plus) @@ -101238,6 +101448,426 @@ target_compile_options(GENERIC_NODE_SE_TTI_serial_none INTERFACE "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" ) +# GENERIC_U073C8TX +# ----------------------------------------------------------------------------- + +set(GENERIC_U073C8TX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)") +set(GENERIC_U073C8TX_MAXSIZE 65536) +set(GENERIC_U073C8TX_MAXDATASIZE 40960) +set(GENERIC_U073C8TX_MCU cortex-m0plus) +set(GENERIC_U073C8TX_FPCONF "-") +add_library(GENERIC_U073C8TX INTERFACE) +target_compile_options(GENERIC_U073C8TX INTERFACE + "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U073C8TX_MCU} +) +target_compile_definitions(GENERIC_U073C8TX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U073C8TX" + "BOARD_NAME=\"GENERIC_U073C8TX\"" + "BOARD_ID=GENERIC_U073C8TX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U073C8TX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U073C8TX_VARIANT_PATH} +) + +target_link_options(GENERIC_U073C8TX INTERFACE + "LINKER:--default-script=${GENERIC_U073C8TX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=65536" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U073C8TX_MCU} +) + +add_library(GENERIC_U073C8TX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U073C8TX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U073C8TX_serial_generic INTERFACE) +target_compile_options(GENERIC_U073C8TX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U073C8TX_serial_none INTERFACE) +target_compile_options(GENERIC_U073C8TX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U073C8TX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U073C8TX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U073C8TX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U073C8TX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U073C8TX_usb_HID INTERFACE) +target_compile_options(GENERIC_U073C8TX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U073C8TX_usb_none INTERFACE) +target_compile_options(GENERIC_U073C8TX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_U073C8UX +# ----------------------------------------------------------------------------- + +set(GENERIC_U073C8UX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)") +set(GENERIC_U073C8UX_MAXSIZE 65536) +set(GENERIC_U073C8UX_MAXDATASIZE 40960) +set(GENERIC_U073C8UX_MCU cortex-m0plus) +set(GENERIC_U073C8UX_FPCONF "-") +add_library(GENERIC_U073C8UX INTERFACE) +target_compile_options(GENERIC_U073C8UX INTERFACE + "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U073C8UX_MCU} +) +target_compile_definitions(GENERIC_U073C8UX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U073C8UX" + "BOARD_NAME=\"GENERIC_U073C8UX\"" + "BOARD_ID=GENERIC_U073C8UX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U073C8UX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U073C8UX_VARIANT_PATH} +) + +target_link_options(GENERIC_U073C8UX INTERFACE + "LINKER:--default-script=${GENERIC_U073C8UX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=65536" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U073C8UX_MCU} +) + +add_library(GENERIC_U073C8UX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U073C8UX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U073C8UX_serial_generic INTERFACE) +target_compile_options(GENERIC_U073C8UX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U073C8UX_serial_none INTERFACE) +target_compile_options(GENERIC_U073C8UX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U073C8UX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U073C8UX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U073C8UX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U073C8UX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U073C8UX_usb_HID INTERFACE) +target_compile_options(GENERIC_U073C8UX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U073C8UX_usb_none INTERFACE) +target_compile_options(GENERIC_U073C8UX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_U073CBTX +# ----------------------------------------------------------------------------- + +set(GENERIC_U073CBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)") +set(GENERIC_U073CBTX_MAXSIZE 131072) +set(GENERIC_U073CBTX_MAXDATASIZE 40960) +set(GENERIC_U073CBTX_MCU cortex-m0plus) +set(GENERIC_U073CBTX_FPCONF "-") +add_library(GENERIC_U073CBTX INTERFACE) +target_compile_options(GENERIC_U073CBTX INTERFACE + "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U073CBTX_MCU} +) +target_compile_definitions(GENERIC_U073CBTX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U073CBTX" + "BOARD_NAME=\"GENERIC_U073CBTX\"" + "BOARD_ID=GENERIC_U073CBTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U073CBTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U073CBTX_VARIANT_PATH} +) + +target_link_options(GENERIC_U073CBTX INTERFACE + "LINKER:--default-script=${GENERIC_U073CBTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U073CBTX_MCU} +) + +add_library(GENERIC_U073CBTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U073CBTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U073CBTX_serial_generic INTERFACE) +target_compile_options(GENERIC_U073CBTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U073CBTX_serial_none INTERFACE) +target_compile_options(GENERIC_U073CBTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U073CBTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U073CBTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U073CBTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U073CBTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U073CBTX_usb_HID INTERFACE) +target_compile_options(GENERIC_U073CBTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U073CBTX_usb_none INTERFACE) +target_compile_options(GENERIC_U073CBTX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_U073CBUX +# ----------------------------------------------------------------------------- + +set(GENERIC_U073CBUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)") +set(GENERIC_U073CBUX_MAXSIZE 131072) +set(GENERIC_U073CBUX_MAXDATASIZE 40960) +set(GENERIC_U073CBUX_MCU cortex-m0plus) +set(GENERIC_U073CBUX_FPCONF "-") +add_library(GENERIC_U073CBUX INTERFACE) +target_compile_options(GENERIC_U073CBUX INTERFACE + "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U073CBUX_MCU} +) +target_compile_definitions(GENERIC_U073CBUX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U073CBUX" + "BOARD_NAME=\"GENERIC_U073CBUX\"" + "BOARD_ID=GENERIC_U073CBUX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U073CBUX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U073CBUX_VARIANT_PATH} +) + +target_link_options(GENERIC_U073CBUX INTERFACE + "LINKER:--default-script=${GENERIC_U073CBUX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U073CBUX_MCU} +) + +add_library(GENERIC_U073CBUX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U073CBUX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U073CBUX_serial_generic INTERFACE) +target_compile_options(GENERIC_U073CBUX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U073CBUX_serial_none INTERFACE) +target_compile_options(GENERIC_U073CBUX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U073CBUX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U073CBUX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U073CBUX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U073CBUX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U073CBUX_usb_HID INTERFACE) +target_compile_options(GENERIC_U073CBUX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U073CBUX_usb_none INTERFACE) +target_compile_options(GENERIC_U073CBUX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_U073CCTX +# ----------------------------------------------------------------------------- + +set(GENERIC_U073CCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)") +set(GENERIC_U073CCTX_MAXSIZE 262144) +set(GENERIC_U073CCTX_MAXDATASIZE 40960) +set(GENERIC_U073CCTX_MCU cortex-m0plus) +set(GENERIC_U073CCTX_FPCONF "-") +add_library(GENERIC_U073CCTX INTERFACE) +target_compile_options(GENERIC_U073CCTX INTERFACE + "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U073CCTX_MCU} +) +target_compile_definitions(GENERIC_U073CCTX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U073CCTX" + "BOARD_NAME=\"GENERIC_U073CCTX\"" + "BOARD_ID=GENERIC_U073CCTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U073CCTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U073CCTX_VARIANT_PATH} +) + +target_link_options(GENERIC_U073CCTX INTERFACE + "LINKER:--default-script=${GENERIC_U073CCTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U073CCTX_MCU} +) + +add_library(GENERIC_U073CCTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U073CCTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U073CCTX_serial_generic INTERFACE) +target_compile_options(GENERIC_U073CCTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U073CCTX_serial_none INTERFACE) +target_compile_options(GENERIC_U073CCTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U073CCTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U073CCTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U073CCTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U073CCTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U073CCTX_usb_HID INTERFACE) +target_compile_options(GENERIC_U073CCTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U073CCTX_usb_none INTERFACE) +target_compile_options(GENERIC_U073CCTX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_U073CCUX +# ----------------------------------------------------------------------------- + +set(GENERIC_U073CCUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)") +set(GENERIC_U073CCUX_MAXSIZE 262144) +set(GENERIC_U073CCUX_MAXDATASIZE 40960) +set(GENERIC_U073CCUX_MCU cortex-m0plus) +set(GENERIC_U073CCUX_FPCONF "-") +add_library(GENERIC_U073CCUX INTERFACE) +target_compile_options(GENERIC_U073CCUX INTERFACE + "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U073CCUX_MCU} +) +target_compile_definitions(GENERIC_U073CCUX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U073CCUX" + "BOARD_NAME=\"GENERIC_U073CCUX\"" + "BOARD_ID=GENERIC_U073CCUX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U073CCUX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U073CCUX_VARIANT_PATH} +) + +target_link_options(GENERIC_U073CCUX INTERFACE + "LINKER:--default-script=${GENERIC_U073CCUX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U073CCUX_MCU} +) + +add_library(GENERIC_U073CCUX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U073CCUX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U073CCUX_serial_generic INTERFACE) +target_compile_options(GENERIC_U073CCUX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U073CCUX_serial_none INTERFACE) +target_compile_options(GENERIC_U073CCUX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U073CCUX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U073CCUX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U073CCUX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U073CCUX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U073CCUX_usb_HID INTERFACE) +target_compile_options(GENERIC_U073CCUX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U073CCUX_usb_none INTERFACE) +target_compile_options(GENERIC_U073CCUX_usb_none INTERFACE + "SHELL:" +) + # GENERIC_U073R8IX # ----------------------------------------------------------------------------- @@ -101658,6 +102288,146 @@ target_compile_options(GENERIC_U073RCTX_usb_none INTERFACE "SHELL:" ) +# GENERIC_U083CCTX +# ----------------------------------------------------------------------------- + +set(GENERIC_U083CCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)") +set(GENERIC_U083CCTX_MAXSIZE 262144) +set(GENERIC_U083CCTX_MAXDATASIZE 40960) +set(GENERIC_U083CCTX_MCU cortex-m0plus) +set(GENERIC_U083CCTX_FPCONF "-") +add_library(GENERIC_U083CCTX INTERFACE) +target_compile_options(GENERIC_U083CCTX INTERFACE + "SHELL:-DSTM32U083xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U083CCTX_MCU} +) +target_compile_definitions(GENERIC_U083CCTX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U083CCTX" + "BOARD_NAME=\"GENERIC_U083CCTX\"" + "BOARD_ID=GENERIC_U083CCTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U083CCTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U083CCTX_VARIANT_PATH} +) + +target_link_options(GENERIC_U083CCTX INTERFACE + "LINKER:--default-script=${GENERIC_U083CCTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U083CCTX_MCU} +) + +add_library(GENERIC_U083CCTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U083CCTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U083CCTX_serial_generic INTERFACE) +target_compile_options(GENERIC_U083CCTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U083CCTX_serial_none INTERFACE) +target_compile_options(GENERIC_U083CCTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U083CCTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U083CCTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U083CCTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U083CCTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U083CCTX_usb_HID INTERFACE) +target_compile_options(GENERIC_U083CCTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U083CCTX_usb_none INTERFACE) +target_compile_options(GENERIC_U083CCTX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_U083CCUX +# ----------------------------------------------------------------------------- + +set(GENERIC_U083CCUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)") +set(GENERIC_U083CCUX_MAXSIZE 262144) +set(GENERIC_U083CCUX_MAXDATASIZE 40960) +set(GENERIC_U083CCUX_MCU cortex-m0plus) +set(GENERIC_U083CCUX_FPCONF "-") +add_library(GENERIC_U083CCUX INTERFACE) +target_compile_options(GENERIC_U083CCUX INTERFACE + "SHELL:-DSTM32U083xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U083CCUX_MCU} +) +target_compile_definitions(GENERIC_U083CCUX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U083CCUX" + "BOARD_NAME=\"GENERIC_U083CCUX\"" + "BOARD_ID=GENERIC_U083CCUX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U083CCUX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U083CCUX_VARIANT_PATH} +) + +target_link_options(GENERIC_U083CCUX INTERFACE + "LINKER:--default-script=${GENERIC_U083CCUX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U083CCUX_MCU} +) + +add_library(GENERIC_U083CCUX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U083CCUX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U083CCUX_serial_generic INTERFACE) +target_compile_options(GENERIC_U083CCUX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U083CCUX_serial_none INTERFACE) +target_compile_options(GENERIC_U083CCUX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U083CCUX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U083CCUX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U083CCUX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U083CCUX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U083CCUX_usb_HID INTERFACE) +target_compile_options(GENERIC_U083CCUX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U083CCUX_usb_none INTERFACE) +target_compile_options(GENERIC_U083CCUX_usb_none INTERFACE + "SHELL:" +) + # GENERIC_U083RCIX # ----------------------------------------------------------------------------- @@ -104699,7 +105469,7 @@ target_compile_options(GENERIC_WB55VCYX_xusb_HSFS INTERFACE set(GENERIC_WB55VEQX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY") set(GENERIC_WB55VEQX_MAXSIZE 262144) -set(GENERIC_WB55VEQX_MAXDATASIZE 65536) +set(GENERIC_WB55VEQX_MAXDATASIZE 131072) set(GENERIC_WB55VEQX_MCU cortex-m4) set(GENERIC_WB55VEQX_FPCONF "-") add_library(GENERIC_WB55VEQX INTERFACE) @@ -104730,7 +105500,7 @@ target_link_options(GENERIC_WB55VEQX INTERFACE "LINKER:--default-script=${GENERIC_WB55VEQX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=262144" - "LINKER:--defsym=LD_MAX_DATA_SIZE=65536" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_WB55VEQX_MCU} ) @@ -104863,7 +105633,7 @@ target_compile_options(GENERIC_WB55VEYX_xusb_HSFS INTERFACE set(GENERIC_WB55VGQX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY") set(GENERIC_WB55VGQX_MAXSIZE 524288) -set(GENERIC_WB55VGQX_MAXDATASIZE 65536) +set(GENERIC_WB55VGQX_MAXDATASIZE 131072) set(GENERIC_WB55VGQX_MCU cortex-m4) set(GENERIC_WB55VGQX_FPCONF "-") add_library(GENERIC_WB55VGQX INTERFACE) @@ -104894,7 +105664,7 @@ target_link_options(GENERIC_WB55VGQX INTERFACE "LINKER:--default-script=${GENERIC_WB55VGQX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=524288" - "LINKER:--defsym=LD_MAX_DATA_SIZE=65536" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_WB55VGQX_MCU} ) @@ -107275,7 +108045,7 @@ target_compile_options(NUCLEO_C071RB_xusb_HSFS INTERFACE # NUCLEO_C092RC # ----------------------------------------------------------------------------- -set(NUCLEO_C092RC_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)") +set(NUCLEO_C092RC_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092RBT_C092RC(I-T)") set(NUCLEO_C092RC_MAXSIZE 262144) set(NUCLEO_C092RC_MAXDATASIZE 30720) set(NUCLEO_C092RC_MCU cortex-m0plus) diff --git a/variants/STM32C0xx/C092C(B-C)(T-U)/CMakeLists.txt b/variants/STM32C0xx/C092C(B-C)(T-U)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32C0xx/C092C(B-C)(T-U)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32C0xx/C092RBT_C092RC(I-T)/CMakeLists.txt b/variants/STM32C0xx/C092RBT_C092RC(I-T)/CMakeLists.txt new file mode 100644 index 0000000000..52db19363f --- /dev/null +++ b/variants/STM32C0xx/C092RBT_C092RC(I-T)/CMakeLists.txt @@ -0,0 +1,32 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp + variant_NUCLEO_C092RC.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32G4xx/G491C(C-E)U/CMakeLists.txt b/variants/STM32G4xx/G491C(C-E)U/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32G4xx/G491C(C-E)U/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32G4xx/G4A1CEU/CMakeLists.txt b/variants/STM32G4xx/G4A1CEU/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32G4xx/G4A1CEU/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + From 7f7437d0aaa373c141609db6229d4bb8ca8e845d Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 21 Aug 2025 11:49:26 +0200 Subject: [PATCH 05/18] chore(ci): update generics list to skip Signed-off-by: Frederic Pillon --- CI/build/conf/cores_config.json | 19 +++++++++++++++++++ CI/build/conf/cores_config_ci.json | 19 +++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/CI/build/conf/cores_config.json b/CI/build/conf/cores_config.json index 7cdc1022ca..32b2772a00 100644 --- a/CI/build/conf/cores_config.json +++ b/CI/build/conf/cores_config.json @@ -48,7 +48,11 @@ "GENERIC_C031C4UX", "GENERIC_C031C6TX", "GENERIC_C031F4PX", + "GENERIC_C071G8UX", "GENERIC_C071R8TX", + "GENERIC_C092CBTX", + "GENERIC_C092CBUX", + "GENERIC_C092CCTX", "GENERIC_F031C4TX", "GENERIC_F031E6YX", "GENERIC_F031F4PX", @@ -835,12 +839,19 @@ "GENERIC_MP157AACX", "GENERIC_MP157CACX", "GENERIC_MP157DACX", + "GENERIC_U073C8TX", + "GENERIC_U073C8UX", + "GENERIC_U073CBTX", + "GENERIC_U073CBUX", + "GENERIC_U073CCTX", + "GENERIC_U073CCUX", "GENERIC_U073R8IX", "GENERIC_U073R8TX", "GENERIC_U073RBIX", "GENERIC_U073RBTX", "GENERIC_U073RCIX", "GENERIC_U073RCTX", + "GENERIC_U083CCTX", "GENERIC_U083RCIX", "GENERIC_U375RETXQ", "GENERIC_U375RGTXQ", @@ -857,6 +868,14 @@ "GENERIC_U575ZGTXQ", "GENERIC_U575ZITXQ", "GENERIC_U585CITX", + "GENERIC_U595ZITXQ", + "GENERIC_U595ZJTXQ", + "GENERIC_U599ZITXQ", + "GENERIC_U599ZJTXQ", + "GENERIC_U5A5ZJTXQ", + "GENERIC_WB05KZVX", + "GENERIC_WB05TZFX", + "GENERIC_WB09KEVX", "GENERIC_WB35CCUXA", "GENERIC_WB35CEUXA", "GENERIC_WB55CCUX", diff --git a/CI/build/conf/cores_config_ci.json b/CI/build/conf/cores_config_ci.json index 267c32f85c..b6c3685313 100644 --- a/CI/build/conf/cores_config_ci.json +++ b/CI/build/conf/cores_config_ci.json @@ -48,7 +48,11 @@ "GENERIC_C031C4UX", "GENERIC_C031C6TX", "GENERIC_C031F4PX", + "GENERIC_C071G8UX", "GENERIC_C071R8TX", + "GENERIC_C092CBTX", + "GENERIC_C092CBUX", + "GENERIC_C092CCTX", "GENERIC_F031C4TX", "GENERIC_F031E6YX", "GENERIC_F031F4PX", @@ -835,12 +839,19 @@ "GENERIC_MP157AACX", "GENERIC_MP157CACX", "GENERIC_MP157DACX", + "GENERIC_U073C8TX", + "GENERIC_U073C8UX", + "GENERIC_U073CBTX", + "GENERIC_U073CBUX", + "GENERIC_U073CCTX", + "GENERIC_U073CCUX", "GENERIC_U073R8IX", "GENERIC_U073R8TX", "GENERIC_U073RBIX", "GENERIC_U073RBTX", "GENERIC_U073RCIX", "GENERIC_U073RCTX", + "GENERIC_U083CCTX", "GENERIC_U083RCIX", "GENERIC_U375RETXQ", "GENERIC_U375RGTXQ", @@ -857,6 +868,14 @@ "GENERIC_U575ZGTXQ", "GENERIC_U575ZITXQ", "GENERIC_U585CITX", + "GENERIC_U595ZITXQ", + "GENERIC_U595ZJTXQ", + "GENERIC_U599ZITXQ", + "GENERIC_U599ZJTXQ", + "GENERIC_U5A5ZJTXQ", + "GENERIC_WB05KZVX", + "GENERIC_WB05TZFX", + "GENERIC_WB09KEVX", "GENERIC_WB35CCUXA", "GENERIC_WB35CEUXA", "GENERIC_WB55CCUX", From af53c10784883253e07a9ed45e269783f96a9f40 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 25 Aug 2025 09:52:57 +0200 Subject: [PATCH 06/18] system(f4) update STM32F4xx HAL Drivers to v1.8.5 Included in STM32CubeF4 FW v1.28.3 Signed-off-by: Frederic Pillon --- .../STM32F4xx_HAL_Driver/Release_Notes.html | 84 +++++++++++-------- .../STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c | 4 +- .../Src/stm32f4xx_hal_flash.c | 9 +- .../Src/stm32f4xx_hal_mmc.c | 2 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 5 files changed, 62 insertions(+), 39 deletions(-) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html index 5cba24b0f0..e50efebbea 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html @@ -40,10 +40,26 @@

Purpose

Update History

- +

Main Changes

    +
  • HAL SDMMC +
      +
    • Update to use dedicated MMC defines in the HAL SDMMC driver.
      • +
    • +
  • HAL FLASH +
      +
    • Initialize the ‘pFlash’ variable with default values.
      • +
    • +
+
+
+
+ +
+

Main Changes

+
  • Enhance HAL code quality for MISRA-C 2012 Rule-8.13 by adding const qualifiers.
  • HAL RTC
      @@ -119,7 +135,7 @@

      Main Changes

      -

      Main Changes

      +

      Main Changes

      • Enhance HAL code quality for MISRA-C Rule-8.13 by adding const qualifiers.
      • HAL Generic @@ -212,7 +228,7 @@

        Main Changes

        -

        Main Changes

        +

        Main Changes

        • General updates to fix known defects and implementation enhancements.
        • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.
          • @@ -389,7 +405,7 @@

          Main Changes

          -

          Main Changes

          +

          Main Changes

          • General updates to fix HAL ETH defects and implementation enhancements.
          • HAL updates @@ -409,7 +425,7 @@

            Main Changes

            -

            Main Changes

            +

            Main Changes

            • General updates to fix known defects and implementation enhancements.
            • All source files: update disclaimer to add reference to the new license agreement.
              • @@ -591,7 +607,7 @@

              Main Changes

              -

              Main Changes

              +

              Main Changes

              • HAL update
                  @@ -680,7 +696,7 @@

                  Main Changes

                  -

                  Main Changes

                  +

                  Main Changes

                  • HAL
                      @@ -695,7 +711,7 @@

                      Main Changes

                      -

                      Main Changes

                      +

                      Main Changes

                      • General updates to fix known defects and enhancements implementation
                      • Added new HAL FMPSMBUS extended driver to support FMPSMBUS fast Mode Plus.
                        • @@ -922,7 +938,7 @@

                        Main Changes

                        -

                        Main Changes

                        +

                        Main Changes

                        • General updates to fix known defects.
                        • HAL/LL I2C update @@ -938,7 +954,7 @@

                          Main Changes

                          -

                          Main Changes

                          +

                          Main Changes

                          • General updates to fix known defects and enhancements implementation
                          • HAL/LL I2C update @@ -971,7 +987,7 @@

                            Main Changes

                            -

                            Main Changes

                            +

                            Main Changes

                            • Add new HAL FMPSMBUS and LL FMPI2C drivers
                            • General updates to fix known defects and enhancements implementation
                              • @@ -1010,7 +1026,7 @@

                              Main Changes

                              -

                              Main Changes

                              +

                              Main Changes

                              • General updates to fix known defects and enhancements implementation
                              • HAL Generic update @@ -1378,7 +1394,7 @@

                                Main Changes

                                -

                                Main Changes

                                +

                                Main Changes

                                • General updates to fix known defects and enhancements implementation
                                • HAL I2C update @@ -1415,7 +1431,7 @@

                                  Main Changes

                                  -

                                  Main Changes

                                  +

                                  Main Changes

                                  • General updates to fix known defects and enhancements implementation
                                  • General updates to fix CodeSonar compilation warnings
                                    • @@ -1686,7 +1702,7 @@

                                    Main Changes

                                    -

                                    Main Changes

                                    +

                                    Main Changes

                                    • General updates to fix known defects and enhancements implementation
                                    • HAL update @@ -1717,7 +1733,7 @@

                                      Main Changes

                                      -

                                      Main Changes

                                      +

                                      Main Changes

                                      • General updates to fix known defects and enhancements implementation
                                      • The following changes done on the HAL drivers require an update on the application code based on older HAL versions @@ -1800,7 +1816,7 @@

                                        Main Changes

                                        -

                                        Main Changes

                                        +

                                        Main Changes

                                        • General updates to fix known defects and enhancements implementation
                                        • Fix compilation warning with GCC compiler
                                          • @@ -1931,7 +1947,7 @@

                                          Main Changes

                                          -

                                          Main Changes

                                          +

                                          Main Changes

                                          • Update CHM UserManuals to support LL drivers
                                          • General updates to fix known defects and enhancements implementation
                                            • @@ -1961,7 +1977,7 @@

                                            Main Changes

                                            -

                                            Main Changes

                                            +

                                            Main Changes

                                            • Add Low Layer drivers allowing performance and footprint optimization
                                                @@ -2135,7 +2151,7 @@

                                                Main Changes

                                                -

                                                Main Changes

                                                +

                                                Main Changes

                                                • Add support of STM32F413xx and STM32F423xx devices
                                                • General updates to fix known defects and enhancements implementation
                                                  • @@ -2242,7 +2258,7 @@

                                                  Main Changes

                                                  -

                                                  Main Changes

                                                  +

                                                  Main Changes

                                                  • HAL I2C update
                                                      @@ -2273,7 +2289,7 @@

                                                      Main Changes

                                                      -

                                                      Main Changes

                                                      +

                                                      Main Changes

                                                      • HAL GPIO update
                                                          @@ -2305,7 +2321,7 @@

                                                          Main Changes

                                                          -

                                                          Main Changes

                                                          +

                                                          Main Changes

                                                          • Add support of STM32F412cx, STM32F412rx, STM32F412vx and STM32F412zx devices
                                                          • General updates to fix known defects and enhancements implementation
                                                            • @@ -2681,7 +2697,7 @@

                                                            Main Changes

                                                            -

                                                            Main Changes

                                                            +

                                                            Main Changes

                                                            • HAL Generic update
                                                                @@ -2915,7 +2931,7 @@

                                                                Main Changes

                                                                -

                                                                Main Changes

                                                                +

                                                                Main Changes

                                                                • HAL Generic update
                                                                    @@ -2935,7 +2951,7 @@

                                                                    Main Changes

                                                                    -

                                                                    Main Changes

                                                                    +

                                                                    Main Changes

                                                                    • General updates to fix known defects and enhancements implementation
                                                                      • @@ -3021,7 +3037,7 @@

                                                                      Main Changes

                                                                      -

                                                                      Main Changes

                                                                      +

                                                                      Main Changes

                                                                      • HAL DSI update
                                                                          @@ -3036,7 +3052,7 @@

                                                                          Main Changes

                                                                          -

                                                                          Main Changes

                                                                          +

                                                                          Main Changes

                                                                          • Add support of STM32F469xx, STM32F479xx, STM32F410Cx, STM32F410Rx and STM32F410Tx devices
                                                                          • General updates to fix known defects and enhancements implementation
                                                                            • @@ -3114,7 +3130,7 @@

                                                                            Main Changes

                                                                            -

                                                                            Main Changes

                                                                            +

                                                                            Main Changes

                                                                            • General updates to fix known defects and enhancements implementation
                                                                            • One changes done on the HAL may require an update on the application code based on HAL V1.3.1 @@ -3222,7 +3238,7 @@

                                                                              Main Changes

                                                                              -

                                                                              Main Changes

                                                                              +

                                                                              Main Changes

                                                                              • HAL PWR update
                                                                                  @@ -3248,7 +3264,7 @@

                                                                                  Main Changes

                                                                                  -

                                                                                  Main Changes

                                                                                  +

                                                                                  Main Changes

                                                                                  • Add support of STM32F446xx devices
                                                                                  • General updates to fix known defects and enhancements implementation
                                                                                    • @@ -3510,7 +3526,7 @@

                                                                                    Main Changes

                                                                                    -

                                                                                    Main Changes

                                                                                    +

                                                                                    Main Changes

                                                                                    • Maintenance release to fix known defects and enhancements implementation
                                                                                    • Macros and literals renaming to ensure compatibles across STM32 series, backward compatibility maintained thanks to new added file stm32_hal_legacy.h under /Inc/Legacy
                                                                                      • @@ -4041,7 +4057,7 @@

                                                                                      Main Changes

                                                                                      -

                                                                                      Main Changes

                                                                                      +

                                                                                      Main Changes

                                                                                      • Add support of STM32F411xE devices
                                                                                      • HAL generic update @@ -4343,7 +4359,7 @@

                                                                                        Main Changes

                                                                                        -

                                                                                        Main Changes

                                                                                        +

                                                                                        Main Changes

                                                                                        • First official release
                                                                                        diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c index eb118631e5..2e5f67ef1d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c @@ -50,11 +50,11 @@ * @{ */ /** - * @brief STM32F4xx HAL Driver version number V1.8.4 + * @brief STM32F4xx HAL Driver version number V1.8.5 */ #define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32F4xx_HAL_VERSION_SUB1 (0x08U) /*!< [23:16] sub1 version */ -#define __STM32F4xx_HAL_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */ +#define __STM32F4xx_HAL_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */ #define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\ |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c index 29c60e327d..808949ea2d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c @@ -101,7 +101,14 @@ * @{ */ /* Variable used for Erase sectors under interruption */ -FLASH_ProcessTypeDef pFlash; +FLASH_ProcessTypeDef pFlash = {.ProcedureOnGoing = FLASH_PROC_NONE, + .NbSectorsToErase = 0U, + .VoltageForErase= FLASH_VOLTAGE_RANGE_1, + .Sector = 0U, + .Bank = FLASH_BANK_1, + .Address = 0U, + .Lock = HAL_UNLOCKED, + .ErrorCode = HAL_FLASH_ERROR_NONE}; /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.c index 4d60e274e6..aab51197e9 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.c @@ -1689,7 +1689,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) } } } - else if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + else if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) { if(hmmc->hdmarx != NULL) { diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index e1f4f13cff..466989018d 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -5,7 +5,7 @@ * STM32F1: 1.1.10 * STM32F2: 1.2.9 * STM32F3: 1.5.8 - * STM32F4: 1.8.4 + * STM32F4: 1.8.5 * STM32F7: 1.3.2 * STM32G0: 1.4.6 * STM32G4: 1.2.5 From 34d7699ff83ece262d48b87da592f0a7f7078194 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 25 Aug 2025 09:57:20 +0200 Subject: [PATCH 07/18] system(f7) update STM32F7xx HAL Drivers to v1.3.3 Included in STM32CubeF7 FW v1.17.4 Signed-off-by: Frederic Pillon --- .../STM32F7xx_HAL_Driver/Release_Notes.html | 21 ++++++++++++++++++- .../STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c | 4 ++-- .../Src/stm32f7xx_hal_flash.c | 8 ++++++- .../Src/stm32f7xx_hal_mmc.c | 2 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 5 files changed, 31 insertions(+), 6 deletions(-) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32F7xx_HAL_Driver/Release_Notes.html index e137e2a5a3..4e9425953c 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32F7xx_HAL_Driver/Release_Notes.html @@ -32,7 +32,26 @@

                                                                                        Purpose

                                                                                        Update History

                                                                                        - + +
                                                                                        +

                                                                                        Main Changes

                                                                                        +
                                                                                          +
                                                                                        • HAL +
                                                                                            +
                                                                                          • HAL SDMMC +
                                                                                              +
                                                                                            • Update to use dedicated MMC defines in the HAL SDMMC driver.
                                                                                              • +
                                                                                            • +
                                                                                          • HAL FLASH +
                                                                                              +
                                                                                            • Initialize the ‘pFlash’ variable with default values.
                                                                                              • +
                                                                                            • +
                                                                                          • +
                                                                                        +
                                                                                        +
                                                                                        +
                                                                                        +

                                                                                        Main Changes

                                                                                          diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c index ecfa0196f2..fce11ea716 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c @@ -50,11 +50,11 @@ * @{ */ /** - * @brief STM32F7xx HAL Driver version number V1.3.2 + * @brief STM32F7xx HAL Driver version number V1.3.3 */ #define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32F7xx_HAL_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F7xx_HAL_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ +#define __STM32F7xx_HAL_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ #define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\ |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c index d7be4a69d3..77ab1d0b70 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c @@ -109,7 +109,13 @@ * @{ */ /* Variable used for Erase sectors under interruption */ -FLASH_ProcessTypeDef pFlash; +FLASH_ProcessTypeDef pFlash = {.ProcedureOnGoing = FLASH_PROC_NONE, + .NbSectorsToErase = 0U, + .VoltageForErase= FLASH_VOLTAGE_RANGE_1, + .Sector = 0U, + .Address = 0U, + .Lock = HAL_UNLOCKED, + .ErrorCode = HAL_FLASH_ERROR_NONE}; /** * @} */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mmc.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mmc.c index 635bed26a1..15c367b465 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mmc.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mmc.c @@ -1641,7 +1641,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) } } } - else if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + else if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) { if(hmmc->hdmarx != NULL) { diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 466989018d..afc78821f7 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -6,7 +6,7 @@ * STM32F2: 1.2.9 * STM32F3: 1.5.8 * STM32F4: 1.8.5 - * STM32F7: 1.3.2 + * STM32F7: 1.3.3 * STM32G0: 1.4.6 * STM32G4: 1.2.5 * STM32H5: 1.5.0 From 2095f5307e67c5224c171a4e8d97773cd8e5be82 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 28 Nov 2023 11:04:07 +0100 Subject: [PATCH 08/18] feat(spi): add slave mode support Signed-off-by: patricklaf Co-authored-by: Frederic Pillon --- libraries/SPI/keywords.txt | 7 ++++-- libraries/SPI/src/SPI.cpp | 31 +++++++++++-------------- libraries/SPI/src/SPI.h | 36 +++++++++++++++++++++-------- libraries/SPI/src/utility/spi_com.c | 7 +++--- libraries/SPI/src/utility/spi_com.h | 8 ++++++- 5 files changed, 56 insertions(+), 33 deletions(-) diff --git a/libraries/SPI/keywords.txt b/libraries/SPI/keywords.txt index 18701284e0..4bf7e9bc16 100644 --- a/libraries/SPI/keywords.txt +++ b/libraries/SPI/keywords.txt @@ -30,5 +30,8 @@ SPI_MODE1 LITERAL1 SPI_MODE2 LITERAL1 SPI_MODE3 LITERAL1 -SPI_CONTINUE LITERAL1 -SPI_LAST LITERAL1 +SPI_TRANSMITRECEIVE LITERAL1 +SPI_TRANSMITONLY LITERAL1 +SPI_MASTER LITERAL1 +SPI_SLAVE LITERAL1 + diff --git a/libraries/SPI/src/SPI.cpp b/libraries/SPI/src/SPI.cpp index f77b48c59b..3e6253c70d 100644 --- a/libraries/SPI/src/SPI.cpp +++ b/libraries/SPI/src/SPI.cpp @@ -46,28 +46,28 @@ SPIClass::SPIClass(uint32_t mosi, uint32_t miso, uint32_t sclk, uint32_t ssel) /** * @brief Initialize the SPI instance. + * @param device: device mode (optional), SPI_MASTER or SPI_SLAVE. Default is master. */ -void SPIClass::begin(void) +void SPIClass::begin(SPIDeviceMode device) { _spi.handle.State = HAL_SPI_STATE_RESET; _spiSettings = SPISettings(); - spi_init(&_spi, _spiSettings.clockFreq, - _spiSettings.dataMode, - _spiSettings.bitOrder); + _spiSettings.deviceMode = device; + spi_init(&_spi, _spiSettings.clockFreq, _spiSettings.dataMode, + _spiSettings.bitOrder, _spiSettings.deviceMode); } /** * @brief This function should be used to configure the SPI instance in case you * don't use the default parameters set by the begin() function. - * @param settings: SPI settings(clock speed, bit order, data mode). + * @param settings: SPI settings(clock speed, bit order, data mode, device mode). */ void SPIClass::beginTransaction(SPISettings settings) { if (_spiSettings != settings) { _spiSettings = settings; - spi_init(&_spi, _spiSettings.clockFreq, - _spiSettings.dataMode, - _spiSettings.bitOrder); + spi_init(&_spi, _spiSettings.clockFreq, _spiSettings.dataMode, + _spiSettings.bitOrder, _spiSettings.deviceMode); } } @@ -96,9 +96,8 @@ void SPIClass::setBitOrder(BitOrder bitOrder) { _spiSettings.bitOrder = bitOrder; - spi_init(&_spi, _spiSettings.clockFreq, - _spiSettings.dataMode, - _spiSettings.bitOrder); + spi_init(&_spi, _spiSettings.clockFreq, _spiSettings.dataMode, + _spiSettings.bitOrder, _spiSettings.deviceMode); } /** @@ -120,9 +119,8 @@ void SPIClass::setDataMode(uint8_t mode) void SPIClass::setDataMode(SPIMode mode) { _spiSettings.dataMode = mode; - spi_init(&_spi, _spiSettings.clockFreq, - _spiSettings.dataMode, - _spiSettings.bitOrder); + spi_init(&_spi, _spiSettings.clockFreq, _spiSettings.dataMode, + _spiSettings.bitOrder, _spiSettings.deviceMode); } /** @@ -140,9 +138,8 @@ void SPIClass::setClockDivider(uint8_t divider) _spiSettings.clockFreq = spi_getClkFreq(&_spi) / divider; } - spi_init(&_spi, _spiSettings.clockFreq, - _spiSettings.dataMode, - _spiSettings.bitOrder); + spi_init(&_spi, _spiSettings.clockFreq, _spiSettings.dataMode, + _spiSettings.bitOrder, _spiSettings.deviceMode); } /** diff --git a/libraries/SPI/src/SPI.h b/libraries/SPI/src/SPI.h index a558f5f05c..07a42134bb 100644 --- a/libraries/SPI/src/SPI.h +++ b/libraries/SPI/src/SPI.h @@ -43,27 +43,31 @@ extern "C" { class SPISettings { public: - constexpr SPISettings(uint32_t clock, BitOrder bitOrder, uint8_t dataMode) + constexpr SPISettings(uint32_t clock, BitOrder bitOrder, uint8_t dataMode, SPIDeviceMode deviceMode = SPI_MASTER) : clockFreq(clock), bitOrder(bitOrder), - dataMode((SPIMode)dataMode) + dataMode((SPIMode)dataMode), + deviceMode(deviceMode) { } - constexpr SPISettings(uint32_t clock, BitOrder bitOrder, SPIMode dataMode) + constexpr SPISettings(uint32_t clock, BitOrder bitOrder, SPIMode dataMode, SPIDeviceMode deviceMode = SPI_MASTER) : clockFreq(clock), bitOrder(bitOrder), - dataMode(dataMode) + dataMode(dataMode), + deviceMode(deviceMode) { } constexpr SPISettings() : clockFreq(SPI_SPEED_CLOCK_DEFAULT), bitOrder(MSBFIRST), - dataMode(SPI_MODE0) + dataMode(SPI_MODE0), + deviceMode(SPI_MASTER) { } bool operator==(const SPISettings &rhs) const { if ((this->clockFreq == rhs.clockFreq) && (this->bitOrder == rhs.bitOrder) && - (this->dataMode == rhs.dataMode)) { + (this->dataMode == rhs.dataMode) && + (this->deviceMode == rhs.deviceMode)) { return true; } return false; @@ -75,9 +79,10 @@ class SPISettings { } private: - uint32_t clockFreq; //specifies the spi bus maximum clock speed - BitOrder bitOrder; //bit order (MSBFirst or LSBFirst) - SPIMode dataMode; //one of the data mode + uint32_t clockFreq; // specifies the spi bus maximum clock speed + BitOrder bitOrder; // bit order (MSBFirst or LSBFirst) + SPIMode dataMode; // one of the data mode + SPIDeviceMode deviceMode; // device mode: master or slave friend class SPIClass; }; @@ -121,7 +126,7 @@ class SPIClass { _spi.pin_ssel = (ssel); }; - void begin(void); + void begin(SPIDeviceMode device = SPI_MASTER); void end(void); /* This function should be used to configure the SPI instance in case you @@ -162,6 +167,17 @@ class SPIClass { return &(_spi.handle); } + // Dedicated to SPI Slave + void attachSlaveInterrupt(uint8_t pin, callback_function_t callback) + { + ::attachInterrupt(pin, callback, FALLING); + } + + void detachSlaveInterrupt(uint8_t pin) + { + ::detachInterrupt(pin); + } + protected: // spi instance spi_t _spi; diff --git a/libraries/SPI/src/utility/spi_com.c b/libraries/SPI/src/utility/spi_com.c index 8bdb56f303..3fc4d6ef76 100644 --- a/libraries/SPI/src/utility/spi_com.c +++ b/libraries/SPI/src/utility/spi_com.c @@ -203,9 +203,10 @@ static uint32_t compute_disable_delay(spi_t *obj) * @param speed : spi output speed * @param mode : one of the spi modes * @param msb : set to 1 in msb first + * @param device : spi device mode: master or slave * @retval None */ -void spi_init(spi_t *obj, uint32_t speed, SPIMode mode, uint8_t msb) +void spi_init(spi_t *obj, uint32_t speed, SPIMode mode, uint8_t msb, SPIDeviceMode device) { if (obj == NULL) { return; @@ -257,8 +258,8 @@ void spi_init(spi_t *obj, uint32_t speed, SPIMode mode, uint8_t msb) } /* Fill default value */ - handle->Instance = obj->spi; - handle->Init.Mode = SPI_MODE_MASTER; + handle->Instance = obj->spi; + handle->Init.Mode = (device == SPI_MASTER) ? SPI_MODE_MASTER : SPI_MODE_SLAVE; spi_freq = spi_getClkFreqInst(obj->spi); /* For SUBGHZSPI, 'SPI_BAUDRATEPRESCALER_*' == 'SUBGHZSPI_BAUDRATEPRESCALER_*' */ diff --git a/libraries/SPI/src/utility/spi_com.h b/libraries/SPI/src/utility/spi_com.h index 4d145ff7fd..cdde9ed0d2 100644 --- a/libraries/SPI/src/utility/spi_com.h +++ b/libraries/SPI/src/utility/spi_com.h @@ -74,6 +74,12 @@ typedef enum { SPI_MODE3 = 3, } SPIMode; +// Device mode +typedef enum { + SPI_MASTER, /* Device is master */ + SPI_SLAVE /* Device is slave */ +} SPIDeviceMode; + ///@brief SPI errors typedef enum { SPI_OK = 0, @@ -82,7 +88,7 @@ typedef enum { } spi_status_e; /* Exported functions ------------------------------------------------------- */ -void spi_init(spi_t *obj, uint32_t speed, SPIMode mode, uint8_t msb); +void spi_init(spi_t *obj, uint32_t speed, SPIMode mode, uint8_t msb, SPIDeviceMode device); void spi_deinit(spi_t *obj); spi_status_e spi_transfer(spi_t *obj, const uint8_t *tx_buffer, uint8_t *rx_buffer, uint16_t len); uint32_t spi_getClkFreq(spi_t *obj); From e96c3a11fb51b1d1e32120555b8863d9febb316c Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 1 Sep 2025 14:22:39 +0200 Subject: [PATCH 09/18] fix(stm32wrapper): header regex Fixes #2809. Signed-off-by: Frederic Pillon --- CI/update/stm32wrapper.py | 2 +- .../{stm32yyxx_ll_timer.h => stm32yyxx_ll_radio_timer.h} | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) rename libraries/SrcWrapper/inc/LL/{stm32yyxx_ll_timer.h => stm32yyxx_ll_radio_timer.h} (65%) diff --git a/CI/update/stm32wrapper.py b/CI/update/stm32wrapper.py index 1abdba4c1c..7c85db0cb1 100644 --- a/CI/update/stm32wrapper.py +++ b/CI/update/stm32wrapper.py @@ -61,7 +61,7 @@ # re peripheral_c_regex = re.compile(r"stm32\w+_[h]?[al][l]_(.*).c$") -peripheral_h_regex = re.compile(r"stm32\w+_(\w+).h$") +peripheral_h_regex = re.compile(r"stm32\w+_[h]?[al][l]_(.*).h$") def checkConfig(arg_core, arg_cmsis): diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_timer.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_radio_timer.h similarity index 65% rename from libraries/SrcWrapper/inc/LL/stm32yyxx_ll_timer.h rename to libraries/SrcWrapper/inc/LL/stm32yyxx_ll_radio_timer.h index 9fbb78f288..b8875b6d2a 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_timer.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_radio_timer.h @@ -1,5 +1,5 @@ -#ifndef _STM32YYXX_LL_TIMER_H_ -#define _STM32YYXX_LL_TIMER_H_ +#ifndef _STM32YYXX_LL_RADIO_TIMER_H_ +#define _STM32YYXX_LL_RADIO_TIMER_H_ /* LL raised several warnings, ignore them */ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" @@ -9,7 +9,7 @@ #endif #ifdef STM32WB0x - #include "stm32wb0x_ll_timer.h" + #include "stm32wb0x_ll_radio_timer.h" #endif #pragma GCC diagnostic pop -#endif /* _STM32YYXX_LL_TIMER_H_ */ +#endif /* _STM32YYXX_LL_RADIO_TIMER_H_ */ From d35fec36d8cd33df2d13c22fb7d558c9773486ef Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bartu=20=C3=96zcan?= <104321219+baftii@users.noreply.github.com> Date: Mon, 8 Sep 2025 15:37:27 +0300 Subject: [PATCH 10/18] fix(uart): HardwareSerial begin() causes Infinite Loop (#2785) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * fix(uart): uart clock prescaler configuration Signed-off-by: Bartu Özcan Co-authored-by: Frederic Pillon --- libraries/SrcWrapper/inc/uart.h | 5 + libraries/SrcWrapper/src/stm32/uart.c | 150 ++++++++++++++++++++++++++ 2 files changed, 155 insertions(+) diff --git a/libraries/SrcWrapper/inc/uart.h b/libraries/SrcWrapper/inc/uart.h index 6c466ebe8c..c3a330820c 100644 --- a/libraries/SrcWrapper/inc/uart.h +++ b/libraries/SrcWrapper/inc/uart.h @@ -272,6 +272,11 @@ void uart_enable_rx(serial_t *obj); size_t uart_debug_write(uint8_t *data, uint32_t size); +#if defined(UART_PRESCALER_DIV1) +uint32_t uart_compute_prescaler(UART_HandleTypeDef *huart); +uint32_t uart_get_clock_source_freq(UART_HandleTypeDef *huart); +#endif + #endif /* HAL_UART_MODULE_ENABLED && !HAL_UART_MODULE_ONLY */ #ifdef __cplusplus } diff --git a/libraries/SrcWrapper/src/stm32/uart.c b/libraries/SrcWrapper/src/stm32/uart.c index db791c94f4..fa1789dd78 100644 --- a/libraries/SrcWrapper/src/stm32/uart.c +++ b/libraries/SrcWrapper/src/stm32/uart.c @@ -413,6 +413,18 @@ bool uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par huart->Init.Mode = UART_MODE_TX_RX; huart->Init.HwFlowCtl = flow_control; huart->Init.OverSampling = UART_OVERSAMPLING_16; + + /* Configure UART Clock Prescaler */ +#if defined(UART_PRESCALER_DIV1) + huart->Init.ClockPrescaler = uart_compute_prescaler(huart); + if (!IS_UART_PRESCALER(huart->Init.ClockPrescaler)) { + if (obj != &serial_debug) { + core_debug("WARNING: [U(S)ART] wrong prescaler, reset to UART_PRESCALER_DIV1!\n"); + } + huart->Init.ClockPrescaler = UART_PRESCALER_DIV1; + } +#endif + #if defined(UART_ADVFEATURE_NO_INIT) // Default value huart->AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; @@ -1415,6 +1427,144 @@ void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) serial_t *obj = get_serial_obj(huart); HAL_UART_Receive_IT(huart, &(obj->recv), 1); } + +/** + * @brief Function called to set the uart clock prescaler + * @param huart : uart handle structure + * @retval uint32_t clock prescaler + */ +#if defined(UART_PRESCALER_DIV1) +uint32_t uart_compute_prescaler(UART_HandleTypeDef *huart) +{ + uint32_t prescaler = UART_PRESCALER_DIV1; + static const uint16_t presc_div[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; + uint32_t freq = uart_get_clock_source_freq(huart); + uint32_t usartdiv = 0; + +#if defined(UART_INSTANCE_LOWPOWER) + if (UART_INSTANCE_LOWPOWER(huart)) { + for (uint32_t idx = 0; idx < 12; idx++) { + /* Check computed UsartDiv value is in allocated range + (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ + usartdiv = (uint32_t)(UART_DIV_LPUART(freq, huart->Init.BaudRate, presc_div[idx])); + if ((usartdiv >= 0x00000300U) && (usartdiv <= 0x000FFFFFU)) { + prescaler = UART_PRESCALER_DIV1 + idx; + break; + } + } + } else +#endif /* UART_INSTANCE_LOWPOWER */ + { + for (uint32_t idx = 0; idx < 12; idx++) { + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) { + usartdiv = (uint32_t)(UART_DIV_SAMPLING8(freq, huart->Init.BaudRate, presc_div[idx])); + } else { + usartdiv = (uint32_t)(UART_DIV_SAMPLING16(freq, huart->Init.BaudRate, presc_div[idx])); + } + if ((usartdiv >= 0x10U) && (usartdiv <= 0x0000FFFFU)) { + prescaler = UART_PRESCALER_DIV1 + idx; + break; + } + } + } + return prescaler; +} + +/** + * @brief Function called to get the clock source frequency of the uart + * @param huart : uart handle structure + * @retval uint32_t clock source frequency + */ +uint32_t uart_get_clock_source_freq(UART_HandleTypeDef *huart) +{ + uint32_t freq = 0; +#if defined(STM32WB0) + freq = UART_PERIPHCLK; + if (UART_INSTANCE_LOWPOWER(huart)) { +#if defined(RCC_CFGR_LPUCLKSEL) + freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_LPUART1); +#endif /* RCC_CFGR_LPUCLKSEL */ + } +#else /* !STM32WB0 */ + uint32_t clocksource; + UART_GETCLOCKSOURCE(huart, clocksource); +#if defined(STM32H5) || defined(STM32MP1) || defined(STM32U0) ||\ + defined(STM32U3) || defined(STM32U5) + freq = HAL_RCCEx_GetPeriphCLKFreq(clocksource); +#else + switch (clocksource) { +#if defined(UART_CLOCKSOURCE_D2PCLK1) || defined(UART_CLOCKSOURCE_PCLK1) +#if defined(UART_CLOCKSOURCE_D2PCLK1) + case UART_CLOCKSOURCE_D2PCLK1: +#endif /* UART_CLOCKSOURCE_D2PCLK1*/ +#if defined(UART_CLOCKSOURCE_PCLK1) + case UART_CLOCKSOURCE_PCLK1: +#endif /* UART_CLOCKSOURCE_PCLK1 */ + freq = HAL_RCC_GetPCLK1Freq(); + break; +#endif /* UART_CLOCKSOURCE_D2PCLK1 || UART_CLOCKSOURCE_PCLK1*/ +#if defined(UART_CLOCKSOURCE_D2PCLK2) || defined(UART_CLOCKSOURCE_PCLK2) +#if defined(UART_CLOCKSOURCE_D2PCLK2) + case UART_CLOCKSOURCE_D2PCLK2: +#endif /* UART_CLOCKSOURCE_D2PCLK2*/ +#if defined(UART_CLOCKSOURCE_PCLK2) + case UART_CLOCKSOURCE_PCLK2: +#endif /* UART_CLOCKSOURCE_PCLK2 */ + freq = HAL_RCC_GetPCLK2Freq(); + break; +#endif /* UART_CLOCKSOURCE_D2PCLK2 || UART_CLOCKSOURCE_PCLK2*/ +#if defined(UART_CLOCKSOURCE_PCLK7) + case UART_CLOCKSOURCE_PCLK7: + freq = HAL_RCC_GetPCLK7Freq(); + break; +#endif /* UART_CLOCKSOURCE_PCLK7 */ +#if defined(UART_CLOCKSOURCE_PLL2) + case UART_CLOCKSOURCE_PLL2: + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + freq = pll2_clocks.PLL2_Q_Frequency; + break; + case UART_CLOCKSOURCE_PLL3: + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + freq = pll3_clocks.PLL3_Q_Frequency; + break; +#endif /* UART_CLOCKSOURCE_PLL2 */ + case UART_CLOCKSOURCE_HSI: +#if defined(__HAL_RCC_GET_HSIKER_DIVIDER) + freq = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U)); +#else +#if defined(RCC_FLAG_HSIDIV) + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) { + freq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); + } else +#endif /* RCC_FLAG_HSIDIV */ + { + freq = (uint32_t) HSI_VALUE; + } +#endif + break; +#if defined(UART_CLOCKSOURCE_CSI) + case UART_CLOCKSOURCE_CSI: + freq = (uint32_t) CSI_VALUE; + break; +#endif /* UART_CLOCKSOURCE_CSI */ +#if defined(UART_CLOCKSOURCE_SYSCLK) + case UART_CLOCKSOURCE_SYSCLK: + freq = HAL_RCC_GetSysClockFreq(); + break; +#endif /* UART_CLOCKSOURCE_SYSCLK */ + case UART_CLOCKSOURCE_LSE: + freq = (uint32_t) LSE_VALUE; + break; + default: + freq = 0U; + break; + } +#endif /* STM32H5 */ +#endif /* STM32WB0 */ + return freq; +} +#endif /* UART_PRESCALER_DIV1 */ + #endif /* HAL_UART_MODULE_ENABLED && !HAL_UART_MODULE_ONLY */ #ifdef __cplusplus From 93d997316cdecb1226af60c5eb6c0f39de1ffa3e Mon Sep 17 00:00:00 2001 From: John Gietzen Date: Fri, 29 Aug 2025 08:27:34 -0700 Subject: [PATCH 11/18] variant(f4): add the STM32F411E-DISCO board Signed-off-by: John Gietzen --- README.md | 2 + boards.txt | 32 +++ variants/STM32F4xx/F411V(C-E)T/CMakeLists.txt | 1 + .../STM32F4xx/F411V(C-E)T/generic_clock.c | 38 ++- variants/STM32F4xx/F411V(C-E)T/ldscript.ld | 188 ++++++++++++++ .../F411V(C-E)T/variant_DISCO_F411VE.cpp | 191 ++++++++++++++ .../F411V(C-E)T/variant_DISCO_F411VE.h | 237 ++++++++++++++++++ 7 files changed, 687 insertions(+), 2 deletions(-) create mode 100644 variants/STM32F4xx/F411V(C-E)T/ldscript.ld create mode 100644 variants/STM32F4xx/F411V(C-E)T/variant_DISCO_F411VE.cpp create mode 100644 variants/STM32F4xx/F411V(C-E)T/variant_DISCO_F411VE.h diff --git a/README.md b/README.md index 07cd09856a..f92b320621 100644 --- a/README.md +++ b/README.md @@ -191,6 +191,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32F100RB | [STM32VLDISCOVERY](https://www.st.com/en/evaluation-tools/stm32vldiscovery.html) | 0.2.1 | | | :green_heart: | STM32F303VC | [STM32F3DISCOVERY](https://www.st.com/en/evaluation-tools/stm32f3discovery.html) | *2.0.0* | | | :green_heart: | STM32F407VG | [STM32F407G-DISC1](http://www.st.com/en/evaluation-tools/stm32f4discovery.html) | *0.1.0* | | +| :yellow_heart: | STM32F411VE | [STM32F411E-DISCO](https://www.st.com/en/evaluation-tools/32f411ediscovery.html) | **2.12.0** | | | :green_heart: | STM32F413ZH | [32F413HDISCOVERY](https://www.st.com/en/evaluation-tools/32f413hdiscovery.html) | *1.9.0* | | | :green_heart: | STM32F746NG | [STM32F746G-DISCOVERY](http://www.st.com/en/evaluation-tools/32f746gdiscovery.html) | *0.1.0* | | | :green_heart: | STM32G031J6 | [STM32G0316-DISCO](https://www.st.com/en/evaluation-tools/stm32g0316-disco.html) | *1.9.0* | | @@ -389,6 +390,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32F410T8
                                                                                          STM32F410TB | Generic Board | *2.4.0* | | | :green_heart: | STM32F411CC
                                                                                          STM32F411CE | Generic Board | *1.9.0* | | | :green_heart: | STM32F411RC
                                                                                          STM32F411RE | Generic Board | *1.9.0* | | +| :yellow_heart: | STM32F411VC
                                                                                          STM32F411VE | Generic Board | **2.12.0** | | | :green_heart: | STM32F412CE
                                                                                          STM32F412CG | Generic Board | *1.9.0* | | | :green_heart: | STM32F412RE
                                                                                          STM32F412RG | Generic Board | *1.9.0* | | | :green_heart: | STM32F412ZE
                                                                                          STM32F412ZG | Generic Board | *2.6.0* | | diff --git a/boards.txt b/boards.txt index 70e6ab6f95..742e45f479 100644 --- a/boards.txt +++ b/boards.txt @@ -1421,6 +1421,20 @@ Disco.menu.pnum.DISCO_F407VG.build.variant=STM32F4xx/F407V(E-G)T_F417V(E-G)T Disco.menu.pnum.DISCO_F407VG.openocd.target=stm32f4x Disco.menu.pnum.DISCO_F407VG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F407.svd +# DISCO_F411VE board +Disco.menu.pnum.DISCO_F411VE=STM32F411E-DISCO +Disco.menu.pnum.DISCO_F411VE.upload.maximum_size=524288 +Disco.menu.pnum.DISCO_F411VE.upload.maximum_data_size=131072 +Disco.menu.pnum.DISCO_F411VE.build.mcu=cortex-m4 +Disco.menu.pnum.DISCO_F411VE.build.fpu=-mfpu=fpv4-sp-d16 +Disco.menu.pnum.DISCO_F411VE.build.float-abi=-mfloat-abi=hard +Disco.menu.pnum.DISCO_F411VE.build.board=DISCO_F411VE +Disco.menu.pnum.DISCO_F411VE.build.series=STM32F4xx +Disco.menu.pnum.DISCO_F411VE.build.product_line=STM32F411xE +Disco.menu.pnum.DISCO_F411VE.build.variant=STM32F4xx/F411V(C-E)T +Disco.menu.pnum.DISCO_F411VE.openocd.target=stm32f4x +Disco.menu.pnum.DISCO_F411VE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F411.svd + # DISCO_F413ZH board Disco.menu.pnum.DISCO_F413ZH=STM32F413H-DISCO Disco.menu.pnum.DISCO_F413ZH.node=DIS_F413ZH @@ -5258,6 +5272,24 @@ GenF4.menu.pnum.GENERIC_F411RETX.build.product_line=STM32F411xE GenF4.menu.pnum.GENERIC_F411RETX.build.variant=STM32F4xx/F411R(C-E)T GenF4.menu.pnum.GENERIC_F411RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F411.svd +# Generic F411VCTx +GenF4.menu.pnum.GENERIC_F411VCTX=Generic F411VCTx +GenF4.menu.pnum.GENERIC_F411VCTX.upload.maximum_size=262144 +GenF4.menu.pnum.GENERIC_F411VCTX.upload.maximum_data_size=131072 +GenF4.menu.pnum.GENERIC_F411VCTX.build.board=GENERIC_F411VCTX +GenF4.menu.pnum.GENERIC_F411VCTX.build.product_line=STM32F411xE +GenF4.menu.pnum.GENERIC_F411VCTX.build.variant=STM32F4xx/F411V(C-E)T +GenF4.menu.pnum.GENERIC_F411VCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F411.svd + +# Generic F411VETx +GenF4.menu.pnum.GENERIC_F411VETX=Generic F411VETx +GenF4.menu.pnum.GENERIC_F411VETX.upload.maximum_size=524288 +GenF4.menu.pnum.GENERIC_F411VETX.upload.maximum_data_size=131072 +GenF4.menu.pnum.GENERIC_F411VETX.build.board=GENERIC_F411VETX +GenF4.menu.pnum.GENERIC_F411VETX.build.product_line=STM32F411xE +GenF4.menu.pnum.GENERIC_F411VETX.build.variant=STM32F4xx/F411V(C-E)T +GenF4.menu.pnum.GENERIC_F411VETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F411.svd + # Generic F412CEUx GenF4.menu.pnum.GENERIC_F412CEUX=Generic F412CEUx GenF4.menu.pnum.GENERIC_F412CEUX.upload.maximum_size=524288 diff --git a/variants/STM32F4xx/F411V(C-E)T/CMakeLists.txt b/variants/STM32F4xx/F411V(C-E)T/CMakeLists.txt index 2a4d55b6b1..1aecc9cfb3 100644 --- a/variants/STM32F4xx/F411V(C-E)T/CMakeLists.txt +++ b/variants/STM32F4xx/F411V(C-E)T/CMakeLists.txt @@ -22,6 +22,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL generic_clock.c PeripheralPins.c variant_generic.cpp + variant_DISCO_F411VE.cpp ) target_link_libraries(variant_bin PUBLIC variant_usage) diff --git a/variants/STM32F4xx/F411V(C-E)T/generic_clock.c b/variants/STM32F4xx/F411V(C-E)T/generic_clock.c index bf8bb0b6cf..16eb085be5 100644 --- a/variants/STM32F4xx/F411V(C-E)T/generic_clock.c +++ b/variants/STM32F4xx/F411V(C-E)T/generic_clock.c @@ -20,8 +20,42 @@ */ WEAK void SystemClock_Config(void) { - /* SystemClock_Config can be generated by STM32CubeMX */ -#warning "SystemClock_Config() is empty. Default clock at reset is used." + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 16; + RCC_OscInitStruct.PLL.PLLN = 192; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 4; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + Error_Handler(); + } } #endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32F4xx/F411V(C-E)T/ldscript.ld b/variants/STM32F4xx/F411V(C-E)T/ldscript.ld new file mode 100644 index 0000000000..3f1681174f --- /dev/null +++ b/variants/STM32F4xx/F411V(C-E)T/ldscript.ld @@ -0,0 +1,188 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32F411VETx Device from STM32F4 series +** 512KBytes FLASH +** 128KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2025 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE + FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET +} + +/* Sections */ +SECTIONS +{ + + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/variants/STM32F4xx/F411V(C-E)T/variant_DISCO_F411VE.cpp b/variants/STM32F4xx/F411V(C-E)T/variant_DISCO_F411VE.cpp new file mode 100644 index 0000000000..55de45797d --- /dev/null +++ b/variants/STM32F4xx/F411V(C-E)T/variant_DISCO_F411VE.cpp @@ -0,0 +1,191 @@ +/* + ******************************************************************************* + * Copyright (c) 2011-2021, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_DISCO_F411VE) + +#include "pins_arduino.h" + +// Pin number +const PinName digitalPin[] = { + //P1 connector Right side + PC_0, //D0/A10 + PC_2, //D1/A12 + PA_0, //D2/A0 + PA_2, //D3/A2 + PA_4, //D4/A4 + PA_6, //D5/A6 + PC_4, //D6/A14 + PB_0, //D7/A8 + PB_2, //D8 + PE_8, //D9 + PE_10, //D10 + PE_12, //D11 + PE_14, //D12 + PB_10, //D13 + PB_12, //D14 + PB_14, //D15 + PD_8, //D16 + PD_10, //D17 + PD_12, //D18 + PD_14, //D19 + //P2 connector Left side + PH_0, //D20 + PC_14, //D21 + PE_6, //D22 + PE_4, //D23 + PE_2, //D24 + PE_0, //D25 + PB_8, //D26 + PB_6, //D27 + PB_4, //D28 + PD_7, //D29 + PD_5, //D30 + PD_3, //D31 + PD_1, //D32 + PC_12, //D33 + PC_10, //D34 + PA_14, //D35 + PA_10, //D36 + PA_8, //D37 + PC_8, //D38 + PC_6, //D39 + //P1 Connector Left Side + PC_1, //D40/A11 + PC_3, //D41/A13 + PA_1, //D42/A1 + PA_3, //D43/A3 + PA_5, //D44/A5 + PA_7, //D45/A7 + PC_5, //D46/A15 + PB_1, //D47/A9 + PE_7, //D48 + PE_9, //D49 + PE_11, //D50 + PE_13, //D51 + PE_15, //D52 + PB_13, //D53 + PB_15, //D54 + PD_9, //D55 + PD_11, //D56 + PD_13, //D57 + PD_15, //D58 + //P2 connector Right side + PH_1, //D59 + PC_15, //D60 + PC_13, //D61 + PE_5, //D62 + PE_3, //D63 + PE_1, //D64 + PB_9, //D65 + PB_7, //D66 + PB_5, //D67 + PB_3, //D68 + PD_6, //D69 + PD_4, //D70 + PD_2, //D71 + PD_0, //D72 + PC_11, //D73 + PA_15, //D74 + PA_13, //D75 + PA_9, //D76 + PC_9, //D77 + PC_7, //D78 + //CN5 USB USER connector + PA_11, //D79 + PA_12 //D80 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 2, //A0 + 42, //A1 + 3, //A2 + 43, //A3 + 4, //A4 + 44, //A5 + 5, //A6 + 45, //A7 + 7, //A8 + 47, //A9 + 0, //A10 + 40, //A11 + 1, //A12 + 41, //A13 + 6, //A14 + 46 //A15 +}; + +// ---------------------------------------------------------------------------- + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief System Clock Configuration + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 4; + RCC_OscInitStruct.PLL.PLLN = 192; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; + RCC_OscInitStruct.PLL.PLLQ = 4; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S; + PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; + PeriphClkInitStruct.PLLI2S.PLLI2SM = 4; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } +} + +#ifdef __cplusplus +} +#endif + +#endif /* ARDUINO_DISCO_F411VE */ diff --git a/variants/STM32F4xx/F411V(C-E)T/variant_DISCO_F411VE.h b/variants/STM32F4xx/F411V(C-E)T/variant_DISCO_F411VE.h new file mode 100644 index 0000000000..b2ca6f65b2 --- /dev/null +++ b/variants/STM32F4xx/F411V(C-E)T/variant_DISCO_F411VE.h @@ -0,0 +1,237 @@ +/* + ******************************************************************************* + * Copyright (c) 2025, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ + +//P1 connector Right side +#define PC0 PIN_A10 +#define PC2 PIN_A12 +#define PA0 PIN_A0 +#define PA2 PIN_A2 +#define PA4 PIN_A4 +#define PA6 PIN_A6 +#define PC4 PIN_A14 +#define PB0 PIN_A8 +#define PB2 8 +#define PE8 9 +#define PE10 10 +#define PE12 11 +#define PE14 12 +#define PB10 13 +#define PB12 14 +#define PB14 15 +#define PD8 16 +#define PD10 17 +#define PD12 18 +#define PD14 19 +//P2 connector Left side +#define PH0 20 +#define PC14 21 +#define PE6 22 +#define PE4 23 +#define PE2 24 +#define PE0 25 +#define PB8 26 +#define PB6 27 +#define PB4 28 +#define PD7 29 +#define PD5 30 +#define PD3 31 +#define PD1 32 +#define PC12 33 +#define PC10 34 +#define PA14 35 +#define PA10 36 +#define PA8 37 +#define PC8 38 +#define PC6 39 +//P1 Connector Left Side +#define PC1 PIN_A11 +#define PC3 PIN_A13 +#define PA1 PIN_A1 +#define PA3 PIN_A3 +#define PA5 PIN_A5 +#define PA7 PIN_A7 +#define PC5 PIN_A15 +#define PB1 PIN_A9 +#define PE7 48 +#define PE9 49 +#define PE11 50 +#define PE13 51 +#define PE15 52 +#define PB13 53 +#define PB15 54 +#define PD9 55 +#define PD11 56 +#define PD13 57 +#define PD15 58 +//P2 connector Right side +#define PH1 59 +#define PC15 60 +#define PC13 61 +#define PE5 62 +#define PE3 63 +#define PE1 64 +#define PB9 65 +#define PB7 66 +#define PB5 67 +#define PB3 68 +#define PD6 69 +#define PD4 70 +#define PD2 71 +#define PD0 72 +#define PC11 73 +#define PA15 74 +#define PA13 75 +#define PA9 76 +#define PC9 77 +#define PC7 78 +//CN5 USB USER connector +#define PA11 79 +#define PA12 80 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB12_ALT1 (PB12 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PE2_ALT1 (PE2 | ALT1) +#define PE4_ALT1 (PE4 | ALT1) +#define PE5_ALT1 (PE5 | ALT1) +#define PE6_ALT1 (PE6 | ALT1) +#define PE11_ALT1 (PE11 | ALT1) +#define PE12_ALT1 (PE12 | ALT1) +#define PE13_ALT1 (PE13 | ALT1) +#define PE14_ALT1 (PE14 | ALT1) + +#define NUM_DIGITAL_PINS 81 +#define NUM_ANALOG_INPUTS 16 + +// On-board LED pin number +#define LED_GREEN PD12 +#define LED_BLUE PD15 +#define LED_RED PD14 +#define LED_ORANGE PD13 +#ifndef LED_BUILTIN + #define LED_BUILTIN LED_GREEN +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PA0 +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PE3 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB9 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB6 +#endif + +// Timer Definitions +#ifndef TIMER_TONE + #define TIMER_TONE TIM10 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM11 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 2 //Connected to ST-Link +#endif + +// Default pin used for 'Serial' instance (ex: ST-Link) +// Mandatory for Firmata +// By default not connected to ST-Link as +// SB10 and SB11 not fitted on the board. +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA3 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA2 +#endif + +// Extra HAL modules +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif From b7e543b5d0bbbd8a3dcce31af12a2ab4dbf554e4 Mon Sep 17 00:00:00 2001 From: qqqlab <46283638+qqqlab@users.noreply.github.com> Date: Mon, 15 Sep 2025 03:22:44 +0200 Subject: [PATCH 12/18] Add readBytes(uint8_t *buffer, size_t length) to USBSerial.h Signed-off-by: qqqlab <46283638+qqqlab@users.noreply.github.com> --- libraries/USBDevice/inc/USBSerial.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/libraries/USBDevice/inc/USBSerial.h b/libraries/USBDevice/inc/USBSerial.h index 202c059daa..89b50cebcc 100644 --- a/libraries/USBDevice/inc/USBSerial.h +++ b/libraries/USBDevice/inc/USBSerial.h @@ -37,7 +37,15 @@ class USBSerial : public Stream { virtual int peek(void); virtual int read(void); virtual size_t readBytes(char *buffer, size_t length); // read chars from stream into buffer + size_t readBytes(uint8_t *buffer, size_t length) + { + return readBytes((char *)buffer, length); + } virtual size_t readBytesUntil(char terminator, char *buffer, size_t length); // as readBytes with terminator character + size_t readBytesUntil(char terminator, uint8_t *buffer, size_t length) + { + return readBytesUntil(terminator, (char *)buffer, length); + } virtual void flush(void); virtual size_t write(uint8_t); virtual size_t write(const uint8_t *buffer, size_t size); From 3d52b32cc047750a0a25f969b1c0693323e81ca8 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 15 Sep 2025 15:50:22 +0200 Subject: [PATCH 13/18] fix: add guard to custom startup scripts Fixes #2819. Signed-off-by: Frederic Pillon --- variants/STM32F0xx/F070CBT/startup_Mx00_f070xb.S | 2 ++ variants/STM32F1xx/F103C8T_F103CB(T-U)/startup_M200_f103xb.S | 3 +++ 2 files changed, 5 insertions(+) diff --git a/variants/STM32F0xx/F070CBT/startup_Mx00_f070xb.S b/variants/STM32F0xx/F070CBT/startup_Mx00_f070xb.S index 9e4416672d..d42b22a4eb 100644 --- a/variants/STM32F0xx/F070CBT/startup_Mx00_f070xb.S +++ b/variants/STM32F0xx/F070CBT/startup_Mx00_f070xb.S @@ -1,3 +1,4 @@ +#if defined(ARDUINO_MALYANM200_F070CB) || defined(ARDUINO_MALYANM300_F070CB) /** ****************************************************************************** * @file startup_stm32f070xb.s @@ -300,3 +301,4 @@ g_pfnVectors: .thumb_set USB_IRQHandler,Default_Handler /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* ARDUINO_MALYANM200_F070CB || ARDUINO_MALYANM300_F070CB */ diff --git a/variants/STM32F1xx/F103C8T_F103CB(T-U)/startup_M200_f103xb.S b/variants/STM32F1xx/F103C8T_F103CB(T-U)/startup_M200_f103xb.S index eb2f379e3b..19ba3f0799 100644 --- a/variants/STM32F1xx/F103C8T_F103CB(T-U)/startup_M200_f103xb.S +++ b/variants/STM32F1xx/F103C8T_F103CB(T-U)/startup_M200_f103xb.S @@ -1,3 +1,4 @@ +#if defined(ARDUINO_MALYANM200_F103CB) /** *************** (C) COPYRIGHT 2017 STMicroelectronics ************************ * @file startup_stm32f103xb.s @@ -389,3 +390,5 @@ g_pfnVectors: .thumb_set USBWakeUp_IRQHandler,Default_Handler /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + +#endif /* ARDUINO_MALYANM200_F103CB */ From d01d9ab8b4ede404bc77c5d9b2b3683f7e129c28 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 22 Sep 2025 14:24:02 +0200 Subject: [PATCH 14/18] system(u0) update STM32U0xx HAL Drivers to v1.3.0 Included in STM32CubeU0 FW 1.3.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 23 +- .../STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal.h | 21 +- .../Inc/stm32u0xx_hal_comp.h | 3 +- .../Inc/stm32u0xx_hal_cryp.h | 2 +- .../Inc/stm32u0xx_hal_flash.h | 15 +- .../Inc/stm32u0xx_hal_pwr_ex.h | 4 +- .../Inc/stm32u0xx_hal_rcc.h | 18 +- .../Inc/stm32u0xx_hal_rtc.h | 22 +- .../Inc/stm32u0xx_hal_rtc_ex.h | 66 +-- .../Inc/stm32u0xx_hal_smartcard.h | 6 +- .../Inc/stm32u0xx_hal_spi.h | 46 +- .../Inc/stm32u0xx_hal_uart.h | 8 +- .../Inc/stm32u0xx_hal_usart.h | 12 +- .../Inc/stm32u0xx_ll_adc.h | 8 +- .../Inc/stm32u0xx_ll_comp.h | 2 + .../Inc/stm32u0xx_ll_lptim.h | 25 +- .../Inc/stm32u0xx_ll_lpuart.h | 4 + .../Inc/stm32u0xx_ll_spi.h | 119 +++-- .../Inc/stm32u0xx_ll_usart.h | 4 + .../STM32U0xx_HAL_Driver/Release_Notes.html | 82 +++- .../STM32U0xx_HAL_Driver/Src/stm32u0xx_hal.c | 41 +- .../Src/stm32u0xx_hal_adc_ex.c | 6 +- .../Src/stm32u0xx_hal_crc.c | 8 +- .../Src/stm32u0xx_hal_cryp.c | 40 +- .../Src/stm32u0xx_hal_flash_ex.c | 2 +- .../Src/stm32u0xx_hal_rtc_ex.c | 2 +- .../Src/stm32u0xx_hal_spi.c | 452 +++++++++--------- .../Src/stm32u0xx_hal_timebase_tim_template.c | 22 +- .../Src/stm32u0xx_hal_uart.c | 129 +++-- .../Src/stm32u0xx_hal_uart_ex.c | 52 +- .../Src/stm32u0xx_ll_comp.c | 1 + .../Src/stm32u0xx_ll_spi.c | 7 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 33 files changed, 698 insertions(+), 556 deletions(-) diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index afaa855825..fdda5903e3 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -538,6 +538,10 @@ extern "C" { #define FLASH_FLAG_WDW FLASH_FLAG_WBNE #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ +#if defined(STM32H7RS) +#define FLASH_OPTKEY1 FLASH_OPT_KEY1 +#define FLASH_OPTKEY2 FLASH_OPT_KEY2 +#endif /* STM32H7RS */ #if defined(STM32U5) #define OB_USER_nRST_STOP OB_USER_NRST_STOP #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY @@ -560,6 +564,9 @@ extern "C" { #define OB_nBOOT0_RESET OB_NBOOT0_RESET #define OB_nBOOT0_SET OB_NBOOT0_SET #endif /* STM32U0 */ +#if defined(STM32H5) +#define FLASH_ECC_AREA_EDATA FLASH_ECC_AREA_EDATA_BANK1 +#endif /* STM32H5 */ /** * @} @@ -1299,22 +1306,22 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL #endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ -#if defined(STM32F7) +#if defined(STM32F7) || defined(STM32WB) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK -#endif /* STM32F7 */ +#endif /* STM32F7 || STM32WB */ #if defined(STM32H7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT #endif /* STM32H7 */ -#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP -#endif /* STM32F7 || STM32H7 || STM32L0 */ +#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */ /** * @} @@ -1481,7 +1488,7 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif -#if defined(STM32U5) +#if defined(STM32U5) || defined(STM32MP2) #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK #endif @@ -3695,7 +3702,7 @@ extern "C" { #endif #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3946,8 +3953,8 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32V7) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \ - defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || \ + defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal.h index d5f485d9b2..fb1e945313 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal.h @@ -45,10 +45,13 @@ extern "C" { /** @defgroup HAL_TICK_FREQ Tick Frequency * @{ */ -#define HAL_TICK_FREQ_10HZ 100U -#define HAL_TICK_FREQ_100HZ 10U -#define HAL_TICK_FREQ_1KHZ 1U -#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; /** * @} @@ -687,8 +690,8 @@ void HAL_IncTick(void); void HAL_Delay(uint32_t Delay); uint32_t HAL_GetTick(void); uint32_t HAL_GetTickPrio(void); -HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq); -uint32_t HAL_GetTickFreq(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); void HAL_SuspendTick(void); void HAL_ResumeTick(void); uint32_t HAL_GetHalVersion(void); @@ -720,9 +723,9 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void); /** @addtogroup HAL_Exported_Variables * @{ */ -extern __IO uint32_t uwTick; -extern uint32_t uwTickPrio; -extern uint32_t uwTickFreq; +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; /** * @} */ diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_comp.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_comp.h index 7165c86f5f..af7cab5534 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_comp.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_comp.h @@ -686,7 +686,8 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer ((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_BOTH) ) #define IS_COMP_POWERMODE(__POWERMODE__) (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED) || \ - ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) ) + ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) || \ + ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER) ) #define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__COMP_INSTANCE__) == COMP1) \ ? (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \ diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_cryp.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_cryp.h index 70ee4a5ffe..2b43d0af7e 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_cryp.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_cryp.h @@ -177,7 +177,7 @@ typedef struct uint32_t IV_saved[4]; /*!< copy of Initialisation Vector registers */ - uint32_t SUSPxR_saved[8]; /*!< copy of suspension registers */ + uint32_t SUSPRx_saved[8]; /*!< copy of suspension registers */ uint32_t CR_saved; /*!< copy of CRYP control register when processing is suspended*/ diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_flash.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_flash.h index 7584c137eb..27d5605b7c 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_flash.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_flash.h @@ -292,7 +292,7 @@ typedef struct * @{ */ #define OB_USER_BOR_EN FLASH_OPTR_BOR_EN /*!< BOR reset enable */ -#define OB_USER_BOR_LEV (FLASH_OPTR_BORF_LEV | FLASH_OPTR_BORR_LEV) /*!< BOR reset Level */ +#define OB_USER_BOR_LEV FLASH_OPTR_BOR_LEV /*!< BOR reset Level */ #define OB_USER_NRST_STOP FLASH_OPTR_nRST_STOP /*!< Reset generated when entering the stop mode */ #define OB_USER_NRST_STDBY FLASH_OPTR_nRST_STDBY /*!< Reset generated when entering the standby mode */ #define OB_USER_NRST_SHDW FLASH_OPTR_nRST_SHDW /*!< Reset generated when entering the shutdown mode */ @@ -328,14 +328,11 @@ typedef struct /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level * @{ */ -#define OB_BOR_LEVEL_FALLING_0 0x00000000U /*!< BOR falling level 1 with threshold around 2.0V */ -#define OB_BOR_LEVEL_FALLING_1 FLASH_OPTR_BORF_LEV_0 /*!< BOR falling level 2 with threshold around 2.2V */ -#define OB_BOR_LEVEL_FALLING_2 FLASH_OPTR_BORF_LEV_1 /*!< BOR falling level 3 with threshold around 2.5V */ -#define OB_BOR_LEVEL_FALLING_3 (FLASH_OPTR_BORF_LEV_0 | FLASH_OPTR_BORF_LEV_1) /*!< BOR falling level 4 with threshold around 2.8V */ -#define OB_BOR_LEVEL_RISING_0 0x00000000U /*!< BOR rising level 1 with threshold around 2.1V */ -#define OB_BOR_LEVEL_RISING_1 FLASH_OPTR_BORR_LEV_0 /*!< BOR rising level 2 with threshold around 2.3V */ -#define OB_BOR_LEVEL_RISING_2 FLASH_OPTR_BORR_LEV_1 /*!< BOR rising level 3 with threshold around 2.6V */ -#define OB_BOR_LEVEL_RISING_3 (FLASH_OPTR_BORR_LEV_0 | FLASH_OPTR_BORR_LEV_1) /*!< BOR rising level 4 with threshold around 2.9V */ +#define OB_BOR_LEVEL_0 0x00000000U /*!< BOR level 0 with threshold around 2.0V */ +#define OB_BOR_LEVEL_1 FLASH_OPTR_BOR_LEV_0 /*!< BOR level 1 with threshold around 2.2V */ +#define OB_BOR_LEVEL_2 FLASH_OPTR_BOR_LEV_1 /*!< BOR level 2 with threshold around 2.5V */ +#define OB_BOR_LEVEL_3 (FLASH_OPTR_BOR_LEV_0 | FLASH_OPTR_BOR_LEV_1) /*!< BOR level 3 with threshold around 2.8V */ + /** * @} */ diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_pwr_ex.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_pwr_ex.h index e20437f526..01a16d831c 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_pwr_ex.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_pwr_ex.h @@ -225,7 +225,7 @@ typedef struct */ /** @defgroup PWREx_Flag PWR Status Flags - * Elements values convention: 0000 0000 0XXY YYYYb + * Elements values convention: 0000 00XX 000Y YYYYb * - Y YYYY : Flag position in the XX register (5 bits) * - XX : Status register (2 bits) * - 01: SR1 register @@ -254,7 +254,7 @@ typedef struct #define PWR_FLAG_PVMO_USB 0x020CU /*!< Power Voltage Monitoring 1 output flag */ #define PWR_FLAG_PVMO_ADC 0x020EU /*!< Power Voltage Monitoring 3 output flag */ #define PWR_FLAG_PVMO_DAC 0x020FU /*!< Power Voltage Monitoring 4 output flag */ -#define PWR_SCR_CWUF 0x002FU /*!< Clear Wake-up Flags */ +#define PWR_SCR_CWUF 0x005FU /*!< Clear Wake-up Flags */ /** * @} */ diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_rcc.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_rcc.h index 7a76870a8e..204afb6acb 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_rcc.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_rcc.h @@ -478,33 +478,33 @@ typedef struct | Index | AF | Port | Pin | -------------------------------*/ -#define RCC_MCO_GPIOPORT_POS 16U +#define RCC_MCO_GPIOPORT_POS 16UL #define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS) -#define RCC_MCO_GPIOAF_POS 20U +#define RCC_MCO_GPIOAF_POS 20UL #define RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS) -#define RCC_MCO_INDEX_POS 28U +#define RCC_MCO_INDEX_POS 28UL #define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS) #define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */ #define RCC_MCO1_PA8 (RCC_MCO1_INDEX |\ - (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \ + (RCC_MCO_GPIOAF_MASK & ((uint32_t)GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS)) | \ (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) #define RCC_MCO1_PA9 (RCC_MCO1_INDEX |\ - (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \ + (RCC_MCO_GPIOAF_MASK & ((uint32_t)GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS)) | \ (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_9) #define RCC_MCO1_PF2 (RCC_MCO1_INDEX |\ - (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \ + (RCC_MCO_GPIOAF_MASK & ((uint32_t)GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS)) | \ (GPIO_GET_INDEX(GPIOF) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_2) #define RCC_MCO1 RCC_MCO1_PA8 #define RCC_MCO2_INDEX (0x1UL << RCC_MCO_INDEX_POS) /*!< MCO2 index */ #define RCC_MCO2_PC2 (RCC_MCO2_INDEX |\ - (GPIO_AF0_MCO2 << RCC_MCO_GPIOAF_POS) | \ + (RCC_MCO_GPIOAF_MASK & ((uint32_t)GPIO_AF0_MCO2 << RCC_MCO_GPIOAF_POS)) | \ (GPIO_GET_INDEX(GPIOC) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_2) #define RCC_MCO2_PA10 (RCC_MCO2_INDEX |\ - (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | \ + (RCC_MCO_GPIOAF_MASK & ((uint32_t)GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS)) | \ (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10) #define RCC_MCO2_PA8 (RCC_MCO2_INDEX |\ - (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | \ + (RCC_MCO_GPIOAF_MASK & ((uint32_t)GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS)) | \ (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) #define RCC_MCO2 RCC_MCO2_PC2 diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_rtc.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_rtc.h index f573827d1e..b90f9791a6 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_rtc.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_rtc.h @@ -590,6 +590,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to */ #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ do{ \ + UNUSED(__HANDLE__); \ RTC->WPR = 0xCAU; \ RTC->WPR = 0x53U; \ } while(0U) @@ -601,6 +602,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to */ #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ do{ \ + UNUSED(__HANDLE__); \ RTC->WPR = 0xFFU; \ } while(0U) @@ -643,28 +645,28 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_ALRAE)) +#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_ALRAE))) /** * @brief Disable the RTC ALARMA peripheral. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_ALRAE)) +#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_ALRAE))) /** * @brief Enable the RTC ALARMB peripheral. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_ALRBE)) +#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_ALRBE))) /** * @brief Disable the RTC ALARMB peripheral. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_ALRBE)) +#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_ALRBE))) /** * @brief Enable the RTC Alarm interrupt. @@ -675,7 +677,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @arg @ref RTC_IT_ALRB Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__)) +#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (RTC->CR |= (__INTERRUPT__))) /** * @brief Disable the RTC Alarm interrupt. @@ -686,7 +688,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @arg @ref RTC_IT_ALRB Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__)) +#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (RTC->CR &= ~(__INTERRUPT__))) /** * @brief Check whether the specified RTC Alarm interrupt has occurred or not. @@ -697,7 +699,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @arg @ref RTC_IT_ALRB Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR)& ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL) +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), ((((RTC->MISR)& ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL)) /** * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. @@ -708,7 +710,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @arg @ref RTC_IT_ALRB Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL) +#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)) /** * @brief Get the selected RTC Alarms flag status. @@ -730,8 +732,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @arg @ref RTC_FLAG_ALRBF * @retval None */ -#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) \ - (((__FLAG__) == RTC_FLAG_ALRAF) ? ((RTC->SCR = (RTC_CLEAR_ALRAF))) : (RTC->SCR = (RTC_CLEAR_ALRBF))) +#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) (UNUSED(__HANDLE__), \ + (((__FLAG__) == RTC_FLAG_ALRAF) ? ((RTC->SCR = (RTC_CLEAR_ALRAF))) : (RTC->SCR = (RTC_CLEAR_ALRBF)))) /** * @brief Enable interrupt on the RTC Alarm associated Exti line. * @retval None diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_rtc_ex.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_rtc_ex.h index 0b2ae98cd3..b5ae1133e0 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_rtc_ex.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_rtc_ex.h @@ -533,7 +533,7 @@ typedef struct * @arg @ref RTC_CLEAR_SSRUF Clear SSR underflow flag" * @retval None */ -#define __HAL_RTC_CLEAR_FLAG(__HANDLE__, __FLAG__) (RTC->SCR = (__FLAG__)) +#define __HAL_RTC_CLEAR_FLAG(__HANDLE__, __FLAG__) (UNUSED(__HANDLE__), (RTC->SCR = (__FLAG__))) /** @brief Check whether the specified RTC flag is set or not. * @param __HANDLE__ specifies the RTC Handle. @@ -554,8 +554,8 @@ typedef struct * @retval The state of __FLAG__ (TRUE or FALSE). */ #define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__) \ - (((((__FLAG__)) >> 8U) == 1U) ? (RTC->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_IT_MASK))) : \ - (RTC->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_IT_MASK)))) + (UNUSED(__HANDLE__), (((((__FLAG__)) >> 8U) == 1U) ? (RTC->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_IT_MASK))) : \ + (RTC->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_IT_MASK))))) /* ---------------------------------WAKEUPTIMER---------------------------------*/ /** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer @@ -566,14 +566,14 @@ typedef struct * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_WUTE)) +#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_WUTE))) /** * @brief Disable the RTC WakeUp Timer peripheral. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_WUTE)) +#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_WUTE))) /** * @brief Enable the RTC WakeUpTimer interrupt. @@ -583,7 +583,7 @@ typedef struct * @arg @ref RTC_IT_WUT WakeUpTimer interrupt * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__)) +#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (RTC->CR |= (__INTERRUPT__))) /** * @brief Disable the RTC WakeUpTimer interrupt. @@ -593,7 +593,7 @@ typedef struct * @arg @ref RTC_IT_WUT WakeUpTimer interrupt * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__)) +#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (RTC->CR &= ~(__INTERRUPT__))) /** @@ -604,8 +604,8 @@ typedef struct * @arg @ref RTC_IT_WUT WakeUpTimer interrupt * @retval The state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) &\ - ((__INTERRUPT__)>> 12U)) != 0UL) ? 1UL : 0UL) +#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), ((((RTC->MISR) &\ + ((__INTERRUPT__)>> 12U)) != 0UL) ? 1UL : 0UL)) /** * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. @@ -614,8 +614,8 @@ typedef struct * @arg @ref RTC_IT_WUT WakeUpTimer interrupt * @retval The state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) &\ - (__INTERRUPT__)) != 0UL) ? 1UL : 0UL) +#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), ((((RTC->CR) &\ + (__INTERRUPT__)) != 0UL) ? 1UL : 0UL)) /** * @brief Get the selected RTC WakeUpTimers flag status. @@ -678,14 +678,14 @@ typedef struct * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_TSE)) +#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_TSE))) /** * @brief Disable the RTC TimeStamp peripheral. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_TSE)) +#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_TSE))) /** * @brief Enable the RTC TimeStamp interrupt. @@ -695,7 +695,7 @@ typedef struct * @arg @ref RTC_IT_TS TimeStamp interrupt * @retval None */ -#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__)) +#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (RTC->CR |= (__INTERRUPT__))) /** * @brief Disable the RTC TimeStamp interrupt. @@ -705,7 +705,7 @@ typedef struct * @arg @ref RTC_IT_TS TimeStamp interrupt * @retval None */ -#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__)) +#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (RTC->CR &= ~(__INTERRUPT__))) /** * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. @@ -715,8 +715,8 @@ typedef struct * @arg @ref RTC_IT_TS TimeStamp interrupt * @retval The state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) &\ - ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL) +#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), ((((RTC->MISR) &\ + ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL)) /** * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. @@ -725,8 +725,8 @@ typedef struct * @arg @ref RTC_IT_TS TimeStamp interrupt * @retval The state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) &\ - (__INTERRUPT__)) != 0U) ? 1UL : 0UL) +#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), ((((RTC->CR) &\ + (__INTERRUPT__)) != 0U) ? 1UL : 0UL)) /** * @brief Get the selected RTC TimeStamps flag status. @@ -781,14 +781,14 @@ typedef struct * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_ITSE)) +#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_ITSE))) /** * @brief Disable the RTC internal TimeStamp peripheral. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_ITSE)) +#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_ITSE))) /** * @brief Get the selected RTC Internal Time Stamps flag status. @@ -816,28 +816,28 @@ typedef struct * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_TAMPTS)) +#define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_TAMPTS))) /** * @brief Disable the RTC TimeStamp on Tamper detection. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_TAMPTS)) +#define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_TAMPTS))) /** * @brief Enable the RTC Tamper detection output. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_TAMPOE_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_TAMPOE)) +#define __HAL_RTC_TAMPOE_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_TAMPOE))) /** * @brief Disable the RTC Tamper detection output. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_TAMPOE_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_TAMPOE)) +#define __HAL_RTC_TAMPOE_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_TAMPOE))) /** @@ -855,14 +855,14 @@ typedef struct * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_COE)) +#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_COE))) /** * @brief Disable the calibration output. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_COE)) +#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_COE))) /** @@ -870,14 +870,14 @@ typedef struct * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_REFCKON)) +#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_REFCKON))) /** * @brief Disable the clock reference detection. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_REFCKON)) +#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_REFCKON))) /** @@ -1092,7 +1092,7 @@ typedef struct * @arg @ref RTC_IT_SSRU SSRU interrupt * @retval None */ -#define __HAL_RTC_SSRU_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__)) +#define __HAL_RTC_SSRU_ENABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (RTC->CR |= (__INTERRUPT__))) /** * @brief Disable the RTC SSRU interrupt. @@ -1102,7 +1102,7 @@ typedef struct * @arg @ref RTC_IT_SSRU SSRU interrupt * @retval None */ -#define __HAL_RTC_SSRU_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__)) +#define __HAL_RTC_SSRU_DISABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (RTC->CR &= ~(__INTERRUPT__))) /** @@ -1113,7 +1113,7 @@ typedef struct * @arg @ref RTC_IT_SSRU SSRU interrupt * @retval The state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_RTC_SSRU_GET_IT(__HANDLE__, __INTERRUPT__) (((RTC->MISR) & ((__INTERRUPT__) >> 1) != 0U) ? 1U : 0U) +#define __HAL_RTC_SSRU_GET_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (((RTC->MISR) & ((__INTERRUPT__) >> 1) != 0U) ? 1U : 0U)) /** * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. @@ -1122,7 +1122,7 @@ typedef struct * @arg @ref RTC_IT_SSRU SSRU interrupt * @retval The state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_RTC_SSRU_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) +#define __HAL_RTC_SSRU_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)) /** * @brief Get the selected RTC SSRU's flag status. diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_smartcard.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_smartcard.h index 50487c2bbb..adb4db8d06 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_smartcard.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_smartcard.h @@ -713,13 +713,13 @@ typedef void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard) */ #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR1 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR2 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR3 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Check whether the specified SmartCard interrupt has occurred or not. diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_spi.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_spi.h index a947714666..7926b5a0a8 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_spi.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_spi.h @@ -118,7 +118,7 @@ typedef struct __SPI_HandleTypeDef SPI_InitTypeDef Init; /*!< SPI communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ uint16_t TxXferSize; /*!< SPI Tx Transfer size */ @@ -426,11 +426,12 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval None */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ @@ -533,7 +534,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to __IO uint32_t tmpreg_fre = 0x00U; \ tmpreg_fre = (__HANDLE__)->Instance->SR; \ UNUSED(tmpreg_fre); \ - }while(0U) + } while(0U) /** @brief Enable the SPI peripheral. * @param __HANDLE__ specifies the SPI Handle. @@ -577,8 +578,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ - SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) +#define SPI_RESET_CRC(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + } while(0U) /** @brief Check whether the specified SPI flag is set or not. * @param __SR__ copy of SPI SR register. @@ -596,7 +600,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ - ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) + ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. * @param __CR2__ copy of SPI CR2 register. @@ -608,7 +612,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ - (__INTERRUPT__)) ? SET : RESET) + (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if SPI Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Mode. @@ -746,7 +750,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ ((__POLYNOMIAL__) <= 0xFFFFU) && \ - (((__POLYNOMIAL__)&0x1U) != 0U)) + (((__POLYNOMIAL__)&0x1U) != 0U)) /** @brief Checks if DMA handle is valid. * @param __HANDLE__ specifies a DMA Handle. @@ -789,17 +793,17 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @{ */ /* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); @@ -825,8 +829,8 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); /** * @} */ diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_uart.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_uart.h index 4a8183eb04..85e9abd5f8 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_uart.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_uart.h @@ -47,12 +47,10 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the UART communication baud rate. The baud rate register is computed using the following formula: - LPUART: - ======= + @note For LPUART : Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) - where lpuart_ker_ck_pres is the UART input clock divided by a prescaler - UART: - ===== + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler. + @note For UART : - If oversampling is 16 or in LIN mode, Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - If oversampling is 8, diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_usart.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_usart.h index 6cc6aceff7..9106067efc 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_usart.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_hal_usart.h @@ -537,10 +537,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR1 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + ((__HANDLE__)->Instance->CR2 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. * @param __HANDLE__ specifies the USART Handle. @@ -562,10 +562,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR1 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + ((__HANDLE__)->Instance->CR2 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Check whether the specified USART interrupt has occurred or not. * @param __HANDLE__ specifies the USART Handle. diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_adc.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_adc.h index 4782b690b3..b99a625210 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_adc.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_adc.h @@ -258,17 +258,17 @@ extern "C" { /* ADC internal channels related definitions */ /* Internal voltage reference VrefInt */ -#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF6EA4UL)) /* Internal voltage reference, address of +#define VREFINT_CAL_ADDR ((const uint16_t*) (0x1FFF6EA4UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 Deg (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ #define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) value with which VrefInt has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ /* Temperature sensor */ -#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF6E68UL)) /* Address of parameter TS_CAL1: On STM32U0, +#define TEMPSENSOR_CAL1_ADDR ((const uint16_t*) (0x1FFF6E68UL)) /* Address of parameter TS_CAL1: temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF6E8AUL)) /* Address of parameter TS_CAL2: On STM32U0, +#define TEMPSENSOR_CAL2_ADDR ((const uint16_t*) (0x1FFF6E8AUL)) /* Address of parameter TS_CAL2: temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Temperature at which temperature sensor @@ -3830,7 +3830,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK) >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + ADC_SMPR_SMPSEL0_BITOFFSET_POS) - & 0x1FUL)); + & 0x1FUL)) & 0x01UL; /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */ return ((~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1) diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_comp.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_comp.h index ceb17fdaab..66593df62a 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_comp.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_comp.h @@ -470,6 +470,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowOutput(const COMP_Common_TypeDef * @param PowerMode This parameter can be one of the following values: * @arg @ref LL_COMP_POWERMODE_HIGHSPEED * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED + * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER * @retval None */ __STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode) @@ -484,6 +485,7 @@ __STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMod * @retval Returned value can be one of the following values: * @arg @ref LL_COMP_POWERMODE_HIGHSPEED * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED + * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER */ __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(const COMP_TypeDef *COMPx) { diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_lptim.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_lptim.h index cf3c602492..c7e84dd842 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_lptim.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_lptim.h @@ -84,23 +84,22 @@ static const uint8_t LL_LPTIM_SHIFT_TAB_CCxSEL[] = static const uint8_t LL_LPTIM_SHIFT_TAB_CCxE[] = { - LPTIM_CCMR1_CC1E_Pos, /* CC1E */ - LPTIM_CCMR1_CC2E_Pos, /* CC2E */ - LPTIM_CCMR2_CC3E_Pos, /* CC3E */ - LPTIM_CCMR2_CC4E_Pos, /* CC4E */ + (uint8_t)LPTIM_CCMR1_CC1E_Pos, /* CC1E */ + (uint8_t)LPTIM_CCMR1_CC2E_Pos, /* CC2E */ + (uint8_t)LPTIM_CCMR2_CC3E_Pos, /* CC3E */ + (uint8_t)LPTIM_CCMR2_CC4E_Pos, /* CC4E */ }; static const uint8_t LL_LPTIM_OFFSET_TAB_ICx[8][4] = { - {2, 7, 9, 13}, - {3, 5, 6, 8}, - {2, 3, 4, 5}, - {2, 2, 3, 3}, - {2, 2, 2, 2}, - {2, 2, 2, 2}, - {2, 2, 2, 2}, - {2, 2, 2, 2} - + {2U, 7U, 9U, 13U}, + {3U, 5U, 6U, 8U}, + {2U, 3U, 4U, 5U}, + {2U, 2U, 3U, 3U}, + {2U, 2U, 2U, 2U}, + {2U, 2U, 2U, 2U}, + {2U, 2U, 2U, 2U}, + {2U, 2U, 2U, 2U} }; /** diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_lpuart.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_lpuart.h index e961e8e462..f889641987 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_lpuart.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_lpuart.h @@ -56,6 +56,10 @@ static const uint16_t LPUART_PRESCALER_TAB[] = (uint16_t)32, (uint16_t)64, (uint16_t)128, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256, (uint16_t)256 }; /** diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_spi.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_spi.h index bdbb7f5e18..3e05ece089 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_spi.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_spi.h @@ -55,53 +55,66 @@ typedef struct uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferDirection().*/ uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). This parameter can be a value of @ref SPI_LL_EC_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetMode().*/ uint32_t DataWidth; /*!< Specifies the SPI data width. This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetDataWidth().*/ uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. This parameter can be a value of @ref SPI_LL_EC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPolarity().*/ uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. This parameter can be a value of @ref SPI_LL_EC_PHASE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPhase().*/ - uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) + or by software using the SSI bit. This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetNSSMode().*/ - uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used + to configure the transmit and receive SCK clock. This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. - @note The communication clock is derived from the master clock. The slave clock does not need to be set. + @note The communication clock is derived from the master clock. + The slave clock does not need to be set. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetBaudRatePrescaler().*/ uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferBitOrder().*/ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. - This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + This feature can be modified afterwards using unitary + functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetCRCPolynomial().*/ } LL_SPI_InitTypeDef; @@ -378,7 +391,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); } @@ -408,7 +421,7 @@ __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) * @arg @ref LL_SPI_MODE_MASTER * @arg @ref LL_SPI_MODE_SLAVE */ -__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); } @@ -436,7 +449,7 @@ __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) * @arg @ref LL_SPI_PROTOCOL_MOTOROLA * @arg @ref LL_SPI_PROTOCOL_TI */ -__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); } @@ -465,7 +478,7 @@ __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase * @arg @ref LL_SPI_PHASE_1EDGE * @arg @ref LL_SPI_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); } @@ -494,7 +507,7 @@ __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo * @arg @ref LL_SPI_POLARITY_LOW * @arg @ref LL_SPI_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); } @@ -534,7 +547,7 @@ __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Bau * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 */ -__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); } @@ -562,7 +575,7 @@ __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitO * @arg @ref LL_SPI_LSB_FIRST * @arg @ref LL_SPI_MSB_FIRST */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); } @@ -599,7 +612,7 @@ __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t Tra * @arg @ref LL_SPI_HALF_DUPLEX_RX * @arg @ref LL_SPI_HALF_DUPLEX_TX */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); } @@ -648,7 +661,7 @@ __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) * @arg @ref LL_SPI_DATAWIDTH_15BIT * @arg @ref LL_SPI_DATAWIDTH_16BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); } @@ -675,7 +688,7 @@ __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Thres * @arg @ref LL_SPI_RX_FIFO_TH_HALF * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); } @@ -719,7 +732,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); } @@ -747,7 +760,7 @@ __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) * @arg @ref LL_SPI_CRC_8BIT * @arg @ref LL_SPI_CRC_16BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); } @@ -782,7 +795,7 @@ __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->CRCPR)); } @@ -793,7 +806,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->RXCRCR)); } @@ -804,7 +817,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->TXCRCR)); } @@ -845,7 +858,7 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) * @arg @ref LL_SPI_NSS_HARD_INPUT * @arg @ref LL_SPI_NSS_HARD_OUTPUT */ -__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx) { uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); @@ -883,7 +896,7 @@ __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL); } @@ -902,7 +915,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); } @@ -913,7 +926,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); } @@ -924,7 +937,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); } @@ -935,7 +948,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); } @@ -946,7 +959,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); } @@ -964,7 +977,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); } @@ -975,7 +988,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); } @@ -990,7 +1003,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) * @arg @ref LL_SPI_RX_FIFO_HALF_FULL * @arg @ref LL_SPI_RX_FIFO_FULL */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); } @@ -1005,7 +1018,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) * @arg @ref LL_SPI_TX_FIFO_HALF_FULL * @arg @ref LL_SPI_TX_FIFO_FULL */ -__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); } @@ -1045,7 +1058,7 @@ __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->DR; @@ -1061,7 +1074,7 @@ __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_SPI_ClearFlag_FRE(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->SR; @@ -1078,7 +1091,8 @@ __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) /** * @brief Enable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR * @param SPIx SPI Instance * @retval None @@ -1112,7 +1126,8 @@ __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) /** * @brief Disable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR * @param SPIx SPI Instance * @retval None @@ -1150,7 +1165,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); } @@ -1161,7 +1176,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); } @@ -1172,7 +1187,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); } @@ -1213,7 +1228,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); } @@ -1246,7 +1261,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); } @@ -1273,7 +1288,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) * @arg @ref LL_SPI_DMA_PARITY_ODD * @arg @ref LL_SPI_DMA_PARITY_EVEN */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); } @@ -1300,7 +1315,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) * @arg @ref LL_SPI_DMA_PARITY_ODD * @arg @ref LL_SPI_DMA_PARITY_EVEN */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); } @@ -1311,7 +1326,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx) { return (uint32_t) &(SPIx->DR); } @@ -1388,7 +1403,7 @@ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) * @{ */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx); ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_usart.h b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_usart.h index ec904b702f..414de8d7aa 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_usart.h +++ b/system/Drivers/STM32U0xx_HAL_Driver/Inc/stm32u0xx_ll_usart.h @@ -56,6 +56,10 @@ static const uint32_t USART_PRESCALER_TAB[] = 32UL, 64UL, 128UL, + 256UL, + 256UL, + 256UL, + 256UL, 256UL }; /** diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32U0xx_HAL_Driver/Release_Notes.html index 5d84d76cc0..7b8618f3c6 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32U0xx_HAL_Driver/Release_Notes.html @@ -40,11 +40,69 @@

                                                                                          Purpose

                                                                                          Update History

                                                                                          - +

                                                                                          Main Changes

                                                                                          -

                                                                                          Second maintenance release of HAL and LL drivers for STM32U083 / STM32U073 / STM32U031 devices

                                                                                          +

                                                                                          Third maintenance release of HAL and LL drivers for STM32U083 / STM32U073 / STM32U031 devices

                                                                                          Contents

                                                                                          +

                                                                                          HAL and LL driver third maintenance release

                                                                                          +
                                                                                            +
                                                                                          • HAL drivers: +
                                                                                              +
                                                                                            • HAL ADC driver: +
                                                                                                +
                                                                                              • Update the “HAL_ADCEx_Calibration_Start” function to use properly “LL_ADC_GetCalibrationFactor”.
                                                                                                • +
                                                                                              • +
                                                                                            • HAL CRYP driver: +
                                                                                                +
                                                                                              • Rename AES suspend registers according last update in STM32U0 reference manual.
                                                                                                • +
                                                                                              • +
                                                                                            • HAL CRC driver: +
                                                                                                +
                                                                                              • Improve performance of “CRC_Handle_8” function.
                                                                                                • +
                                                                                              • +
                                                                                            • HAL RTC driver: +
                                                                                                +
                                                                                              • Minors implementation enhancements.
                                                                                                • +
                                                                                              • +
                                                                                            • HAL SPI driver: +
                                                                                                +
                                                                                              • Implementation enhancements.
                                                                                                • +
                                                                                              • +
                                                                                            • HAL UART driver: +
                                                                                                +
                                                                                              • Implementation enhancements.
                                                                                                • +
                                                                                              • +
                                                                                            • LL ADC driver: +
                                                                                                +
                                                                                              • Update the “LL_ADC_GetChannelSamplingTime” to return correct value when multiple channels configured.
                                                                                                • +
                                                                                              • +
                                                                                            • LL COMP driver: +
                                                                                                +
                                                                                              • Update the “IS_LL_COMP_POWER_MODE” macro to support the “LL_COMP_POWERMODE_ULTRALOWPOWER”.
                                                                                                • +
                                                                                              • +
                                                                                            • LL SPI driver: +
                                                                                                +
                                                                                              • Minors implementation enhancements.
                                                                                                • +
                                                                                              • +
                                                                                            • +
                                                                                          +

                                                                                          Known Limitations

                                                                                          +
                                                                                            +
                                                                                          • None
                                                                                            • +
                                                                                          +

                                                                                          Backward Compatibility

                                                                                          +
                                                                                            +
                                                                                          • Not applicable
                                                                                            • +
                                                                                          +
                                                                                          +
                                                                                          +
                                                                                          + +
                                                                                          +

                                                                                          Main Changes

                                                                                          +

                                                                                          Second maintenance release of HAL and LL drivers for STM32U083 / STM32U073 / STM32U031 devices

                                                                                          +

                                                                                          Contents

                                                                                          HAL and LL driver second maintenance release

                                                                                          • HAL drivers: @@ -63,11 +121,11 @@

                                                                                            Contents

                                                                                      -

                                                                                      Known Limitations

                                                                                      +

                                                                                      Known Limitations

                                                                                      • None
                                                                                      -

                                                                                      Backward Compatibility

                                                                                      +

                                                                                      Backward Compatibility

                                                                                      • Not applicable
                                                                                      @@ -76,9 +134,9 @@

                                                                                      Backward Compatibility

                                                                                      -

                                                                                      Main Changes

                                                                                      +

                                                                                      Main Changes

                                                                                      Maintenance release of HAL and LL drivers for STM32U083 / STM32U073 / STM32U031 devices

                                                                                      -

                                                                                      Contents

                                                                                      +

                                                                                      Contents

                                                                                      HAL and LL driver maintenance release

                                                                                      • HAL drivers: @@ -101,11 +159,11 @@

                                                                                        Contents

                                                                                  -

                                                                                  Known Limitations

                                                                                  +

                                                                                  Known Limitations

                                                                                  • None
                                                                                  -

                                                                                  Backward Compatibility

                                                                                  +

                                                                                  Backward Compatibility

                                                                                  • Not applicable
                                                                                  @@ -114,19 +172,19 @@

                                                                                  Backward Compatibility

                                                                                  -

                                                                                  Main Changes

                                                                                  +

                                                                                  Main Changes

                                                                                  First official release of HAL and LL drivers for STM32U083 / STM32U073 / STM32U031 devices

                                                                                  -

                                                                                  Contents

                                                                                  +

                                                                                  Contents

                                                                                  HAL and LL driver beta version for all peripherals

                                                                                  • HAL: ADC, CORTEX, COMP, CRC, CRYP, DAC, DMA, EXTI, GPIO, I2C, I2S, IRDA, IWDG, LPTIM, OPAMP, LTDC, PCD, PWR, RCC, RNG, RTC, SMARTCARD, SPI, TIM, UART, USART, WWDG

                                                                                  • LL: ADC, COMP, CRC, CRS, DAC, DMA, EXTI, GPIO, I2C, LPTIM, LPUART, OPAMP, PWR, RCC, RNG, RTC, SPI, TIM, USART, USB, UTILS

                                                                                  -

                                                                                  Known Limitations

                                                                                  +

                                                                                  Known Limitations

                                                                                  • None
                                                                                  -

                                                                                  Backward Compatibility

                                                                                  +

                                                                                  Backward Compatibility

                                                                                  • Not applicable
                                                                                  diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal.c index 1b8961257e..162b1288d4 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal.c @@ -54,17 +54,17 @@ /** * @brief STM32U0xx HAL Driver version number */ -#define __STM32U0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32U0xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ -#define __STM32U0xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ -#define __STM32U0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ -#define __STM32U0xx_HAL_VERSION ((__STM32U0xx_HAL_VERSION_MAIN << 24U)\ - |(__STM32U0xx_HAL_VERSION_SUB1 << 16U)\ - |(__STM32U0xx_HAL_VERSION_SUB2 << 8U )\ +#define __STM32U0xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ +#define __STM32U0xx_HAL_VERSION_SUB1 (0x03UL) /*!< [23:16] sub1 version */ +#define __STM32U0xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */ +#define __STM32U0xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ +#define __STM32U0xx_HAL_VERSION ((__STM32U0xx_HAL_VERSION_MAIN << 24UL) \ + |(__STM32U0xx_HAL_VERSION_SUB1 << 16UL)\ + |(__STM32U0xx_HAL_VERSION_SUB2 << 8UL) \ |(__STM32U0xx_HAL_VERSION_RC)) #if defined(VREFBUF) -#define VREFBUF_TIMEOUT_VALUE 10U /*!< 10 ms */ +#define VREFBUF_TIMEOUT_VALUE 10UL /*!< 10 ms */ #endif /* VREFBUF */ /** @@ -78,7 +78,7 @@ */ __IO uint32_t uwTick; uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ -uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ /** * @} */ @@ -239,10 +239,10 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { HAL_StatusTypeDef status = HAL_OK; - if (uwTickFreq != 0U) + if ((uint32_t)uwTickFreq != 0U) { /*Configure the SysTick to have interrupt in 1ms time basis*/ - if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U) { /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) @@ -304,7 +304,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) */ __weak void HAL_IncTick(void) { - uwTick += uwTickFreq; + uwTick += (uint32_t)uwTickFreq; } /** @@ -331,17 +331,28 @@ uint32_t HAL_GetTickPrio(void) * @brief Set new tick Freq. * @retval Status */ -HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq) +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) { HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; assert_param(IS_TICKFREQ(Freq)); if (uwTickFreq != Freq) { + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ uwTickFreq = Freq; /* Apply the new tick Freq */ status = HAL_InitTick(uwTickPrio); + + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } } return status; @@ -351,7 +362,7 @@ HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq) * @brief return tick frequency. * @retval tick period in Hz */ -uint32_t HAL_GetTickFreq(void) +HAL_TickFreqTypeDef HAL_GetTickFreq(void) { return uwTickFreq; } @@ -430,7 +441,7 @@ uint32_t HAL_GetHalVersion(void) */ uint32_t HAL_GetREVID(void) { - return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16U); + return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); } /** diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_adc_ex.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_adc_ex.c index a402a68692..c8675878a2 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_adc_ex.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_adc_ex.c @@ -163,9 +163,11 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) } } - calibration_factor_accumulated += LL_ADC_GetCalibrationFactor(hadc->Instance); + /* Read the calibration factor and increment by one */ + calibration_factor_accumulated += (LL_ADC_GetCalibrationFactor(hadc->Instance) + 1UL); } - /* Compute average */ + /* Compute average (rounded up to the nearest integer) */ + calibration_factor_accumulated += (calibration_index / 2UL); calibration_factor_accumulated /= calibration_index; /* Apply calibration factor (requires ADC enable and disable process) */ diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_crc.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_crc.c index 9d1d858077..f5303aca1c 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_crc.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_crc.c @@ -452,13 +452,13 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ { *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ } - if ((BufferLength % 4U) == 2U) + else if ((BufferLength % 4U) == 2U) { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ *pReg = data; } - if ((BufferLength % 4U) == 3U) + else if ((BufferLength % 4U) == 3U) { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ @@ -466,6 +466,10 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ } + else + { + /* Nothing to do */ + } } /* Return the CRC computed value */ diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_cryp.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_cryp.c index de216ba10a..7a5c02c339 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_cryp.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_cryp.c @@ -963,7 +963,7 @@ HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp) (hcryp->Init.Algorithm == CRYP_AES_CCM)) { /* Save Suspension registers */ - CRYP_Read_SuspendRegisters(hcryp, hcryp->SUSPxR_saved); + CRYP_Read_SuspendRegisters(hcryp, hcryp->SUSPRx_saved); /* Save Key */ CRYP_Read_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize); /* Save IV */ @@ -1053,10 +1053,10 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp) hcryp->CrypHeaderCount = hcryp->CrypHeaderCount_saved; hcryp->SizesSum = hcryp->SizesSum_saved; - /* Disable AES and write-back SUSPxR registers */; + /* Disable AES and write-back SUSPRx registers */; __HAL_CRYP_DISABLE(hcryp); /* Restore AES Suspend Registers */ - CRYP_Write_SuspendRegisters(hcryp, hcryp->SUSPxR_saved); + CRYP_Write_SuspendRegisters(hcryp, hcryp->SUSPRx_saved); /* Restore Control, Key and IV Registers, then enable AES */ hcryp->Instance->CR = hcryp->CR_saved; CRYP_Write_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize); @@ -5300,7 +5300,7 @@ static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input) * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. * @param Output Pointer to the buffer containing the saved Suspend Registers. - * @note These values have to be stored for reuse by writing back the AES_SUSPxR registers + * @note These values have to be stored for reuse by writing back the AES_SUSPRx registers * as soon as the suspended processing has to be resumed. * @retval None */ @@ -5335,21 +5335,21 @@ static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Outp } - *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP7R; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSPR7; outputaddr += 4U; - *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP6R; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSPR6; outputaddr += 4U; - *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP5R; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSPR5; outputaddr += 4U; - *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP4R; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSPR4; outputaddr += 4U; - *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP3R; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSPR3; outputaddr += 4U; - *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP2R; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSPR2; outputaddr += 4U; - *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP1R; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSPR1; outputaddr += 4U; - *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP0R; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSPR0; } /** @@ -5366,21 +5366,21 @@ static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Inp { uint32_t ivaddr = (uint32_t)Input; - hcryp->Instance->SUSP7R = *(uint32_t *)(ivaddr); + hcryp->Instance->SUSPR7 = *(uint32_t *)(ivaddr); ivaddr += 4U; - hcryp->Instance->SUSP6R = *(uint32_t *)(ivaddr); + hcryp->Instance->SUSPR6 = *(uint32_t *)(ivaddr); ivaddr += 4U; - hcryp->Instance->SUSP5R = *(uint32_t *)(ivaddr); + hcryp->Instance->SUSPR5 = *(uint32_t *)(ivaddr); ivaddr += 4U; - hcryp->Instance->SUSP4R = *(uint32_t *)(ivaddr); + hcryp->Instance->SUSPR4 = *(uint32_t *)(ivaddr); ivaddr += 4U; - hcryp->Instance->SUSP3R = *(uint32_t *)(ivaddr); + hcryp->Instance->SUSPR3 = *(uint32_t *)(ivaddr); ivaddr += 4U; - hcryp->Instance->SUSP2R = *(uint32_t *)(ivaddr); + hcryp->Instance->SUSPR2 = *(uint32_t *)(ivaddr); ivaddr += 4U; - hcryp->Instance->SUSP1R = *(uint32_t *)(ivaddr); + hcryp->Instance->SUSPR1 = *(uint32_t *)(ivaddr); ivaddr += 4U; - hcryp->Instance->SUSP0R = *(uint32_t *)(ivaddr); + hcryp->Instance->SUSPR0 = *(uint32_t *)(ivaddr); } /** diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_flash_ex.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_flash_ex.c index 8810051f7f..8fd256efad 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_flash_ex.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_flash_ex.c @@ -418,7 +418,7 @@ uint32_t HAL_FLASHEx_FlashEmptyCheck(void) /** * @brief Force Empty check value. * @note Allows to modify program empty check value in order to force this - * infrmation in Flash Interface, for all next reset that do not launch + * information in Flash Interface, for all next reset that do not launch * Option Byte Loader. * @param FlashEmpty this parameter can be a value of @ref FLASHEx_Empty_Check * @retval None diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_rtc_ex.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_rtc_ex.c index 22178d2a64..e6036d78a6 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_rtc_ex.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_rtc_ex.c @@ -1504,7 +1504,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(const RTC_HandleTypeDef *hrtc, const RT tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | \ (sTamper->Tamper << TAMP_CR2_TAMP1POM_Pos)); - if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) + if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)) { tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos); } diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_spi.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_spi.c index a0e5d63f32..cefebd610b 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_spi.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_spi.c @@ -44,7 +44,8 @@ (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx Stream/Channel (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx + or Rx Stream/Channel (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. @@ -190,7 +191,8 @@ @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). @note - (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and + HAL_SPI_TransmitReceive_DMA() (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() @@ -813,43 +815,40 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @brief Transmit an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent - * @param Timeout Timeout duration + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration in ms * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; uint16_t initial_TxXferCount; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); initial_TxXferCount = Size; if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -888,7 +887,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } @@ -898,7 +897,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } @@ -907,9 +906,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -919,7 +918,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); hspi->TxXferCount--; } @@ -928,7 +927,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); hspi->TxXferCount--; } @@ -937,9 +936,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -964,29 +963,31 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint __HAL_SPI_CLEAR_OVRFLAG(hspi); } + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error: - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; } /** * @brief Receive an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be received - * @param Timeout Timeout duration + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be received + * @param Timeout Timeout duration in ms * @retval HAL status + * @note In master mode, if the direction is set to SPI_DIRECTION_2LINES + * the receive buffer is written to data register (DR) to generate + * clock pulses and receive data */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { @@ -996,12 +997,15 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) @@ -1011,17 +1015,11 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); } - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } + /* Process Locked */ + __HAL_LOCK(hspi); /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1093,9 +1091,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1117,9 +1115,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1136,8 +1134,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { /* the latest data has not been received */ - errorcode = HAL_TIMEOUT; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Receive last data in 16 Bit mode */ @@ -1155,8 +1153,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read CRC to Flush DR and RXNE flag */ @@ -1182,8 +1181,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ tmpreg8 = *ptmpreg8; @@ -1209,32 +1209,31 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } #endif /* USE_SPI_CRC */ + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error : - __HAL_UNLOCK(hspi); - return errorcode; } /** * @brief Transmit and Receive an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer - * @param Size amount of data to be sent and received - * @param Timeout Timeout duration + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent and received + * @param Timeout Timeout duration in ms * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) { uint16_t initial_TxXferCount; uint32_t tmp_mode; @@ -1250,14 +1249,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Variable used to alternate Rx and Tx during transfer */ uint32_t txallowed = 1U; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1271,18 +1266,20 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD #endif /* USE_SPI_CRC */ if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -1294,7 +1291,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->pRxBuffPtr = (uint8_t *)pRxData; hspi->RxXferCount = Size; hspi->RxXferSize = Size; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferCount = Size; hspi->TxXferSize = Size; @@ -1334,7 +1331,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -1357,7 +1354,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; /* Next Data is a reception (Rx). Tx not allowed */ @@ -1388,9 +1385,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1399,7 +1396,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); hspi->TxXferCount--; @@ -1421,7 +1418,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; /* Next Data is a reception (Rx). Tx not allowed */ @@ -1452,9 +1449,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1468,8 +1465,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read CRC */ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) @@ -1494,8 +1492,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ tmpreg8 = *ptmpreg8; @@ -1511,43 +1510,44 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); /* Clear CRC Flag */ __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - - errorcode = HAL_ERROR; + __HAL_UNLOCK(hspi); + return HAL_ERROR; } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) { - errorcode = HAL_ERROR; hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + __HAL_UNLOCK(hspi); + return HAL_ERROR; } + + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error : - __HAL_UNLOCK(hspi); - return errorcode; } /** * @brief Transmit an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -1555,14 +1555,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } /* Process Locked */ @@ -1571,7 +1569,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1619,27 +1617,28 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Enable TXE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** * @brief Receive an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) @@ -1650,12 +1649,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui } - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - /* Process Locked */ __HAL_LOCK(hspi); @@ -1727,24 +1720,23 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Enable RXNE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer - * @param Size amount of data to be sent and received + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent and received * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -1754,16 +1746,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } /* Process locked */ @@ -1777,7 +1768,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -1838,21 +1829,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Enable TXE, RXNE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** * @brief Transmit an amount of data in non-blocking mode with DMA. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; /* Check tx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); @@ -1860,25 +1849,23 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1940,9 +1927,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -1952,16 +1939,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, __HAL_SPI_ENABLE(hspi); } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -1969,22 +1956,24 @@ error : * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer + * @param pData pointer to data buffer (u8 or u16 data elements) * @note When the CRC feature is enabled the pData Length must be Size + 1. - * @param Size amount of data to be sent + * @param Size amount of data elements (u8 or u16) to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - /* Check rx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) @@ -2001,12 +1990,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Process Locked */ __HAL_LOCK(hspi); - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -2084,9 +2067,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2096,34 +2079,33 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u __HAL_SPI_ENABLE(hspi); } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Rx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); -error: - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) * @note When the CRC feature is enabled the pRxData Length must be Size + 1 - * @param Size amount of data to be sent + * @param Size amount of data elements (u8 or u16) to be sent and received * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check rx & tx dma handles */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); @@ -2132,26 +2114,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process locked */ - __HAL_LOCK(hspi); - /* Init temporary variables */ tmp_state = hspi->State; tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -2160,7 +2141,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -2251,9 +2232,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Enable Rx DMA Request */ @@ -2272,9 +2253,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2283,16 +2264,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -2385,7 +2367,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -2418,7 +2401,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -2673,9 +2657,11 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) { HAL_StatusTypeDef errorcode = HAL_OK; /* The Lock is not implemented on this API to allow the user application - to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback(): when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback() */ /* Abort the SPI DMA tx Stream/Channel */ @@ -2965,7 +2951,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI state */ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi) { /* Return SPI handle state */ return hspi->State; @@ -2977,7 +2963,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI error code in bitmap format */ -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) { /* Return SPI ErrorCode */ return hspi->ErrorCode; @@ -3004,7 +2990,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) */ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; /* Init tickstart for timeout management*/ @@ -3061,7 +3047,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -3178,7 +3164,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -3216,7 +3202,8 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) } else { - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, + tickstart) != HAL_OK) { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); @@ -3278,7 +3265,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Tx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3296,7 +3283,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Rx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3314,7 +3301,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user TxRx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3332,7 +3319,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Stop the disable DMA transfer on SPI side */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); @@ -3355,7 +3342,7 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma) */ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); hspi->RxXferCount = 0U; hspi->TxXferCount = 0U; @@ -3377,7 +3364,7 @@ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) */ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); hspi->hdmatx->XferAbortCallback = NULL; @@ -3393,7 +3380,8 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -3443,7 +3431,7 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) */ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable SPI Peripheral */ __HAL_SPI_DISABLE(hspi); @@ -3460,7 +3448,8 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -3596,14 +3585,14 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /* Transmit data in packing Bit mode */ if (hspi->TxXferCount >= 2U) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } /* Transmit data in 8 Bit mode */ else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; } @@ -3697,7 +3686,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -3850,7 +3839,7 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; @@ -3876,7 +3865,7 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -3955,7 +3944,10 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, { tmp_timeout = 0U; } - count--; + else + { + count--; + } } } @@ -3978,7 +3970,7 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; - __IO uint8_t *ptmpreg8; + __IO const uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; /* Adjust Timeout value in case of end of transfer */ @@ -4037,7 +4029,10 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, { tmp_timeout = 0U; } - count--; + else + { + count--; + } } } @@ -4333,7 +4328,8 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -4376,7 +4372,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -4405,7 +4402,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_timebase_tim_template.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_timebase_tim_template.c index fe6e04cc06..13d72b27de 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_timebase_tim_template.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_timebase_tim_template.c @@ -57,6 +57,9 @@ static TIM_HandleTypeDef TimHandle; /* Private function prototypes -----------------------------------------------*/ void TIM16_IRQHandler(void); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) +void TimeBase_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Private functions ---------------------------------------------------------*/ /** @@ -103,11 +106,11 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) TimHandle.Instance = TIM16; /* Initialize TIMx peripheral as follow: - + Period = [(TIM16CLK/1000) - 1]. to have a (1/1000) s time base. - + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. - + ClockDivision = 0 - + Counter direction = Up - */ + * Period = [(TIM16CLK/1000) - 1]. to have a (1/1000) s time base. + * Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + * ClockDivision = 0 + * Counter direction = Up + */ TimHandle.Init.Period = (1000000U / 1000U) - 1U; TimHandle.Init.Prescaler = uwPrescalerValue; TimHandle.Init.ClockDivision = 0U; @@ -116,6 +119,11 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) status = HAL_TIM_Base_Init(&TimHandle); if (status == HAL_OK) { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) + /* Register callback */ + HAL_TIM_RegisterCallback(&TimHandle, HAL_TIM_PERIOD_ELAPSED_CB_ID, TimeBase_TIM_PeriodElapsedCallback); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Start the TIM time Base generation in interrupt mode */ status = HAL_TIM_Base_Start_IT(&TimHandle); if (status == HAL_OK) @@ -170,7 +178,11 @@ void HAL_ResumeTick(void) * @param htim TIM handle * @retval None */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) +void TimeBase_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +#else void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ { HAL_IncTick(); } diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_uart.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_uart.c index 6618689f90..3f704afe13 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_uart.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_uart.c @@ -1024,78 +1024,79 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) =============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of functions allowing to manage the UART asynchronous and Half duplex data transfers. - (#) There are two mode of transfer: - (+) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (+) Non-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected (#) Blocking mode API's are : - (+) HAL_UART_Transmit() - (+) HAL_UART_Receive() + (++) HAL_UART_Transmit() + (++) HAL_UART_Receive() (#) Non-Blocking mode API's with Interrupt are : - (+) HAL_UART_Transmit_IT() - (+) HAL_UART_Receive_IT() - (+) HAL_UART_IRQHandler() + (++) HAL_UART_Transmit_IT() + (++) HAL_UART_Receive_IT() + (++) HAL_UART_IRQHandler() (#) Non-Blocking mode API's with DMA are : - (+) HAL_UART_Transmit_DMA() - (+) HAL_UART_Receive_DMA() - (+) HAL_UART_DMAPause() - (+) HAL_UART_DMAResume() - (+) HAL_UART_DMAStop() + (++) HAL_UART_Transmit_DMA() + (++) HAL_UART_Receive_DMA() + (++) HAL_UART_DMAPause() + (++) HAL_UART_DMAResume() + (++) HAL_UART_DMAStop() (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: - (+) HAL_UART_TxHalfCpltCallback() - (+) HAL_UART_TxCpltCallback() - (+) HAL_UART_RxHalfCpltCallback() - (+) HAL_UART_RxCpltCallback() - (+) HAL_UART_ErrorCallback() + (++) HAL_UART_TxHalfCpltCallback() + (++) HAL_UART_TxCpltCallback() + (++) HAL_UART_RxHalfCpltCallback() + (++) HAL_UART_RxCpltCallback() + (++) HAL_UART_ErrorCallback() (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_UART_Abort() - (+) HAL_UART_AbortTransmit() - (+) HAL_UART_AbortReceive() - (+) HAL_UART_Abort_IT() - (+) HAL_UART_AbortTransmit_IT() - (+) HAL_UART_AbortReceive_IT() + (++) HAL_UART_Abort() + (++) HAL_UART_AbortTransmit() + (++) HAL_UART_AbortReceive() + (++) HAL_UART_Abort_IT() + (++) HAL_UART_AbortTransmit_IT() + (++) HAL_UART_AbortReceive_IT() (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_UART_AbortCpltCallback() - (+) HAL_UART_AbortTransmitCpltCallback() - (+) HAL_UART_AbortReceiveCpltCallback() + (++) HAL_UART_AbortCpltCallback() + (++) HAL_UART_AbortTransmitCpltCallback() + (++) HAL_UART_AbortReceiveCpltCallback() (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services: - (+) HAL_UARTEx_RxEventCallback() + (++) HAL_UARTEx_RxEventCallback() (#) Wakeup from Stop mode Callback: - (+) HAL_UARTEx_WakeupCallback() + (++) HAL_UARTEx_WakeupCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error - in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user - to identify error type, and HAL_UART_ErrorCallback() user callback is executed. - Transfer is kept ongoing on UART side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() - user callback is executed. + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. -@- In the Half duplex communication, it is forbidden to run the transmit and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. @@ -3775,12 +3776,24 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + huart->RxXferCount = 0; + + /* Check current nb of data still to be received on DMA side. + DMA Normal mode, remaining nb of data will be 0 + DMA Circular mode, remaining nb of data is reset to RxXferSize */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data < huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize); + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else @@ -3813,12 +3826,22 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + huart->RxXferCount = huart->RxXferSize / 2U; + + /* Check current nb of data still to be received on DMA side. */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data <= huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize / 2U); + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_uart_ex.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_uart_ex.c index ae9bfdbfba..7792b0afab 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_uart_ex.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_hal_uart_ex.c @@ -24,7 +24,7 @@ ============================================================================== ##### UART peripheral extended features ##### ============================================================================== - + [..] (#) Declare a UART_HandleTypeDef handle structure. (#) For the UART RS485 Driver Enable mode, initialize the UART registers @@ -253,15 +253,13 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, =============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of Wakeup and FIFO mode related callback functions. - (#) Wakeup from Stop mode Callback: - (+) HAL_UARTEx_WakeupCallback() - + (++) HAL_UARTEx_WakeupCallback() (#) TX/RX Fifos Callbacks: - (+) HAL_UARTEx_RxFifoFullCallback() - (+) HAL_UARTEx_TxFifoEmptyCallback() - + (++) HAL_UARTEx_RxFifoFullCallback() + (++) HAL_UARTEx_TxFifoEmptyCallback() @endverbatim * @{ */ @@ -341,19 +339,19 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) (#) Compared to standard reception services which only consider number of received data elements as reception completion criteria, these functions also consider additional events as triggers for updating reception status to caller : - (+) Detection of inactivity period (RX line has not been active for a given period). - (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + (++) Detection of inactivity period (RX line has not been active for a given period). + (+++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) for 1 frame time, after last received byte. - (++) RX inactivity detected by RTO, i.e. line has been in idle state + (+++) RX inactivity detected by RTO, i.e. line has been in idle state for a programmable time, after last received byte. - (+) Detection that a specific character has been received. + (++) Detection that a specific character has been received. - (#) There are two mode of transfer: - (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + (#) There are two modes of transfer: + (++) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, or till IDLE event occurs. Reception is handled only during function execution. When function exits, no data reception could occur. HAL status and number of actually received data elements, are returned by function after finishing transfer. - (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. + (++) Non-Blocking mode: The reception is performed using Interrupts or DMA. These API's return the HAL status. The end of the data processing will be indicated through the dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. @@ -361,13 +359,13 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. (#) Blocking mode API: - (+) HAL_UARTEx_ReceiveToIdle() + (++) HAL_UARTEx_ReceiveToIdle() (#) Non-Blocking mode API with Interrupt: - (+) HAL_UARTEx_ReceiveToIdle_IT() + (++) HAL_UARTEx_ReceiveToIdle_IT() (#) Non-Blocking mode API with DMA: - (+) HAL_UARTEx_ReceiveToIdle_DMA() + (++) HAL_UARTEx_ReceiveToIdle_DMA() @endverbatim * @{ @@ -992,17 +990,15 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead * to Rx Event callback execution. * @note This function is expected to be called within the user implementation of Rx Event Callback, - * in order to provide the accurate value : - * In Interrupt Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one) - * In DMA Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one). - * In DMA mode, RxEvent callback could be called several times; + * in order to provide the accurate value. + * @note In Interrupt Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received. + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA mode, RxEvent callback could be called several times; * When DMA is configured in Normal Mode, HT event does not stop Reception process; * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; * @param huart UART handle. diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_comp.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_comp.c index 77c2f0ba52..da11a1d9e3 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_comp.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_comp.c @@ -52,6 +52,7 @@ #define IS_LL_COMP_POWER_MODE(__POWER_MODE__) \ (((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED) \ || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED) \ + || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER) \ ) #define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \ diff --git a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_spi.c b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_spi.c index 798eb83441..4407bb6da0 100644 --- a/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_spi.c +++ b/system/Drivers/STM32U0xx_HAL_Driver/Src/stm32u0xx_ll_spi.c @@ -129,7 +129,7 @@ * - SUCCESS: SPI registers are de-initialized * - ERROR: SPI registers are not de-initialized */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx) { ErrorStatus status = ERROR; @@ -178,8 +178,9 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) /** * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. - * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), - * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in SPI configuration registers can only be written when the + * SPI is disabled (SPI_CR1_SPE bit = 0), SPI peripheral should be in disabled state prior + * calling this function. Otherwise, ERROR result will be returned. * @param SPIx SPI Instance * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure * @retval An ErrorStatus enumeration value. (Return always SUCCESS) diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index afc78821f7..ff023be762 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -16,7 +16,7 @@ * STM32L4: 1.13.5 * STM32L5: 1.0.6 * STM32MP1: 1.7.0 - * STM32U0: 1.2.0 + * STM32U0: 1.3.0 * STM32U3: 1.1.0 * STM32U5: 1.6.2 * STM32WB: 1.14.6 From 3cd0a340fd3b67e3df4a15eedcd6b57dbd609a7c Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 22 Sep 2025 14:24:02 +0200 Subject: [PATCH 15/18] system(u0): update STM32U0xx CMSIS Drivers to v1.3.0 Included in STM32CubeU0 FW 1.3.0 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32U0xx/Include/stm32u031xx.h | 4483 +++++++------- .../Device/ST/STM32U0xx/Include/stm32u073xx.h | 4959 ++++++++-------- .../Device/ST/STM32U0xx/Include/stm32u083xx.h | 5145 ++++++++--------- .../Device/ST/STM32U0xx/Include/stm32u0xx.h | 2 +- .../Device/ST/STM32U0xx/Release_Notes.html | 28 +- .../Templates/gcc/linker/STM32U073x8_FLASH.ld | 187 + .../Templates/gcc/linker/STM32U073xB_FLASH.ld | 187 + .../Source/Templates/system_stm32u0xx.c | 4 +- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 9 files changed, 7687 insertions(+), 7310 deletions(-) create mode 100644 system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/linker/STM32U073x8_FLASH.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/linker/STM32U073xB_FLASH.ld diff --git a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u031xx.h b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u031xx.h index 30773e1225..7131a7616f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u031xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u031xx.h @@ -578,7 +578,7 @@ typedef struct { __IO uint32_t CFGR1; /*!< SYSCFG Control register, Address offset: 0x00 */ uint32_t RESERVED0[5]; /*!< Reserved 0x04 --0x14 */ - uint32_t CFGR2; /*!< SYSCFG Class B register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG Class B register, Address offset: 0x18 */ __IO uint32_t SCSR; /*!< SYSCFG Backup Sram Erase Register, Address offset: 0x1C */ __IO uint32_t SKR; /*!< SYSCFG Backup Sram Key Register, Address offset: 0x20 */ __IO uint32_t TSCCR; /*!< SYSCFG TSC Comp Register, Address offset: 0x24 */ @@ -934,34 +934,34 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for ADC_ISR register *******************/ -#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Pos (0UL) #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ -#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Pos (1UL) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ -#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Pos (2UL) #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ -#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Pos (3UL) #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ -#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Pos (4UL) #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ -#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Pos (7UL) #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ -#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Pos (8UL) #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ -#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Pos (9UL) #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ -#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Pos (11UL) #define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ #define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ -#define ADC_ISR_CCRDY_Pos (13U) +#define ADC_ISR_CCRDY_Pos (13UL) #define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ #define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ @@ -969,34 +969,34 @@ typedef struct #define ADC_ISR_EOSEQ (ADC_ISR_EOS) /******************** Bit definition for ADC_IER register *******************/ -#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Pos (0UL) #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ -#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Pos (1UL) #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ -#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Pos (2UL) #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ -#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Pos (3UL) #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ -#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Pos (4UL) #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ -#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Pos (7UL) #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ -#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Pos (8UL) #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ -#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Pos (9UL) #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ -#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Pos (11UL) #define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ #define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ -#define ADC_IER_CCRDYIE_Pos (13U) +#define ADC_IER_CCRDYIE_Pos (13UL) #define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ #define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ @@ -1004,87 +1004,87 @@ typedef struct #define ADC_IER_EOSEQIE (ADC_IER_EOSIE) /******************** Bit definition for ADC_CR register ********************/ -#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Pos (0UL) #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ -#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Pos (1UL) #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ -#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Pos (2UL) #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ -#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Pos (4UL) #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ -#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Pos (28UL) #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ -#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Pos (31UL) #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR1 register *****************/ -#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Pos (0UL) #define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ -#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Pos (1UL) #define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ -#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Pos (2UL) #define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ -#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Pos (3UL) #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ #define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ #define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ -#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Pos (5UL) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ -#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Pos (6UL) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ #define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ #define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ #define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ -#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Pos (10UL) #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ -#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Pos (12UL) #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ -#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Pos (13UL) #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ -#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Pos (14UL) #define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ -#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Pos (15UL) #define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ -#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Pos (16UL) #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ -#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Pos (21UL) #define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ #define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ -#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Pos (22UL) #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ -#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Pos (23UL) #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ -#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Pos (26UL) #define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ #define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ @@ -1097,18 +1097,18 @@ typedef struct #define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) /******************** Bit definition for ADC_CFGR2 register *****************/ -#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Pos (0UL) #define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ -#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Pos (2UL) #define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ #define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ #define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ #define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ -#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Pos (5UL) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ @@ -1116,101 +1116,101 @@ typedef struct #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ -#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Pos (9UL) #define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ -#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Pos (29UL) #define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ -#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Pos (30UL) #define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ #define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_SMPR register ******************/ -#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Pos (0UL) #define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ #define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ #define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ #define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ #define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ -#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Pos (4UL) #define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ #define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ #define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ #define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ #define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ -#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Pos (8UL) #define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */ #define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ -#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Pos (8UL) #define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ #define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ -#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Pos (9UL) #define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ #define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ -#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Pos (10UL) #define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ #define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ -#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Pos (11UL) #define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ #define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ -#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Pos (12UL) #define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ #define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ -#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Pos (13UL) #define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ #define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ -#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Pos (14UL) #define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ #define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ -#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Pos (15UL) #define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ #define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ -#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Pos (16UL) #define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ #define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ -#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Pos (17UL) #define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ #define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ -#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Pos (18UL) #define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ #define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ -#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Pos (19UL) #define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ #define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ -#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Pos (20UL) #define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ #define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ -#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Pos (21UL) #define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ #define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ -#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Pos (22UL) #define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ #define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ -#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Pos (23UL) #define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ #define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ -#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Pos (24UL) #define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ #define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ -#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Pos (25UL) #define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ #define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ -#define ADC_SMPR_SMPSEL18_Pos (26U) +#define ADC_SMPR_SMPSEL18_Pos (26UL) #define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ #define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */ -#define ADC_SMPR_SMPSEL19_Pos (27U) +#define ADC_SMPR_SMPSEL19_Pos (27UL) #define ADC_SMPR_SMPSEL19_Msk (0x1UL << ADC_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ #define ADC_SMPR_SMPSEL19 ADC_SMPR_SMPSEL19_Msk /*!< ADC channel 19 sampling time selection */ /******************** Bit definition for ADC_AWD1TR register *******************/ -#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Pos (0UL) #define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ #define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ #define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ @@ -1226,7 +1226,7 @@ typedef struct #define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ #define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ -#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Pos (16UL) #define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ #define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ @@ -1243,7 +1243,7 @@ typedef struct #define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_AWD2TR register *******************/ -#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Pos (0UL) #define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ #define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ #define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ @@ -1259,7 +1259,7 @@ typedef struct #define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ #define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ -#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Pos (16UL) #define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ #define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ @@ -1276,84 +1276,84 @@ typedef struct #define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_CHSELR register ****************/ -#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Pos (0UL) #define ADC_CHSELR_CHSEL_Msk (0x7FFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFFF */ #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL22_Pos (22U) +#define ADC_CHSELR_CHSEL22_Pos (22UL) #define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00400000 */ #define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 22, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL21_Pos (21U) +#define ADC_CHSELR_CHSEL21_Pos (21UL) #define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00200000 */ #define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 21, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL20_Pos (20U) +#define ADC_CHSELR_CHSEL20_Pos (20UL) #define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00100000 */ #define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 20, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL19_Pos (19U) +#define ADC_CHSELR_CHSEL19_Pos (19UL) #define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00080000 */ #define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 19, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Pos (18UL) #define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Pos (17UL) #define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Pos (16UL) #define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Pos (15UL) #define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Pos (14UL) #define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Pos (13UL) #define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Pos (12UL) #define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Pos (11UL) #define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Pos (10UL) #define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Pos (9UL) #define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Pos (8UL) #define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Pos (7UL) #define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Pos (6UL) #define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Pos (5UL) #define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Pos (4UL) #define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Pos (3UL) #define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Pos (2UL) #define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Pos (1UL) #define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Pos (0UL) #define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Pos (0UL) #define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ #define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ -#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Pos (28UL) #define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ #define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ @@ -1361,7 +1361,7 @@ typedef struct #define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ #define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ -#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Pos (24UL) #define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ #define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ @@ -1369,7 +1369,7 @@ typedef struct #define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ #define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ -#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Pos (20UL) #define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ #define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ @@ -1377,7 +1377,7 @@ typedef struct #define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ #define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ -#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Pos (16UL) #define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ #define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ @@ -1385,7 +1385,7 @@ typedef struct #define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ -#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Pos (12UL) #define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ #define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ @@ -1393,7 +1393,7 @@ typedef struct #define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ #define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ -#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Pos (8UL) #define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ #define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ @@ -1401,7 +1401,7 @@ typedef struct #define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ #define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ -#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Pos (4UL) #define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ #define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ @@ -1409,7 +1409,7 @@ typedef struct #define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ #define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ -#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Pos (0UL) #define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ #define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ @@ -1418,7 +1418,7 @@ typedef struct #define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ /******************** Bit definition for ADC_AWD3TR register *******************/ -#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Pos (0UL) #define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ #define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ #define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ @@ -1434,7 +1434,7 @@ typedef struct #define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ #define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ -#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Pos (16UL) #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ #define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ @@ -1451,7 +1451,7 @@ typedef struct #define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Pos (0UL) #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ #define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ @@ -1472,7 +1472,7 @@ typedef struct #define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_AWD2CR register ****************/ -#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Pos (0UL) #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ @@ -1496,7 +1496,7 @@ typedef struct #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ -#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Pos (0UL) #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ @@ -1520,7 +1520,7 @@ typedef struct #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_CALFACT register ***************/ -#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Pos (0UL) #define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ #define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ @@ -1533,7 +1533,7 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CCR register *******************/ -#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Pos (18UL) #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ @@ -1541,13 +1541,13 @@ typedef struct #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ -#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Pos (22UL) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ -#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Pos (23UL) #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ -#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Pos (24UL) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to VBATEN sensor enable */ @@ -1558,49 +1558,49 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Pos (0UL) #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Pos (0UL) #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Pos (0UL) #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ -#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Pos (3UL) #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ -#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Pos (5UL) #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ -#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Pos (7UL) #define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ #define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ #define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ -#define CRC_CR_RTYPE_IN_Pos (9U) +#define CRC_CR_RTYPE_IN_Pos (9UL) #define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ #define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< Reverse type input */ -#define CRC_CR_RTYPE_OUT_Pos (10U) +#define CRC_CR_RTYPE_OUT_Pos (10UL) #define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ #define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< Reverse type output*/ /******************* Bit definition for CRC_INIT register *******************/ -#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Pos (0UL) #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ /******************* Bit definition for CRC_POL register ********************/ -#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Pos (0UL) #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ /******************************************************************************/ @@ -1609,14 +1609,14 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Pos (0UL) #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -6221,85 +6216,85 @@ typedef struct #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -6308,86 +6303,86 @@ typedef struct #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -6397,279 +6392,279 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for TAMP_CR1 register *****************/ -#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Pos (0UL) #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk -#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Pos (1UL) #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk -#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Pos (2UL) #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Pos (3UL) #define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ #define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Pos (4UL) #define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ #define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Pos (18UL) #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk -#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Pos (19UL) #define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ #define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk -#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Pos (20UL) #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Pos (21UL) #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk /******************** Bits definition for TAMP_CR2 register *****************/ -#define TAMP_CR2_TAMP1POM_Pos (0U) +#define TAMP_CR2_TAMP1POM_Pos (0UL) #define TAMP_CR2_TAMP1POM_Msk (0x1UL << TAMP_CR2_TAMP1POM_Pos) /*!< 0x00000001 */ #define TAMP_CR2_TAMP1POM TAMP_CR2_TAMP1POM_Msk -#define TAMP_CR2_TAMP2POM_Pos (1U) +#define TAMP_CR2_TAMP2POM_Pos (1UL) #define TAMP_CR2_TAMP2POM_Msk (0x1UL << TAMP_CR2_TAMP2POM_Pos) /*!< 0x00000002 */ #define TAMP_CR2_TAMP2POM TAMP_CR2_TAMP2POM_Msk -#define TAMP_CR2_TAMP3POM_Pos (2U) +#define TAMP_CR2_TAMP3POM_Pos (2UL) #define TAMP_CR2_TAMP3POM_Msk (0x1UL << TAMP_CR2_TAMP3POM_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP3POM TAMP_CR2_TAMP3POM_Msk -#define TAMP_CR2_TAMP4POM_Pos (3U) +#define TAMP_CR2_TAMP4POM_Pos (3UL) #define TAMP_CR2_TAMP4POM_Msk (0x1UL << TAMP_CR2_TAMP4POM_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP4POM TAMP_CR2_TAMP4POM_Msk -#define TAMP_CR2_TAMP5POM_Pos (4U) +#define TAMP_CR2_TAMP5POM_Pos (4UL) #define TAMP_CR2_TAMP5POM_Msk (0x1UL << TAMP_CR2_TAMP5POM_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP5POM TAMP_CR2_TAMP5POM_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Pos (16UL) #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Pos (17UL) #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Pos (18UL) #define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ #define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Pos (22UL) #define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00400000 */ #define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk -#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Pos (23UL) #define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Pos (24UL) #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Pos (25UL) #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Pos (26UL) #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Pos (27UL) #define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x04000000 */ #define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Pos (28UL) #define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x04000000 */ #define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk /******************** Bits definition for TAMP_CR3 register *****************/ -#define TAMP_CR3_ITAMP3POM_Pos (2U) +#define TAMP_CR3_ITAMP3POM_Pos (2UL) #define TAMP_CR3_ITAMP3POM_Msk (0x1UL << TAMP_CR3_ITAMP3POM_Pos) /*!< 0x00000004 */ #define TAMP_CR3_ITAMP3POM TAMP_CR3_ITAMP3POM_Msk -#define TAMP_CR3_ITAMP4POM_Pos (3U) +#define TAMP_CR3_ITAMP4POM_Pos (3UL) #define TAMP_CR3_ITAMP4POM_Msk (0x1UL << TAMP_CR3_ITAMP4POM_Pos) /*!< 0x00000008 */ #define TAMP_CR3_ITAMP4POM TAMP_CR3_ITAMP4POM_Msk -#define TAMP_CR3_ITAMP5POM_Pos (4U) +#define TAMP_CR3_ITAMP5POM_Pos (4UL) #define TAMP_CR3_ITAMP5POM_Msk (0x1UL << TAMP_CR3_ITAMP5POM_Pos) /*!< 0x00000010 */ -#define TAMP_CR3_ITAMP5POM TAMP_CR3_ITAMP5NOER_Msk -#define TAMP_CR3_ITAMP6POM_Pos (5U) -#define TAMP_CR3_ITAMP6POM_Msk (0x1UL << TAMP_CR3_ITAMP6tPOM_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP5POM TAMP_CR3_ITAMP5POM_Msk +#define TAMP_CR3_ITAMP6POM_Pos (5UL) +#define TAMP_CR3_ITAMP6POM_Msk (0x1UL << TAMP_CR3_ITAMP6POM_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6POM TAMP_CR3_ITAMP6POM_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ -#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ -#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ -#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ -#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk /******************** Bits definition for TAMP_IER register *****************/ -#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Pos (0UL) #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk -#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Pos (1UL) #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk -#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Pos (2UL) #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk -#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Pos (3UL) #define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk -#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Pos (4UL) #define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk -#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Pos (18UL) #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk -#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Pos (19UL) #define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ #define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk -#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Pos (20UL) #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk -#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Pos (21UL) #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk /******************** Bits definition for TAMP_SR register *****************/ -#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Pos (0UL) #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk -#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Pos (1UL) #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk -#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Pos (2UL) #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk -#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Pos (3UL) #define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk -#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Pos (4UL) #define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk -#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Pos (18UL) #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk -#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Pos (19UL) #define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ #define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk -#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Pos (20UL) #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk -#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Pos (21UL) #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk /******************** Bits definition for TAMP_MISR register ************ *****/ -#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Pos (0UL) #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk -#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Pos (1UL) #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk -#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Pos (2UL) #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk -#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Pos (3UL) #define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk -#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Pos (4UL) #define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk -#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Pos (18UL) #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk -#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Pos (19UL) #define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ #define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk -#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Pos (20UL) #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk -#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Pos (21UL) #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk /******************** Bits definition for TAMP_SCR register *****************/ -#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Pos (0UL) #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk -#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Pos (1UL) #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk -#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Pos (2UL) #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk -#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Pos (3UL) #define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk -#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Pos (4UL) #define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk -#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Pos (18UL) #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk -#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Pos (19UL) #define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ #define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk -#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Pos (20UL) #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk -#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Pos (21UL) #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk /******************** Bits definition for TAMP_BKP0R register ***************/ -#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Pos (0UL) #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP0R TAMP_BKP0R_Msk /******************** Bits definition for TAMP_BKP1R register ****************/ -#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Pos (0UL) #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP1R TAMP_BKP1R_Msk /******************** Bits definition for TAMP_BKP2R register ****************/ -#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Pos (0UL) #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP2R TAMP_BKP2R_Msk /******************** Bits definition for TAMP_BKP3R register ****************/ -#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Pos (0UL) #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP3R TAMP_BKP3R_Msk /******************** Bits definition for TAMP_BKP4R register ****************/ -#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Pos (0UL) #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk /******************** Bits definition for TAMP_BKP5R register ****************/ -#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Pos (0UL) #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP5R TAMP_BKP5R_Msk /******************** Bits definition for TAMP_BKP6R register ****************/ -#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Pos (0UL) #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP6R TAMP_BKP6R_Msk /******************** Bits definition for TAMP_BKP7R register ****************/ -#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Pos (0UL) #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP7R TAMP_BKP7R_Msk /******************** Bits definition for TAMP_BKP8R register ****************/ -#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Pos (0UL) #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP8R TAMP_BKP8R_Msk /******************** Number of backup registers ******************************/ -#define TAMP_BKP_NUMBER_Pos (4U) +#define TAMP_BKP_NUMBER_Pos (4UL) #define TAMP_BKP_NUMBER_Msk (0x1UL << TAMP_BKP_NUMBER_Pos) /*!< 0x00000080 */ #define TAMP_BKP_NUMBER TAMP_BKP_NUMBER_Msk /*!< 9 BKPREG */ @@ -6683,152 +6678,152 @@ typedef struct */ /******************* Bit definition for SPI_CR1 register ********************/ -#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Pos (0UL) #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*! exti[17] */ -#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U) +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0UL) #define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U) +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1UL) #define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U) +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2UL) #define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U) +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3UL) #define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */ #define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC1_Pos (0U) +#define SYSCFG_ITLINE14_SR_TIM1_CC1_Pos (0UL) #define SYSCFG_ITLINE14_SR_TIM1_CC1_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE14_SR_TIM1_CC1 SYSCFG_ITLINE14_SR_TIM1_CC1_Msk /*!< TIM1 CC1 Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC2_Pos (1U) +#define SYSCFG_ITLINE14_SR_TIM1_CC2_Pos (1UL) #define SYSCFG_ITLINE14_SR_TIM1_CC2_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC2_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE14_SR_TIM1_CC2 SYSCFG_ITLINE14_SR_TIM1_CC2_Msk /*!< TIM1 CC2 Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC3_Pos (2U) +#define SYSCFG_ITLINE14_SR_TIM1_CC3_Pos (2UL) #define SYSCFG_ITLINE14_SR_TIM1_CC3_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC3_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE14_SR_TIM1_CC3 SYSCFG_ITLINE14_SR_TIM1_CC3_Msk /*!< TIM1 CC3 Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC4_Pos (3U) +#define SYSCFG_ITLINE14_SR_TIM1_CC4_Pos (3UL) #define SYSCFG_ITLINE14_SR_TIM1_CC4_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC4_Pos) /*!< 0x00000008 */ #define SYSCFG_ITLINE14_SR_TIM1_CC4 SYSCFG_ITLINE14_SR_TIM1_CC4_Msk /*!< TIM1 CC4 Interrupt */ -#define SYSCFG_ITLINE15_SR_TIM2_Pos (0U) +#define SYSCFG_ITLINE15_SR_TIM2_Pos (0UL) #define SYSCFG_ITLINE15_SR_TIM2_Msk (0x1UL << SYSCFG_ITLINE15_SR_TIM2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE15_SR_TIM2 SYSCFG_ITLINE15_SR_TIM2_Msk /*!< TIM2 GLB Interrupt */ -#define SYSCFG_ITLINE16_SR_TIM3_Pos (0U) +#define SYSCFG_ITLINE16_SR_TIM3_Pos (0UL) #define SYSCFG_ITLINE16_SR_TIM3_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE16_SR_TIM3 SYSCFG_ITLINE16_SR_TIM3_Msk /*!< TIM3 GLB Interrupt */ -#define SYSCFG_ITLINE17_SR_TIM6_Pos (0U) +#define SYSCFG_ITLINE17_SR_TIM6_Pos (0UL) #define SYSCFG_ITLINE17_SR_TIM6_Msk (0x1UL << SYSCFG_ITLINE17_SR_TIM6_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE17_SR_TIM6 SYSCFG_ITLINE17_SR_TIM6_Msk /*!< TIM6 GLB Interrupt */ -#define SYSCFG_ITLINE17_SR_DAC_Pos (1U) +#define SYSCFG_ITLINE17_SR_DAC_Pos (1UL) #define SYSCFG_ITLINE17_SR_DAC_Msk (0x1UL << SYSCFG_ITLINE17_SR_DAC_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE17_SR_DAC SYSCFG_ITLINE17_SR_DAC_Msk /*!< DAC Interrupt */ -#define SYSCFG_ITLINE17_SR_LPTIM1_Pos (2U) +#define SYSCFG_ITLINE17_SR_LPTIM1_Pos (2UL) #define SYSCFG_ITLINE17_SR_LPTIM1_Msk (0x1UL << SYSCFG_ITLINE17_SR_LPTIM1_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE17_SR_LPTIM1 SYSCFG_ITLINE17_SR_LPTIM1_Msk /*!< LPTIM1 -> exti[24] Interrupt */ -#define SYSCFG_ITLINE18_SR_TIM7_Pos (0U) +#define SYSCFG_ITLINE18_SR_TIM7_Pos (0UL) #define SYSCFG_ITLINE18_SR_TIM7_Msk (0x1UL << SYSCFG_ITLINE18_SR_TIM7_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE18_SR_TIM7 SYSCFG_ITLINE18_SR_TIM7_Msk /*!< TIM7 GLB Interrupt */ -#define SYSCFG_ITLINE18_SR_LPTIM2_Pos (1U) +#define SYSCFG_ITLINE18_SR_LPTIM2_Pos (1UL) #define SYSCFG_ITLINE18_SR_LPTIM2_Msk (0x1UL << SYSCFG_ITLINE18_SR_LPTIM2_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE18_SR_LPTIM2 SYSCFG_ITLINE18_SR_LPTIM2_Msk /*!< LPTIM2 -> exti[25] Interrupt */ -#define SYSCFG_ITLINE19_SR_TIM15_Pos (0U) +#define SYSCFG_ITLINE19_SR_TIM15_Pos (0UL) #define SYSCFG_ITLINE19_SR_TIM15_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM15_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE19_SR_TIM15 SYSCFG_ITLINE19_SR_TIM15_Msk /*!< TIM15 GLB Interrupt */ -#define SYSCFG_ITLINE20_SR_TIM16_Pos (0U) +#define SYSCFG_ITLINE20_SR_TIM16_Pos (0UL) #define SYSCFG_ITLINE20_SR_TIM16_Msk (0x1UL << SYSCFG_ITLINE20_SR_TIM16_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE20_SR_TIM16 SYSCFG_ITLINE20_SR_TIM16_Msk /*!< TIM16 GLB Interrupt */ -#define SYSCFG_ITLINE21_SR_TSC_MCE_Pos (0U) +#define SYSCFG_ITLINE21_SR_TSC_MCE_Pos (0UL) #define SYSCFG_ITLINE21_SR_TSC_MCE_Msk (0x1UL << SYSCFG_ITLINE21_SR_TSC_MCE_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE21_SR_TSC_MCE SYSCFG_ITLINE21_SR_TSC_MCE_Msk /*!< TSC_MCE Interrupt */ -#define SYSCFG_ITLINE21_SR_TSC_EOA_Pos (1U) +#define SYSCFG_ITLINE21_SR_TSC_EOA_Pos (1UL) #define SYSCFG_ITLINE21_SR_TSC_EOA_Msk (0x1UL << SYSCFG_ITLINE21_SR_TSC_EOA_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE21_SR_TSC_EOA SYSCFG_ITLINE21_SR_TSC_EOA_Msk /*!< TSC_MCE Interrupt */ -#define SYSCFG_ITLINE23_SR_I2C1_Pos (0U) +#define SYSCFG_ITLINE23_SR_I2C1_Pos (0UL) #define SYSCFG_ITLINE23_SR_I2C1_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE23_SR_I2C1 SYSCFG_ITLINE23_SR_I2C1_Msk /*!< I2C1 GLB Interrupt */ -#define SYSCFG_ITLINE24_SR_I2C2_Pos (0U) +#define SYSCFG_ITLINE24_SR_I2C2_Pos (0UL) #define SYSCFG_ITLINE24_SR_I2C2_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE24_SR_I2C2 SYSCFG_ITLINE24_SR_I2C2_Msk /*!< I2C2 GLB Interrupt */ -#define SYSCFG_ITLINE24_SR_I2C4_Pos (1U) +#define SYSCFG_ITLINE24_SR_I2C4_Pos (1UL) #define SYSCFG_ITLINE24_SR_I2C4_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C4_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE24_SR_I2C4 SYSCFG_ITLINE24_SR_I2C4_Msk /*!< I2C3 GLB Interrupt */ -#define SYSCFG_ITLINE24_SR_I2C3_Pos (2U) +#define SYSCFG_ITLINE24_SR_I2C3_Pos (2UL) #define SYSCFG_ITLINE24_SR_I2C3_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C3_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE24_SR_I2C3 SYSCFG_ITLINE24_SR_I2C3_Msk /*!< I2C3 GLB Interrupt -> exti[23]*/ -#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) +#define SYSCFG_ITLINE25_SR_SPI1_Pos (0UL) #define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ -#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U) +#define SYSCFG_ITLINE26_SR_SPI2_Pos (0UL) #define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */ -#define SYSCFG_ITLINE27_SR_USART1_Pos (0U) +#define SYSCFG_ITLINE27_SR_USART1_Pos (0UL) #define SYSCFG_ITLINE27_SR_USART1_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE27_SR_USART1 SYSCFG_ITLINE27_SR_USART1_Msk /*!< USART1 GLB Interrupt */ -#define SYSCFG_ITLINE28_SR_USART2_Pos (0U) +#define SYSCFG_ITLINE28_SR_USART2_Pos (0UL) #define SYSCFG_ITLINE28_SR_USART2_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE28_SR_USART2 SYSCFG_ITLINE28_SR_USART2_Msk /*!< USART2 GLB Interrupt */ -#define SYSCFG_ITLINE28_SR_LPUART2_Pos (1U) +#define SYSCFG_ITLINE28_SR_LPUART2_Pos (1UL) #define SYSCFG_ITLINE28_SR_LPUART2_Msk (0x1UL << SYSCFG_ITLINE28_SR_LPUART2_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE28_SR_LPUART2 SYSCFG_ITLINE28_SR_LPUART2_Msk /*!< LPUART2 GLB Interrupt -> exti[31] */ -#define SYSCFG_ITLINE29_SR_USART3_Pos (0U) +#define SYSCFG_ITLINE29_SR_USART3_Pos (0UL) #define SYSCFG_ITLINE29_SR_USART3_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART3_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE29_SR_USART3 SYSCFG_ITLINE29_SR_USART3_Msk /*!< USART3 GLB Interrupt */ -#define SYSCFG_ITLINE29_SR_LPUART1_Pos (1U) +#define SYSCFG_ITLINE29_SR_LPUART1_Pos (1UL) #define SYSCFG_ITLINE29_SR_LPUART1_Msk (0x1UL << SYSCFG_ITLINE29_SR_LPUART1_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE29_SR_LPUART1 SYSCFG_ITLINE29_SR_LPUART1_Msk /*!< LPUART1 GLB Interrupt -> exti[30] */ -#define SYSCFG_ITLINE30_SR_USART4_Pos (0U) +#define SYSCFG_ITLINE30_SR_USART4_Pos (0UL) #define SYSCFG_ITLINE30_SR_USART4_Msk (0x1UL << SYSCFG_ITLINE30_SR_USART4_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE30_SR_USART4 SYSCFG_ITLINE30_SR_USART4_Msk /*!< USART4 GLB Interrupt */ -#define SYSCFG_ITLINE31_SR_RNG_Pos (0U) +#define SYSCFG_ITLINE31_SR_RNG_Pos (0UL) #define SYSCFG_ITLINE31_SR_RNG_Msk (0x1UL << SYSCFG_ITLINE31_SR_RNG_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE31_SR_RNG SYSCFG_ITLINE31_SR_RNG_Msk /*!< RNG Interrupt */ @@ -7178,92 +7173,92 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Pos (0UL) #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -6849,85 +6844,85 @@ typedef struct #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -6936,86 +6931,86 @@ typedef struct #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -7025,279 +7020,279 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for TAMP_CR1 register *****************/ -#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Pos (0UL) #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk -#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Pos (1UL) #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk -#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Pos (2UL) #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Pos (3UL) #define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ #define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Pos (4UL) #define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ #define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Pos (18UL) #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk -#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Pos (19UL) #define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ #define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk -#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Pos (20UL) #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Pos (21UL) #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk /******************** Bits definition for TAMP_CR2 register *****************/ -#define TAMP_CR2_TAMP1POM_Pos (0U) +#define TAMP_CR2_TAMP1POM_Pos (0UL) #define TAMP_CR2_TAMP1POM_Msk (0x1UL << TAMP_CR2_TAMP1POM_Pos) /*!< 0x00000001 */ #define TAMP_CR2_TAMP1POM TAMP_CR2_TAMP1POM_Msk -#define TAMP_CR2_TAMP2POM_Pos (1U) +#define TAMP_CR2_TAMP2POM_Pos (1UL) #define TAMP_CR2_TAMP2POM_Msk (0x1UL << TAMP_CR2_TAMP2POM_Pos) /*!< 0x00000002 */ #define TAMP_CR2_TAMP2POM TAMP_CR2_TAMP2POM_Msk -#define TAMP_CR2_TAMP3POM_Pos (2U) +#define TAMP_CR2_TAMP3POM_Pos (2UL) #define TAMP_CR2_TAMP3POM_Msk (0x1UL << TAMP_CR2_TAMP3POM_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP3POM TAMP_CR2_TAMP3POM_Msk -#define TAMP_CR2_TAMP4POM_Pos (3U) +#define TAMP_CR2_TAMP4POM_Pos (3UL) #define TAMP_CR2_TAMP4POM_Msk (0x1UL << TAMP_CR2_TAMP4POM_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP4POM TAMP_CR2_TAMP4POM_Msk -#define TAMP_CR2_TAMP5POM_Pos (4U) +#define TAMP_CR2_TAMP5POM_Pos (4UL) #define TAMP_CR2_TAMP5POM_Msk (0x1UL << TAMP_CR2_TAMP5POM_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP5POM TAMP_CR2_TAMP5POM_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Pos (16UL) #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Pos (17UL) #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Pos (18UL) #define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ #define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Pos (22UL) #define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00400000 */ #define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk -#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Pos (23UL) #define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Pos (24UL) #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Pos (25UL) #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Pos (26UL) #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Pos (27UL) #define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x04000000 */ #define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Pos (28UL) #define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x04000000 */ #define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk /******************** Bits definition for TAMP_CR3 register *****************/ -#define TAMP_CR3_ITAMP3POM_Pos (2U) +#define TAMP_CR3_ITAMP3POM_Pos (2UL) #define TAMP_CR3_ITAMP3POM_Msk (0x1UL << TAMP_CR3_ITAMP3POM_Pos) /*!< 0x00000004 */ #define TAMP_CR3_ITAMP3POM TAMP_CR3_ITAMP3POM_Msk -#define TAMP_CR3_ITAMP4POM_Pos (3U) +#define TAMP_CR3_ITAMP4POM_Pos (3UL) #define TAMP_CR3_ITAMP4POM_Msk (0x1UL << TAMP_CR3_ITAMP4POM_Pos) /*!< 0x00000008 */ #define TAMP_CR3_ITAMP4POM TAMP_CR3_ITAMP4POM_Msk -#define TAMP_CR3_ITAMP5POM_Pos (4U) +#define TAMP_CR3_ITAMP5POM_Pos (4UL) #define TAMP_CR3_ITAMP5POM_Msk (0x1UL << TAMP_CR3_ITAMP5POM_Pos) /*!< 0x00000010 */ -#define TAMP_CR3_ITAMP5POM TAMP_CR3_ITAMP5NOER_Msk -#define TAMP_CR3_ITAMP6POM_Pos (5U) -#define TAMP_CR3_ITAMP6POM_Msk (0x1UL << TAMP_CR3_ITAMP6tPOM_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP5POM TAMP_CR3_ITAMP5POM_Msk +#define TAMP_CR3_ITAMP6POM_Pos (5UL) +#define TAMP_CR3_ITAMP6POM_Msk (0x1UL << TAMP_CR3_ITAMP6POM_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6POM TAMP_CR3_ITAMP6POM_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ -#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ -#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ -#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ -#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk /******************** Bits definition for TAMP_IER register *****************/ -#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Pos (0UL) #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk -#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Pos (1UL) #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk -#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Pos (2UL) #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk -#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Pos (3UL) #define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk -#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Pos (4UL) #define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk -#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Pos (18UL) #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk -#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Pos (19UL) #define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ #define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk -#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Pos (20UL) #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk -#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Pos (21UL) #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk /******************** Bits definition for TAMP_SR register *****************/ -#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Pos (0UL) #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk -#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Pos (1UL) #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk -#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Pos (2UL) #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk -#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Pos (3UL) #define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk -#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Pos (4UL) #define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk -#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Pos (18UL) #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk -#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Pos (19UL) #define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ #define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk -#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Pos (20UL) #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk -#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Pos (21UL) #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk /******************** Bits definition for TAMP_MISR register ************ *****/ -#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Pos (0UL) #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk -#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Pos (1UL) #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk -#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Pos (2UL) #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk -#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Pos (3UL) #define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk -#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Pos (4UL) #define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk -#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Pos (18UL) #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk -#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Pos (19UL) #define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ #define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk -#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Pos (20UL) #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk -#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Pos (21UL) #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk /******************** Bits definition for TAMP_SCR register *****************/ -#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Pos (0UL) #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk -#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Pos (1UL) #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk -#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Pos (2UL) #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk -#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Pos (3UL) #define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk -#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Pos (4UL) #define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk -#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Pos (18UL) #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk -#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Pos (19UL) #define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ #define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk -#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Pos (20UL) #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk -#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Pos (21UL) #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk /******************** Bits definition for TAMP_BKP0R register ***************/ -#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Pos (0UL) #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP0R TAMP_BKP0R_Msk /******************** Bits definition for TAMP_BKP1R register ****************/ -#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Pos (0UL) #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP1R TAMP_BKP1R_Msk /******************** Bits definition for TAMP_BKP2R register ****************/ -#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Pos (0UL) #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP2R TAMP_BKP2R_Msk /******************** Bits definition for TAMP_BKP3R register ****************/ -#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Pos (0UL) #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP3R TAMP_BKP3R_Msk /******************** Bits definition for TAMP_BKP4R register ****************/ -#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Pos (0UL) #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk /******************** Bits definition for TAMP_BKP5R register ****************/ -#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Pos (0UL) #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP5R TAMP_BKP5R_Msk /******************** Bits definition for TAMP_BKP6R register ****************/ -#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Pos (0UL) #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP6R TAMP_BKP6R_Msk /******************** Bits definition for TAMP_BKP7R register ****************/ -#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Pos (0UL) #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP7R TAMP_BKP7R_Msk /******************** Bits definition for TAMP_BKP8R register ****************/ -#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Pos (0UL) #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP8R TAMP_BKP8R_Msk /******************** Number of backup registers ******************************/ -#define TAMP_BKP_NUMBER_Pos (4U) +#define TAMP_BKP_NUMBER_Pos (4UL) #define TAMP_BKP_NUMBER_Msk (0x1UL << TAMP_BKP_NUMBER_Pos) /*!< 0x00000080 */ #define TAMP_BKP_NUMBER TAMP_BKP_NUMBER_Msk /*!< 9 BKPREG */ @@ -7311,152 +7306,152 @@ typedef struct */ /******************* Bit definition for SPI_CR1 register ********************/ -#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Pos (0UL) #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*! exti[17] */ -#define SYSCFG_ITLINE12_SR_COMP2_Pos (2U) +#define SYSCFG_ITLINE12_SR_COMP2_Pos (2UL) #define SYSCFG_ITLINE12_SR_COMP2_Msk (0x1UL << SYSCFG_ITLINE12_SR_COMP2_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE12_SR_COMP2 SYSCFG_ITLINE12_SR_COMP2_Msk /*!< COMP2 Interrupt -> exti[18] */ -#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U) +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0UL) #define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U) +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1UL) #define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U) +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2UL) #define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U) +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3UL) #define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */ #define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC1_Pos (0U) +#define SYSCFG_ITLINE14_SR_TIM1_CC1_Pos (0UL) #define SYSCFG_ITLINE14_SR_TIM1_CC1_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE14_SR_TIM1_CC1 SYSCFG_ITLINE14_SR_TIM1_CC1_Msk /*!< TIM1 CC1 Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC2_Pos (1U) +#define SYSCFG_ITLINE14_SR_TIM1_CC2_Pos (1UL) #define SYSCFG_ITLINE14_SR_TIM1_CC2_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC2_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE14_SR_TIM1_CC2 SYSCFG_ITLINE14_SR_TIM1_CC2_Msk /*!< TIM1 CC2 Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC3_Pos (2U) +#define SYSCFG_ITLINE14_SR_TIM1_CC3_Pos (2UL) #define SYSCFG_ITLINE14_SR_TIM1_CC3_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC3_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE14_SR_TIM1_CC3 SYSCFG_ITLINE14_SR_TIM1_CC3_Msk /*!< TIM1 CC3 Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC4_Pos (3U) +#define SYSCFG_ITLINE14_SR_TIM1_CC4_Pos (3UL) #define SYSCFG_ITLINE14_SR_TIM1_CC4_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC4_Pos) /*!< 0x00000008 */ #define SYSCFG_ITLINE14_SR_TIM1_CC4 SYSCFG_ITLINE14_SR_TIM1_CC4_Msk /*!< TIM1 CC4 Interrupt */ -#define SYSCFG_ITLINE15_SR_TIM2_Pos (0U) +#define SYSCFG_ITLINE15_SR_TIM2_Pos (0UL) #define SYSCFG_ITLINE15_SR_TIM2_Msk (0x1UL << SYSCFG_ITLINE15_SR_TIM2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE15_SR_TIM2 SYSCFG_ITLINE15_SR_TIM2_Msk /*!< TIM2 GLB Interrupt */ -#define SYSCFG_ITLINE16_SR_TIM3_Pos (0U) +#define SYSCFG_ITLINE16_SR_TIM3_Pos (0UL) #define SYSCFG_ITLINE16_SR_TIM3_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE16_SR_TIM3 SYSCFG_ITLINE16_SR_TIM3_Msk /*!< TIM3 GLB Interrupt */ -#define SYSCFG_ITLINE17_SR_TIM6_Pos (0U) +#define SYSCFG_ITLINE17_SR_TIM6_Pos (0UL) #define SYSCFG_ITLINE17_SR_TIM6_Msk (0x1UL << SYSCFG_ITLINE17_SR_TIM6_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE17_SR_TIM6 SYSCFG_ITLINE17_SR_TIM6_Msk /*!< TIM6 GLB Interrupt */ -#define SYSCFG_ITLINE17_SR_DAC_Pos (1U) +#define SYSCFG_ITLINE17_SR_DAC_Pos (1UL) #define SYSCFG_ITLINE17_SR_DAC_Msk (0x1UL << SYSCFG_ITLINE17_SR_DAC_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE17_SR_DAC SYSCFG_ITLINE17_SR_DAC_Msk /*!< DAC Interrupt */ -#define SYSCFG_ITLINE17_SR_LPTIM1_Pos (2U) +#define SYSCFG_ITLINE17_SR_LPTIM1_Pos (2UL) #define SYSCFG_ITLINE17_SR_LPTIM1_Msk (0x1UL << SYSCFG_ITLINE17_SR_LPTIM1_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE17_SR_LPTIM1 SYSCFG_ITLINE17_SR_LPTIM1_Msk /*!< LPTIM1 -> exti[24] Interrupt */ -#define SYSCFG_ITLINE18_SR_TIM7_Pos (0U) +#define SYSCFG_ITLINE18_SR_TIM7_Pos (0UL) #define SYSCFG_ITLINE18_SR_TIM7_Msk (0x1UL << SYSCFG_ITLINE18_SR_TIM7_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE18_SR_TIM7 SYSCFG_ITLINE18_SR_TIM7_Msk /*!< TIM7 GLB Interrupt */ -#define SYSCFG_ITLINE18_SR_LPTIM2_Pos (1U) +#define SYSCFG_ITLINE18_SR_LPTIM2_Pos (1UL) #define SYSCFG_ITLINE18_SR_LPTIM2_Msk (0x1UL << SYSCFG_ITLINE18_SR_LPTIM2_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE18_SR_LPTIM2 SYSCFG_ITLINE18_SR_LPTIM2_Msk /*!< LPTIM2 -> exti[25] Interrupt */ -#define SYSCFG_ITLINE19_SR_TIM15_Pos (0U) +#define SYSCFG_ITLINE19_SR_TIM15_Pos (0UL) #define SYSCFG_ITLINE19_SR_TIM15_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM15_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE19_SR_TIM15 SYSCFG_ITLINE19_SR_TIM15_Msk /*!< TIM15 GLB Interrupt */ -#define SYSCFG_ITLINE19_SR_LPTIM3_Pos (1U) +#define SYSCFG_ITLINE19_SR_LPTIM3_Pos (1UL) #define SYSCFG_ITLINE19_SR_LPTIM3_Msk (0x1UL << SYSCFG_ITLINE19_SR_LPTIM3_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE19_SR_LPTIM3 SYSCFG_ITLINE19_SR_LPTIM3_Msk /*!< LPTIM3 GLB Interrupt -> exti [26]*/ -#define SYSCFG_ITLINE20_SR_TIM16_Pos (0U) +#define SYSCFG_ITLINE20_SR_TIM16_Pos (0UL) #define SYSCFG_ITLINE20_SR_TIM16_Msk (0x1UL << SYSCFG_ITLINE20_SR_TIM16_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE20_SR_TIM16 SYSCFG_ITLINE20_SR_TIM16_Msk /*!< TIM16 GLB Interrupt */ -#define SYSCFG_ITLINE21_SR_TSC_MCE_Pos (0U) +#define SYSCFG_ITLINE21_SR_TSC_MCE_Pos (0UL) #define SYSCFG_ITLINE21_SR_TSC_MCE_Msk (0x1UL << SYSCFG_ITLINE21_SR_TSC_MCE_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE21_SR_TSC_MCE SYSCFG_ITLINE21_SR_TSC_MCE_Msk /*!< TSC_MCE Interrupt */ -#define SYSCFG_ITLINE21_SR_TSC_EOA_Pos (1U) +#define SYSCFG_ITLINE21_SR_TSC_EOA_Pos (1UL) #define SYSCFG_ITLINE21_SR_TSC_EOA_Msk (0x1UL << SYSCFG_ITLINE21_SR_TSC_EOA_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE21_SR_TSC_EOA SYSCFG_ITLINE21_SR_TSC_EOA_Msk /*!< TSC_MCE Interrupt */ -#define SYSCFG_ITLINE22_SR_LCD_Pos (0U) +#define SYSCFG_ITLINE22_SR_LCD_Pos (0UL) #define SYSCFG_ITLINE22_SR_LCD_Msk (0x1UL << SYSCFG_ITLINE22_SR_LCD_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE22_SR_LCD SYSCFG_ITLINE22_SR_LCD_Msk /*!< LCD GLB Interrupt */ -#define SYSCFG_ITLINE23_SR_I2C1_Pos (0U) +#define SYSCFG_ITLINE23_SR_I2C1_Pos (0UL) #define SYSCFG_ITLINE23_SR_I2C1_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE23_SR_I2C1 SYSCFG_ITLINE23_SR_I2C1_Msk /*!< I2C1 GLB Interrupt */ -#define SYSCFG_ITLINE24_SR_I2C2_Pos (0U) +#define SYSCFG_ITLINE24_SR_I2C2_Pos (0UL) #define SYSCFG_ITLINE24_SR_I2C2_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE24_SR_I2C2 SYSCFG_ITLINE24_SR_I2C2_Msk /*!< I2C2 GLB Interrupt */ -#define SYSCFG_ITLINE24_SR_I2C4_Pos (1U) +#define SYSCFG_ITLINE24_SR_I2C4_Pos (1UL) #define SYSCFG_ITLINE24_SR_I2C4_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C4_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE24_SR_I2C4 SYSCFG_ITLINE24_SR_I2C4_Msk /*!< I2C3 GLB Interrupt */ -#define SYSCFG_ITLINE24_SR_I2C3_Pos (2U) +#define SYSCFG_ITLINE24_SR_I2C3_Pos (2UL) #define SYSCFG_ITLINE24_SR_I2C3_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C3_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE24_SR_I2C3 SYSCFG_ITLINE24_SR_I2C3_Msk /*!< I2C3 GLB Interrupt -> exti[23]*/ -#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) +#define SYSCFG_ITLINE25_SR_SPI1_Pos (0UL) #define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ -#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U) +#define SYSCFG_ITLINE26_SR_SPI2_Pos (0UL) #define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */ -#define SYSCFG_ITLINE26_SR_SPI3_Pos (1U) +#define SYSCFG_ITLINE26_SR_SPI3_Pos (1UL) #define SYSCFG_ITLINE26_SR_SPI3_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI3_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE26_SR_SPI3 SYSCFG_ITLINE26_SR_SPI3_Msk /*!< SPI3 Interrupt */ -#define SYSCFG_ITLINE27_SR_USART1_Pos (0U) +#define SYSCFG_ITLINE27_SR_USART1_Pos (0UL) #define SYSCFG_ITLINE27_SR_USART1_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE27_SR_USART1 SYSCFG_ITLINE27_SR_USART1_Msk /*!< USART1 GLB Interrupt */ -#define SYSCFG_ITLINE28_SR_USART2_Pos (0U) +#define SYSCFG_ITLINE28_SR_USART2_Pos (0UL) #define SYSCFG_ITLINE28_SR_USART2_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE28_SR_USART2 SYSCFG_ITLINE28_SR_USART2_Msk /*!< USART2 GLB Interrupt */ -#define SYSCFG_ITLINE28_SR_LPUART2_Pos (1U) +#define SYSCFG_ITLINE28_SR_LPUART2_Pos (1UL) #define SYSCFG_ITLINE28_SR_LPUART2_Msk (0x1UL << SYSCFG_ITLINE28_SR_LPUART2_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE28_SR_LPUART2 SYSCFG_ITLINE28_SR_LPUART2_Msk /*!< LPUART2 GLB Interrupt -> exti[31] */ -#define SYSCFG_ITLINE29_SR_USART3_Pos (0U) +#define SYSCFG_ITLINE29_SR_USART3_Pos (0UL) #define SYSCFG_ITLINE29_SR_USART3_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART3_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE29_SR_USART3 SYSCFG_ITLINE29_SR_USART3_Msk /*!< USART3 GLB Interrupt */ -#define SYSCFG_ITLINE29_SR_LPUART1_Pos (1U) +#define SYSCFG_ITLINE29_SR_LPUART1_Pos (1UL) #define SYSCFG_ITLINE29_SR_LPUART1_Msk (0x1UL << SYSCFG_ITLINE29_SR_LPUART1_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE29_SR_LPUART1 SYSCFG_ITLINE29_SR_LPUART1_Msk /*!< LPUART1 GLB Interrupt -> exti[30] */ -#define SYSCFG_ITLINE30_SR_USART4_Pos (0U) +#define SYSCFG_ITLINE30_SR_USART4_Pos (0UL) #define SYSCFG_ITLINE30_SR_USART4_Msk (0x1UL << SYSCFG_ITLINE30_SR_USART4_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE30_SR_USART4 SYSCFG_ITLINE30_SR_USART4_Msk /*!< USART4 GLB Interrupt */ -#define SYSCFG_ITLINE30_SR_LPUART3_Pos (1U) +#define SYSCFG_ITLINE30_SR_LPUART3_Pos (1UL) #define SYSCFG_ITLINE30_SR_LPUART3_Msk (0x1UL << SYSCFG_ITLINE30_SR_LPUART3_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE30_SR_LPUART3 SYSCFG_ITLINE30_SR_LPUART3_Msk /*!< LPUART3 GLB Interrupt */ -#define SYSCFG_ITLINE31_SR_RNG_Pos (0U) +#define SYSCFG_ITLINE31_SR_RNG_Pos (0UL) #define SYSCFG_ITLINE31_SR_RNG_Msk (0x1UL << SYSCFG_ITLINE31_SR_RNG_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE31_SR_RNG SYSCFG_ITLINE31_SR_RNG_Msk /*!< RNG Interrupt */ @@ -7845,92 +7840,92 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Pos (0UL) #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -7116,85 +7111,85 @@ typedef struct #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -7203,86 +7198,86 @@ typedef struct #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -7292,279 +7287,279 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for TAMP_CR1 register *****************/ -#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Pos (0UL) #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk -#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Pos (1UL) #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk -#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Pos (2UL) #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Pos (3UL) #define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ #define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Pos (4UL) #define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ #define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Pos (18UL) #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk -#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Pos (19UL) #define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ #define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk -#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Pos (20UL) #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Pos (21UL) #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk /******************** Bits definition for TAMP_CR2 register *****************/ -#define TAMP_CR2_TAMP1POM_Pos (0U) +#define TAMP_CR2_TAMP1POM_Pos (0UL) #define TAMP_CR2_TAMP1POM_Msk (0x1UL << TAMP_CR2_TAMP1POM_Pos) /*!< 0x00000001 */ #define TAMP_CR2_TAMP1POM TAMP_CR2_TAMP1POM_Msk -#define TAMP_CR2_TAMP2POM_Pos (1U) +#define TAMP_CR2_TAMP2POM_Pos (1UL) #define TAMP_CR2_TAMP2POM_Msk (0x1UL << TAMP_CR2_TAMP2POM_Pos) /*!< 0x00000002 */ #define TAMP_CR2_TAMP2POM TAMP_CR2_TAMP2POM_Msk -#define TAMP_CR2_TAMP3POM_Pos (2U) +#define TAMP_CR2_TAMP3POM_Pos (2UL) #define TAMP_CR2_TAMP3POM_Msk (0x1UL << TAMP_CR2_TAMP3POM_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP3POM TAMP_CR2_TAMP3POM_Msk -#define TAMP_CR2_TAMP4POM_Pos (3U) +#define TAMP_CR2_TAMP4POM_Pos (3UL) #define TAMP_CR2_TAMP4POM_Msk (0x1UL << TAMP_CR2_TAMP4POM_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP4POM TAMP_CR2_TAMP4POM_Msk -#define TAMP_CR2_TAMP5POM_Pos (4U) +#define TAMP_CR2_TAMP5POM_Pos (4UL) #define TAMP_CR2_TAMP5POM_Msk (0x1UL << TAMP_CR2_TAMP5POM_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP5POM TAMP_CR2_TAMP5POM_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Pos (16UL) #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Pos (17UL) #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Pos (18UL) #define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ #define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Pos (22UL) #define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00400000 */ #define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk -#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Pos (23UL) #define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Pos (24UL) #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Pos (25UL) #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Pos (26UL) #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Pos (27UL) #define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x04000000 */ #define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Pos (28UL) #define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x04000000 */ #define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk /******************** Bits definition for TAMP_CR3 register *****************/ -#define TAMP_CR3_ITAMP3POM_Pos (2U) +#define TAMP_CR3_ITAMP3POM_Pos (2UL) #define TAMP_CR3_ITAMP3POM_Msk (0x1UL << TAMP_CR3_ITAMP3POM_Pos) /*!< 0x00000004 */ #define TAMP_CR3_ITAMP3POM TAMP_CR3_ITAMP3POM_Msk -#define TAMP_CR3_ITAMP4POM_Pos (3U) +#define TAMP_CR3_ITAMP4POM_Pos (3UL) #define TAMP_CR3_ITAMP4POM_Msk (0x1UL << TAMP_CR3_ITAMP4POM_Pos) /*!< 0x00000008 */ #define TAMP_CR3_ITAMP4POM TAMP_CR3_ITAMP4POM_Msk -#define TAMP_CR3_ITAMP5POM_Pos (4U) +#define TAMP_CR3_ITAMP5POM_Pos (4UL) #define TAMP_CR3_ITAMP5POM_Msk (0x1UL << TAMP_CR3_ITAMP5POM_Pos) /*!< 0x00000010 */ -#define TAMP_CR3_ITAMP5POM TAMP_CR3_ITAMP5NOER_Msk -#define TAMP_CR3_ITAMP6POM_Pos (5U) -#define TAMP_CR3_ITAMP6POM_Msk (0x1UL << TAMP_CR3_ITAMP6tPOM_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP5POM TAMP_CR3_ITAMP5POM_Msk +#define TAMP_CR3_ITAMP6POM_Pos (5UL) +#define TAMP_CR3_ITAMP6POM_Msk (0x1UL << TAMP_CR3_ITAMP6POM_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6POM TAMP_CR3_ITAMP6POM_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ -#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ -#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ -#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ -#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk /******************** Bits definition for TAMP_IER register *****************/ -#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Pos (0UL) #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk -#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Pos (1UL) #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk -#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Pos (2UL) #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk -#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Pos (3UL) #define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk -#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Pos (4UL) #define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk -#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Pos (18UL) #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk -#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Pos (19UL) #define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ #define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk -#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Pos (20UL) #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk -#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Pos (21UL) #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk /******************** Bits definition for TAMP_SR register *****************/ -#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Pos (0UL) #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk -#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Pos (1UL) #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk -#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Pos (2UL) #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk -#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Pos (3UL) #define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk -#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Pos (4UL) #define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk -#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Pos (18UL) #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk -#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Pos (19UL) #define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ #define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk -#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Pos (20UL) #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk -#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Pos (21UL) #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk /******************** Bits definition for TAMP_MISR register ************ *****/ -#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Pos (0UL) #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk -#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Pos (1UL) #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk -#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Pos (2UL) #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk -#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Pos (3UL) #define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk -#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Pos (4UL) #define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk -#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Pos (18UL) #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk -#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Pos (19UL) #define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ #define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk -#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Pos (20UL) #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk -#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Pos (21UL) #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk /******************** Bits definition for TAMP_SCR register *****************/ -#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Pos (0UL) #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk -#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Pos (1UL) #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk -#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Pos (2UL) #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk -#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Pos (3UL) #define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk -#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Pos (4UL) #define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk -#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Pos (18UL) #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk -#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Pos (19UL) #define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ #define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk -#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Pos (20UL) #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk -#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Pos (21UL) #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk /******************** Bits definition for TAMP_BKP0R register ***************/ -#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Pos (0UL) #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP0R TAMP_BKP0R_Msk /******************** Bits definition for TAMP_BKP1R register ****************/ -#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Pos (0UL) #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP1R TAMP_BKP1R_Msk /******************** Bits definition for TAMP_BKP2R register ****************/ -#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Pos (0UL) #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP2R TAMP_BKP2R_Msk /******************** Bits definition for TAMP_BKP3R register ****************/ -#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Pos (0UL) #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP3R TAMP_BKP3R_Msk /******************** Bits definition for TAMP_BKP4R register ****************/ -#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Pos (0UL) #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk /******************** Bits definition for TAMP_BKP5R register ****************/ -#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Pos (0UL) #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP5R TAMP_BKP5R_Msk /******************** Bits definition for TAMP_BKP6R register ****************/ -#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Pos (0UL) #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP6R TAMP_BKP6R_Msk /******************** Bits definition for TAMP_BKP7R register ****************/ -#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Pos (0UL) #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP7R TAMP_BKP7R_Msk /******************** Bits definition for TAMP_BKP8R register ****************/ -#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Pos (0UL) #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP8R TAMP_BKP8R_Msk /******************** Number of backup registers ******************************/ -#define TAMP_BKP_NUMBER_Pos (4U) +#define TAMP_BKP_NUMBER_Pos (4UL) #define TAMP_BKP_NUMBER_Msk (0x1UL << TAMP_BKP_NUMBER_Pos) /*!< 0x00000080 */ #define TAMP_BKP_NUMBER TAMP_BKP_NUMBER_Msk /*!< 9 BKPREG */ @@ -7578,152 +7573,152 @@ typedef struct */ /******************* Bit definition for SPI_CR1 register ********************/ -#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Pos (0UL) #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*! exti[17] */ -#define SYSCFG_ITLINE12_SR_COMP2_Pos (2U) +#define SYSCFG_ITLINE12_SR_COMP2_Pos (2UL) #define SYSCFG_ITLINE12_SR_COMP2_Msk (0x1UL << SYSCFG_ITLINE12_SR_COMP2_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE12_SR_COMP2 SYSCFG_ITLINE12_SR_COMP2_Msk /*!< COMP2 Interrupt -> exti[18] */ -#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U) +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0UL) #define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U) +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1UL) #define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U) +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2UL) #define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U) +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3UL) #define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */ #define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC1_Pos (0U) +#define SYSCFG_ITLINE14_SR_TIM1_CC1_Pos (0UL) #define SYSCFG_ITLINE14_SR_TIM1_CC1_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE14_SR_TIM1_CC1 SYSCFG_ITLINE14_SR_TIM1_CC1_Msk /*!< TIM1 CC1 Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC2_Pos (1U) +#define SYSCFG_ITLINE14_SR_TIM1_CC2_Pos (1UL) #define SYSCFG_ITLINE14_SR_TIM1_CC2_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC2_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE14_SR_TIM1_CC2 SYSCFG_ITLINE14_SR_TIM1_CC2_Msk /*!< TIM1 CC2 Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC3_Pos (2U) +#define SYSCFG_ITLINE14_SR_TIM1_CC3_Pos (2UL) #define SYSCFG_ITLINE14_SR_TIM1_CC3_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC3_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE14_SR_TIM1_CC3 SYSCFG_ITLINE14_SR_TIM1_CC3_Msk /*!< TIM1 CC3 Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC4_Pos (3U) +#define SYSCFG_ITLINE14_SR_TIM1_CC4_Pos (3UL) #define SYSCFG_ITLINE14_SR_TIM1_CC4_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC4_Pos) /*!< 0x00000008 */ #define SYSCFG_ITLINE14_SR_TIM1_CC4 SYSCFG_ITLINE14_SR_TIM1_CC4_Msk /*!< TIM1 CC4 Interrupt */ -#define SYSCFG_ITLINE15_SR_TIM2_Pos (0U) +#define SYSCFG_ITLINE15_SR_TIM2_Pos (0UL) #define SYSCFG_ITLINE15_SR_TIM2_Msk (0x1UL << SYSCFG_ITLINE15_SR_TIM2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE15_SR_TIM2 SYSCFG_ITLINE15_SR_TIM2_Msk /*!< TIM2 GLB Interrupt */ -#define SYSCFG_ITLINE16_SR_TIM3_Pos (0U) +#define SYSCFG_ITLINE16_SR_TIM3_Pos (0UL) #define SYSCFG_ITLINE16_SR_TIM3_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE16_SR_TIM3 SYSCFG_ITLINE16_SR_TIM3_Msk /*!< TIM3 GLB Interrupt */ -#define SYSCFG_ITLINE17_SR_TIM6_Pos (0U) +#define SYSCFG_ITLINE17_SR_TIM6_Pos (0UL) #define SYSCFG_ITLINE17_SR_TIM6_Msk (0x1UL << SYSCFG_ITLINE17_SR_TIM6_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE17_SR_TIM6 SYSCFG_ITLINE17_SR_TIM6_Msk /*!< TIM6 GLB Interrupt */ -#define SYSCFG_ITLINE17_SR_DAC_Pos (1U) +#define SYSCFG_ITLINE17_SR_DAC_Pos (1UL) #define SYSCFG_ITLINE17_SR_DAC_Msk (0x1UL << SYSCFG_ITLINE17_SR_DAC_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE17_SR_DAC SYSCFG_ITLINE17_SR_DAC_Msk /*!< DAC Interrupt */ -#define SYSCFG_ITLINE17_SR_LPTIM1_Pos (2U) +#define SYSCFG_ITLINE17_SR_LPTIM1_Pos (2UL) #define SYSCFG_ITLINE17_SR_LPTIM1_Msk (0x1UL << SYSCFG_ITLINE17_SR_LPTIM1_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE17_SR_LPTIM1 SYSCFG_ITLINE17_SR_LPTIM1_Msk /*!< LPTIM1 -> exti[24] Interrupt */ -#define SYSCFG_ITLINE18_SR_TIM7_Pos (0U) +#define SYSCFG_ITLINE18_SR_TIM7_Pos (0UL) #define SYSCFG_ITLINE18_SR_TIM7_Msk (0x1UL << SYSCFG_ITLINE18_SR_TIM7_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE18_SR_TIM7 SYSCFG_ITLINE18_SR_TIM7_Msk /*!< TIM7 GLB Interrupt */ -#define SYSCFG_ITLINE18_SR_LPTIM2_Pos (1U) +#define SYSCFG_ITLINE18_SR_LPTIM2_Pos (1UL) #define SYSCFG_ITLINE18_SR_LPTIM2_Msk (0x1UL << SYSCFG_ITLINE18_SR_LPTIM2_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE18_SR_LPTIM2 SYSCFG_ITLINE18_SR_LPTIM2_Msk /*!< LPTIM2 -> exti[25] Interrupt */ -#define SYSCFG_ITLINE19_SR_TIM15_Pos (0U) +#define SYSCFG_ITLINE19_SR_TIM15_Pos (0UL) #define SYSCFG_ITLINE19_SR_TIM15_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM15_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE19_SR_TIM15 SYSCFG_ITLINE19_SR_TIM15_Msk /*!< TIM15 GLB Interrupt */ -#define SYSCFG_ITLINE19_SR_LPTIM3_Pos (1U) +#define SYSCFG_ITLINE19_SR_LPTIM3_Pos (1UL) #define SYSCFG_ITLINE19_SR_LPTIM3_Msk (0x1UL << SYSCFG_ITLINE19_SR_LPTIM3_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE19_SR_LPTIM3 SYSCFG_ITLINE19_SR_LPTIM3_Msk /*!< LPTIM3 GLB Interrupt -> exti [26]*/ -#define SYSCFG_ITLINE20_SR_TIM16_Pos (0U) +#define SYSCFG_ITLINE20_SR_TIM16_Pos (0UL) #define SYSCFG_ITLINE20_SR_TIM16_Msk (0x1UL << SYSCFG_ITLINE20_SR_TIM16_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE20_SR_TIM16 SYSCFG_ITLINE20_SR_TIM16_Msk /*!< TIM16 GLB Interrupt */ -#define SYSCFG_ITLINE21_SR_TSC_MCE_Pos (0U) +#define SYSCFG_ITLINE21_SR_TSC_MCE_Pos (0UL) #define SYSCFG_ITLINE21_SR_TSC_MCE_Msk (0x1UL << SYSCFG_ITLINE21_SR_TSC_MCE_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE21_SR_TSC_MCE SYSCFG_ITLINE21_SR_TSC_MCE_Msk /*!< TSC_MCE Interrupt */ -#define SYSCFG_ITLINE21_SR_TSC_EOA_Pos (1U) +#define SYSCFG_ITLINE21_SR_TSC_EOA_Pos (1UL) #define SYSCFG_ITLINE21_SR_TSC_EOA_Msk (0x1UL << SYSCFG_ITLINE21_SR_TSC_EOA_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE21_SR_TSC_EOA SYSCFG_ITLINE21_SR_TSC_EOA_Msk /*!< TSC_MCE Interrupt */ -#define SYSCFG_ITLINE22_SR_LCD_Pos (0U) +#define SYSCFG_ITLINE22_SR_LCD_Pos (0UL) #define SYSCFG_ITLINE22_SR_LCD_Msk (0x1UL << SYSCFG_ITLINE22_SR_LCD_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE22_SR_LCD SYSCFG_ITLINE22_SR_LCD_Msk /*!< LCD GLB Interrupt */ -#define SYSCFG_ITLINE23_SR_I2C1_Pos (0U) +#define SYSCFG_ITLINE23_SR_I2C1_Pos (0UL) #define SYSCFG_ITLINE23_SR_I2C1_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE23_SR_I2C1 SYSCFG_ITLINE23_SR_I2C1_Msk /*!< I2C1 GLB Interrupt */ -#define SYSCFG_ITLINE24_SR_I2C2_Pos (0U) +#define SYSCFG_ITLINE24_SR_I2C2_Pos (0UL) #define SYSCFG_ITLINE24_SR_I2C2_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE24_SR_I2C2 SYSCFG_ITLINE24_SR_I2C2_Msk /*!< I2C2 GLB Interrupt */ -#define SYSCFG_ITLINE24_SR_I2C4_Pos (1U) +#define SYSCFG_ITLINE24_SR_I2C4_Pos (1UL) #define SYSCFG_ITLINE24_SR_I2C4_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C4_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE24_SR_I2C4 SYSCFG_ITLINE24_SR_I2C4_Msk /*!< I2C3 GLB Interrupt */ -#define SYSCFG_ITLINE24_SR_I2C3_Pos (2U) +#define SYSCFG_ITLINE24_SR_I2C3_Pos (2UL) #define SYSCFG_ITLINE24_SR_I2C3_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C3_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE24_SR_I2C3 SYSCFG_ITLINE24_SR_I2C3_Msk /*!< I2C3 GLB Interrupt -> exti[23]*/ -#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) +#define SYSCFG_ITLINE25_SR_SPI1_Pos (0UL) #define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ -#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U) +#define SYSCFG_ITLINE26_SR_SPI2_Pos (0UL) #define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */ -#define SYSCFG_ITLINE26_SR_SPI3_Pos (1U) +#define SYSCFG_ITLINE26_SR_SPI3_Pos (1UL) #define SYSCFG_ITLINE26_SR_SPI3_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI3_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE26_SR_SPI3 SYSCFG_ITLINE26_SR_SPI3_Msk /*!< SPI3 Interrupt */ -#define SYSCFG_ITLINE27_SR_USART1_Pos (0U) +#define SYSCFG_ITLINE27_SR_USART1_Pos (0UL) #define SYSCFG_ITLINE27_SR_USART1_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE27_SR_USART1 SYSCFG_ITLINE27_SR_USART1_Msk /*!< USART1 GLB Interrupt */ -#define SYSCFG_ITLINE28_SR_USART2_Pos (0U) +#define SYSCFG_ITLINE28_SR_USART2_Pos (0UL) #define SYSCFG_ITLINE28_SR_USART2_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE28_SR_USART2 SYSCFG_ITLINE28_SR_USART2_Msk /*!< USART2 GLB Interrupt */ -#define SYSCFG_ITLINE28_SR_LPUART2_Pos (1U) +#define SYSCFG_ITLINE28_SR_LPUART2_Pos (1UL) #define SYSCFG_ITLINE28_SR_LPUART2_Msk (0x1UL << SYSCFG_ITLINE28_SR_LPUART2_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE28_SR_LPUART2 SYSCFG_ITLINE28_SR_LPUART2_Msk /*!< LPUART2 GLB Interrupt -> exti[31] */ -#define SYSCFG_ITLINE29_SR_USART3_Pos (0U) +#define SYSCFG_ITLINE29_SR_USART3_Pos (0UL) #define SYSCFG_ITLINE29_SR_USART3_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART3_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE29_SR_USART3 SYSCFG_ITLINE29_SR_USART3_Msk /*!< USART3 GLB Interrupt */ -#define SYSCFG_ITLINE29_SR_LPUART1_Pos (1U) +#define SYSCFG_ITLINE29_SR_LPUART1_Pos (1UL) #define SYSCFG_ITLINE29_SR_LPUART1_Msk (0x1UL << SYSCFG_ITLINE29_SR_LPUART1_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE29_SR_LPUART1 SYSCFG_ITLINE29_SR_LPUART1_Msk /*!< LPUART1 GLB Interrupt -> exti[30] */ -#define SYSCFG_ITLINE30_SR_USART4_Pos (0U) +#define SYSCFG_ITLINE30_SR_USART4_Pos (0UL) #define SYSCFG_ITLINE30_SR_USART4_Msk (0x1UL << SYSCFG_ITLINE30_SR_USART4_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE30_SR_USART4 SYSCFG_ITLINE30_SR_USART4_Msk /*!< USART4 GLB Interrupt */ -#define SYSCFG_ITLINE30_SR_LPUART3_Pos (1U) +#define SYSCFG_ITLINE30_SR_LPUART3_Pos (1UL) #define SYSCFG_ITLINE30_SR_LPUART3_Msk (0x1UL << SYSCFG_ITLINE30_SR_LPUART3_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE30_SR_LPUART3 SYSCFG_ITLINE30_SR_LPUART3_Msk /*!< LPUART3 GLB Interrupt */ -#define SYSCFG_ITLINE31_SR_RNG_Pos (0U) +#define SYSCFG_ITLINE31_SR_RNG_Pos (0UL) #define SYSCFG_ITLINE31_SR_RNG_Msk (0x1UL << SYSCFG_ITLINE31_SR_RNG_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE31_SR_RNG SYSCFG_ITLINE31_SR_RNG_Msk /*!< RNG Interrupt */ -#define SYSCFG_ITLINE31_SR_AES_Pos (1U) +#define SYSCFG_ITLINE31_SR_AES_Pos (1UL) #define SYSCFG_ITLINE31_SR_AES_Msk (0x1UL << SYSCFG_ITLINE31_SR_AES_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE31_SR_AES SYSCFG_ITLINE31_SR_AES_Msk /*!< AES Interrupt */ @@ -8115,92 +8110,92 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Pos (0UL) #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!Release Notes for  STM32U0xx C

                                                                                  Update History

                                                                                  - +

                                                                                  Main Changes

                                                                                  • CMSIS Device Maintenance Release version of bits and registers definition aligned with the RM0503 (STM32U0 reference manual).
                                                                                      +
                                                                                    • Added specific linker files for STM32U073xB and STM32U073x8 devices.
                                                                                      • +
                                                                                    • Updated system_stm32u0xx.c file to allow ‘VECT_TAB_OFFSET’ to be overridden externally (by IDE or Makefile).
                                                                                      • +
                                                                                    • BOR bits configuration and definition aligned with the STM32U0 reference manual.
                                                                                      • +
                                                                                    • Rename AES suspend registers according last update in STM32U0 reference manual.
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                                                                                    • +
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                                                                                  + +
                                                                                  +

                                                                                  Main Changes

                                                                                  +
                                                                                    +
                                                                                  • CMSIS Device Maintenance Release version of bits and registers definition aligned with the RM0503 (STM32U0 reference manual). +
                                                                                    • Fixed the right CFGR_HPRE shift in the SystemCoreClockUpdate API.
                                                                                    • Align the ErrorStatus typedef declaration with HAL_StatusTypeDef.
                                                                                    • Add the address to use for the bootloader jump service.
                                                                                  -

                                                                                  +

                                                                                  -

                                                                                  Main Changes

                                                                                  +

                                                                                  Main Changes

                                                                                  • CMSIS Device Maintenance Release version of bits and registers definition aligned with the RM0503 (STM32U0 reference manual).
                                                                                      @@ -55,17 +71,17 @@

                                                                                      Main Changes

                                                                                    • Removed the I2C_CR1_SWRST bit definition.
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                                                                                  -

                                                                                  Main Changes

                                                                                  +

                                                                                  Main Changes

                                                                                  • First official release version of bits and registers definition aligned with the RM0503 (STM32U0 reference manual).
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                                                                                  +

                                                                                  diff --git a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/linker/STM32U073x8_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/linker/STM32U073x8_FLASH.ld new file mode 100644 index 0000000000..80be06cdac --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/linker/STM32U073x8_FLASH.ld @@ -0,0 +1,187 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32U073x8 Device from STM32U0 series +** 64Kbytes FLASH +** 40Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 40K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 64K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/linker/STM32U073xB_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/linker/STM32U073xB_FLASH.ld new file mode 100644 index 0000000000..9877f8de03 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/linker/STM32U073xB_FLASH.ld @@ -0,0 +1,187 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32U073xB Device from STM32U0 series +** 128Kbytes FLASH +** 40Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 40K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/system_stm32u0xx.c b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/system_stm32u0xx.c index ab4b081111..340c680b84 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/system_stm32u0xx.c +++ b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/system_stm32u0xx.c @@ -117,8 +117,10 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ //#define VECT_TAB_SRAM +#if !defined(VECT_TAB_OFFSET) #define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ /*!< Comment the following line if you would like to disable the software workaround related to debug access in case RDP=1 and Boot_Lock=1 */ @@ -327,7 +329,7 @@ void SystemCoreClockUpdate(void) } /* Compute HCLK clock frequency --------------------------------------------*/ /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos) & 0xFU]; + tmp = AHBPrescTable[(((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos) & 0xFU)]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 60808313e5..46e2f4a7c0 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -16,7 +16,7 @@ * STM32L4: 1.7.4 * STM32L5: 1.0.6 * STM32MP1: 1.7.0 - * STM32U0: 1.2.0 + * STM32U0: 1.3.0 * STM32U3: 1.1.0 * STM32U5: 1.4.2 * STM32WB: 1.12.3 From 832a1edf6a9042fbac6a7a4ade3d32718dfb7e95 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 22 Sep 2025 14:36:17 +0200 Subject: [PATCH 16/18] system(u0): update STM32U0xx system Signed-off-by: Frederic Pillon --- system/STM32U0xx/system_stm32u0xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/system/STM32U0xx/system_stm32u0xx.c b/system/STM32U0xx/system_stm32u0xx.c index 46aa24606a..b04d859aa1 100644 --- a/system/STM32U0xx/system_stm32u0xx.c +++ b/system/STM32U0xx/system_stm32u0xx.c @@ -309,7 +309,7 @@ void SystemCoreClockUpdate(void) } /* Compute HCLK clock frequency --------------------------------------------*/ /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U) & 0xFU]; + tmp = AHBPrescTable[(((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos) & 0xFU)]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } From f1432b05b1a919ed270b6edd8b61a55e6a369c7b Mon Sep 17 00:00:00 2001 From: its-kronos <140297693+its-kronos@users.noreply.github.com> Date: Tue, 23 Sep 2025 03:13:33 -0400 Subject: [PATCH 17/18] Add custom devboard - Databoard (#2806) variant(f1): add Databoard Signed-off-by: its-kronos <140297693+its-kronos@users.noreply.github.com> Co-authored-by: Frederic Pillon --- README.md | 1 + boards.txt | 10 + .../F103C8T_F103CB(T-U)/variant_DATABOARD.cpp | 139 +++++++++ .../F103C8T_F103CB(T-U)/variant_DATABOARD.h | 276 ++++++++++++++++++ 4 files changed, 426 insertions(+) create mode 100644 variants/STM32F1xx/F103C8T_F103CB(T-U)/variant_DATABOARD.cpp create mode 100644 variants/STM32F1xx/F103C8T_F103CB(T-U)/variant_DATABOARD.h diff --git a/README.md b/README.md index f92b320621..034c7894a2 100644 --- a/README.md +++ b/README.md @@ -304,6 +304,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32F101ZC
                                                                                  STM32F101ZD
                                                                                  STM32F101ZE | Generic Board | *2.4.0* | | | :green_heart: | STM32F103C6
                                                                                  STM32F103C8
                                                                                  STM32F103CB | [Blue Pill](https://stm32-base.org/boards/STM32F103C8T6-Blue-Pill) | *1.2.0* | USB CDC support since *1.5.0*
                                                                                  Maple bootloaders support since *1.6.0* | | :green_heart: | STM32F103C8
                                                                                  STM32F103CB | [Black Pill](https://stm32-base.org/boards/STM32F103C8T6-Black-Pill) | *1.5.0* | | +| :yellow_heart: | STM32F103C8 | [Databoard](https://github.com/its-kronos/Databoard) | **2.12.0** | | | :green_heart: | STM32F103C4
                                                                                  STM32F103C6
                                                                                  STM32F103C8
                                                                                  STM32F103CB | Generic Board | *1.9.0* | | | :green_heart: | STM32F103R8
                                                                                  STM32F103RB
                                                                                  STM32F103RC
                                                                                  STM32F103RE | [Blue Button F103Rx](https://stm32-base.org/boards/STM32F103RET6-Generic-Board) | *1.9.0* | | | :green_heart: | STM32F103R6
                                                                                  STM32F103R8
                                                                                  STM32F103RB
                                                                                  STM32F103RC
                                                                                  STM32F103RD
                                                                                  STM32F103RE
                                                                                  STM32F103RF
                                                                                  STM32F103RG | Generic Board | *1.9.0* | | diff --git a/boards.txt b/boards.txt index 742e45f479..4e24c37f56 100644 --- a/boards.txt +++ b/boards.txt @@ -2985,6 +2985,16 @@ GenF1.menu.pnum.BLACKPILL_F103CB.build.variant_h=variant_PILL_F103Cx.h GenF1.menu.pnum.BLACKPILL_F103CB.build.variant=STM32F1xx/F103C8T_F103CB(T-U) GenF1.menu.pnum.BLACKPILL_F103CB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F1xx/STM32F103.svd +# Databoard board +GenF1.menu.pnum.DATABOARD=Databoard +GenF1.menu.pnum.DATABOARD.upload.maximum_size=65536 +GenF1.menu.pnum.DATABOARD.upload.maximum_data_size=20480 +GenF1.menu.pnum.DATABOARD.build.board=DATABOARD +GenF1.menu.pnum.DATABOARD.build.product_line=STM32F103xB +GenF1.menu.pnum.DATABOARD.build.variant_h=variant_{build.board}.h +GenF1.menu.pnum.DATABOARD.build.variant=STM32F1xx/F103C8T_F103CB(T-U) +GenF1.menu.pnum.DATABOARD.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F1xx/STM32F103.svd + # VCCGND_F103ZET6_MINI board GenF1.menu.pnum.VCCGND_F103ZET6_MINI=VCCGND F103ZET6 Mini GenF1.menu.pnum.VCCGND_F103ZET6_MINI.upload.maximum_size=524288 diff --git a/variants/STM32F1xx/F103C8T_F103CB(T-U)/variant_DATABOARD.cpp b/variants/STM32F1xx/F103C8T_F103CB(T-U)/variant_DATABOARD.cpp new file mode 100644 index 0000000000..b3f6f06765 --- /dev/null +++ b/variants/STM32F1xx/F103C8T_F103CB(T-U)/variant_DATABOARD.cpp @@ -0,0 +1,139 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_DATABOARD) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25 + PB_10, // D26 + PB_11, // D27 + PB_12, // D28 + PB_13, // D29 + PB_14, // D30 + PB_15, // D31 + PC_13, // D32 + PC_14, // D33 + PC_15, // D34 + PD_0, // D35 + PD_1 // D36 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17 // A9, PB1 +}; + + +// ---------------------------------------------------------------------------- + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief System Clock Configuration + * The system Clock is configured as follow : + * System Clock source = PLL (HSE) + * SYSCLK(Hz) = 72000000 + * HCLK(Hz) = 72000000 + * AHB Prescaler = 1 + * APB1 Prescaler = 2 + * APB2 Prescaler = 1 + * PLL_Source = HSE + * PLL_Mul = 9 + * Flash Latency(WS) = 2 + * ADC Prescaler = 6 + * USB Prescaler = 1.5 + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {}; + + /* Initializes the CPU, AHB and APB busses clocks */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV2; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /* Initializes the CPU, AHB and APB busses clocks */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { + Error_Handler(); + } + + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_USB; + PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; + PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { + Error_Handler(); + } +} + +#ifdef __cplusplus +} +#endif + + + +#endif /* ARDUINO_DATABOARD */ diff --git a/variants/STM32F1xx/F103C8T_F103CB(T-U)/variant_DATABOARD.h b/variants/STM32F1xx/F103C8T_F103CB(T-U)/variant_DATABOARD.h new file mode 100644 index 0000000000..0b9e314959 --- /dev/null +++ b/variants/STM32F1xx/F103C8T_F103CB(T-U)/variant_DATABOARD.h @@ -0,0 +1,276 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 25 +#define PB10 26 +#define PB11 27 +#define PB12 28 +#define PB13 29 +#define PB14 30 +#define PB15 31 +#define PC13 32 +#define PC14 33 +#define PC15 34 +#define PD0 35 +#define PD1 36 + +// Pin Aliases + +#define IO1 PA10 +#define GPIO1 PA10 +#define GP1 PA10 + +#define IO2 PA9 +#define GPIO2 PA9 +#define GP2 PA9 + +#define IO3 PA8 +#define GPIO3 PA8 +#define GP3 PA8 + +#define IO4 PB15 +#define GPIO4 PB15 +#define GP4 PB15 + +#define IO5 PB14 +#define GPIO5 PB14 +#define GP5 PB14 + +#define IO6 PB13 +#define GPIO6 PB13 +#define GP6 PB13 + +#define IO7 PB12 +#define GPIO7 PB12 +#define GP7 PB12 + +#define AIO8 PA7 +#define IO8 PA7 +#define GPIO8 PA7 +#define GP8 PA7 + +#define AIO9 PA6 +#define IO9 PA6 +#define GPIO9 PA6 +#define GP9 PA6 + +#define AIO10 PA5 +#define IO10 PA5 +#define GPIO10 PA5 +#define GP10 PA5 + +#define IO11 PB11 +#define GPIO11 PB11 +#define GP11 PB11 + +#define IO12 PB10 +#define GPIO12 PB10 +#define GP12 PB10 + +#define AIO13 PB1 +#define IO13 PB1 +#define GPIO13 PB1 +#define GP13 PB1 + +#define AIO14 PA4 +#define IO14 PA4 +#define GPIO14 PA4 +#define GP14 PA4 + +#define AIO15 PA3 +#define IO15 PA3 +#define GPIO15 PA3 +#define GP15 PA3 + +#define AIO16 PA2 +#define IO16 PA2 +#define GPIO16 PA2 +#define GP16 PA2 + +#define AIO17 PA1 +#define IO17 PA1 +#define GPIO17 PA1 +#define GP17 PA1 + +#define AIO18 PA0 +#define IO18 PA0 +#define GPIO18 PA0 +#define GP18 PA0 + +#define WIFI_EN PB8 +#define WIFI PB8 +#define WIFI_RX PB7 +#define WIFI_TX PB6 +#define WIFI_BOOT PB9 +#define WIFI_BOOT_EN PB9 +#define WIFI_BOOT_UART PB0 +#define WIFI_BOOT_UART_EN PB0 + +#define MICROSD PB2 +#define MICROSD_EN PB2 +#define MICROSD_MOSI PB5 +#define MICROSD_CLOCK PB3 +#define MICROSD_CLK PB3 +#define MICROSD_MISO PB4 + + + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA8_ALT1 (PA8 | ALT1) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB11_ALT1 (PB11 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) + +#define NUM_DIGITAL_PINS 37 +#define NUM_ANALOG_INPUTS 10 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA15 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB7 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB6 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM3 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM4 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 2 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA3 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA2 +#endif + +#define HSE_VALUE 16000000U // HSE - External Oscillator Frequency in hertz (16MHZ) + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif From 9cc7f13805af2b7939f94a3ae4f7559ff3e533de Mon Sep 17 00:00:00 2001 From: "Zachary J. Fields" Date: Tue, 7 Oct 2025 03:09:01 -0500 Subject: [PATCH 18/18] Define default pins for Cygnet/Swan Serial2/3 (#2826) Co-authored-by: Frederic Pillon Signed-off-by: Zachary J. Fields --- .../L433C(B-C)(T-U)_L443CC(T-U)/variant_CYGNET.h | 8 ++++++++ .../variant_SWAN_R5.h | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/variant_CYGNET.h b/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/variant_CYGNET.h index bc4ff379dd..2b64142628 100644 --- a/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/variant_CYGNET.h +++ b/variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/variant_CYGNET.h @@ -153,6 +153,14 @@ #define PIN_SERIAL_TX PA9 #endif +// Default pin used for generic `Serial2` instance +#ifndef PIN_SERIAL2_RX + #define PIN_SERIAL2_RX PA3_ALT1 +#endif +#ifndef PIN_SERIAL2_TX + #define PIN_SERIAL2_TX PA2_ALT1 +#endif + // LPUART1 #ifndef PIN_SERIAL_LP1_RX #define PIN_SERIAL_LP1_RX PB10 diff --git a/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/variant_SWAN_R5.h b/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/variant_SWAN_R5.h index c4c5b2de0b..01f0144f33 100644 --- a/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/variant_SWAN_R5.h +++ b/variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/variant_SWAN_R5.h @@ -236,6 +236,14 @@ #define PIN_SERIAL_TX PA9 #endif +// Default pin used for generic 'Serial3' instance +#ifndef PIN_SERIAL3_RX + #define PIN_SERIAL3_RX PC5 +#endif +#ifndef PIN_SERIAL3_TX + #define PIN_SERIAL3_TX PC4 +#endif + // LPUART1 #ifndef PIN_SERIAL_LP1_RX #define PIN_SERIAL_LP1_RX PG8