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[pwm] add phase-correct PWM operation mode #37

[pwm] add phase-correct PWM operation mode

[pwm] add phase-correct PWM operation mode #37

Workflow file for this run

name: 'Verilog Conversion'
on:
push:
paths:
- 'rtl/**'
- '.github/workflows/Verilog.yml'
pull_request:
paths:
- 'rtl/**'
- '.github/workflows/Verilog.yml'
workflow_dispatch:
jobs:
convert:
name: '♻️ Convert to Verilog'
runs-on: ubuntu-latest
steps:
- name: 'πŸ“‚ Repository Checkout'
uses: actions/checkout@v6
- name: 'πŸ“¦ Install GHDL'
uses: ghdl/setup-ghdl@v1
with:
version: nightly
backend: mcode
- name: 'βš™οΈ Run conversion'
run: |
make -C rtl/verilog clean convert
- name: 'πŸ“€ Archive generated Verilog code'
if: always()
uses: actions/upload-artifact@v5
with:
name: neorv32_verilog_wrapper
path: rtl/verilog/neorv32_verilog_wrapper.v
sim_iverilog:
name: 'πŸ–₯️ Verilog simulation - Icarus Verilog'
needs: convert
runs-on: ubuntu-latest
steps:
- name: 'πŸ“‚ Repository Checkout'
uses: actions/checkout@v6
- name: 'πŸ“‚ Checkout Conversion Artifact'
uses: actions/download-artifact@v6
with:
name: neorv32_verilog_wrapper
path: rtl/verilog
- name: 'πŸ“¦ Install Icarus Verilog'
run: sudo apt install iverilog
- name: 'βš™οΈ Run Simulation'
run: |
make -C rtl/verilog SIMULATOR=iverilog sim | tee iverilog.log
grep 'Simulation successful!' iverilog.log
sim_verilator:
name: 'πŸ–₯️ Verilog simulation - Verilator'
needs: convert
runs-on: ubuntu-latest
steps:
- name: 'πŸ“‚ Repository Checkout'
uses: actions/checkout@v6
- name: 'πŸ“‚ Checkout Conversion Artifact'
uses: actions/download-artifact@v6
with:
name: neorv32_verilog_wrapper
path: rtl/verilog
- name: 'πŸ“¦ Install Verilator'
run: sudo apt install verilator
- name: 'βš™οΈ Run Simulation'
run: |
make -C rtl/verilog SIMULATOR=verilator sim | tee verilator.log
grep 'Simulation successful!' verilator.log