sudanchapagain

sudan chapagain sudanchapagain

doing something on the information superhighway.

Achievements

4 results for source starred repositories written in Verilog

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Verilog 2,542 322 Updated Apr 27, 2026

Low cost microcontroller + FPGA board for makers , hobbyist and student for endless possibility.

Verilog 371 52 Updated Apr 22, 2026

RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.

Verilog 364 50 Updated Jan 12, 2018

Basic RISC-V Test SoC

Verilog 190 38 Updated Apr 7, 2019