adam-maj / tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
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A minimal GPU design in Verilog to learn how GPUs work from the ground up
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
OpenTitan: Open source silicon root of trust
Common SystemVerilog components
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication